add bitwuzla/cvc5 to hdl-tools-yosys
[dev-env-setup.git] / build_kestrel
1 #!/bin/bash
2 #
3 # Copyright 2022 Raptor Engineering, LLC
4 # Licensed under the terms of the GNU LGPLv3+
5 #
6 # Ensure that the LibreSoC packages and HDL tools
7 # are installed prior to running this script!
8
9 set -e
10
11 echo "Refreshing Python data files from current LibreSoC sources..."
12 cd /home/$SUDO_USER/src/soc
13 python3 src/soc/simple/issuer_verilog.py --fabric-compat --enable-core --enable-mmu --enable-xics --disable-svp64 --disable-pll --debug dmi external_core_top.v
14 cp -Rp external_core_top.v /home/src/kestrel/pythondata-cpu-libresoc/pythondata_cpu_libresoc/hdl/external_core_top.v
15
16 echo "Building Kestrel..."
17 cd /home/$SUDO_USER/src/kestrel/litex-boards/litex_boards/targets
18 ./rcs_arctic_tern_bmc_card.py --device=LFE5UM --cpu-type=libresoc --cpu-variant=standard+irq --with-ethernet --with-video --build --nextpnr-seed 1 --sys-clk-freq=50e6 --remote-ip 192.168.1.1