caveat/FPoperations.def

   1 # Macro Definition                      RM?     FPX?    Softfloat Expression                                            Type    C++ Expression (Host Hardware FP Arithmetic)
   2
   3 @FMADD32( rm, rd, rs1, rs2, rs3)        RM      FPX     FR(rd).f32 = f32_mulAdd( F32(rs1), F32(rs2),  F32(rs3))         n       FR(rd).f =  (FR(rs1).f * FR(rs2).f) + FR(rs3).f; box(rd)
   4 @FMSUB32( rm, rd, rs1, rs2, rs3)        RM      FPX     FR(rd).f32 = f32_mulAdd( F32(rs1), F32(rs2), NF32(rs3))         n       FR(rd).f =  (FR(rs1).f * FR(rs2).f) - FR(rs3).f; box(rd)
   5 @FNMADD32(rm, rd, rs1, rs2, rs3)        RM      FPX     FR(rd).f32 = f32_mulAdd(NF32(rs1), F32(rs2), NF32(rs3))         n       FR(rd).f = -(FR(rs1).f * FR(rs2).f) - FR(rs3).f; box(rd)
   6 @FNMSUB32(rm, rd, rs1, rs2, rs3)        RM      FPX     FR(rd).f32 = f32_mulAdd(NF32(rs1), F32(rs2),  F32(rs3))         n       FR(rd).f = -(FR(rs1).f * FR(rs2).f) + FR(rs3).f; box(rd)
   7
   8 @FMADD64( rm, rd, rs1, rs2, rs3)        RM      FPX     FR(rd).f64 = f64_mulAdd( F64(rs1), F64(rs2),  F64(rs3))         n       FR(rd).d =  (FR(rs1).d * FR(rs2).d) + FR(rs3).d
   9 @FMSUB64( rm, rd, rs1, rs2, rs3)        RM      FPX     FR(rd).f64 = f64_mulAdd( F64(rs1), F64(rs2), NF64(rs3))         n       FR(rd).d =  (FR(rs1).d * FR(rs2).d) - FR(rs3).d
  10 @FNMADD64(rm, rd, rs1, rs2, rs3)        RM      FPX     FR(rd).f64 = f64_mulAdd(NF64(rs1), F64(rs2), NF64(rs3))         n       FR(rd).d = -(FR(rs1).d * FR(rs2).d) - FR(rs3).d
  11 @FNMSUB64(rm, rd, rs1, rs2, rs3)        RM      FPX     FR(rd).f64 = f64_mulAdd(NF64(rs1), F64(rs2),  F64(rs3))         n       FR(rd).d = -(FR(rs1).d * FR(rs2).d) + FR(rs3).d
  12
  13 @FADD32(rm, rd, rs1, rs2)               RM      FPX     FR(rd).f32 = f32_add(F32(rs1), F32(rs2))                        n       FR(rd).f = FR(rs1).f + FR(rs2).f; box(rd)
  14 @FSUB32(rm, rd, rs1, rs2)               RM      FPX     FR(rd).f32 = f32_sub(F32(rs1), F32(rs2))                        n       FR(rd).f = FR(rs1).f - FR(rs2).f; box(rd)
  15 @FMUL32(rm, rd, rs1, rs2)               RM      FPX     FR(rd).f32 = f32_mul(F32(rs1), F32(rs2))                        n       FR(rd).f = FR(rs1).f * FR(rs2).f; box(rd)
  16 @FDIV32(rm, rd, rs1, rs2)               RM      FPX     FR(rd).f32 = f32_div(F32(rs1), F32(rs2))                        n       FR(rd).f = FR(rs1).f / FR(rs2).f; box(rd)
  17
  18 @FADD64(rm, rd, rs1, rs2)               RM      FPX     FR(rd).f64 = f64_add(F64(rs1), F64(rs2))                        n       FR(rd).d = FR(rs1).d + FR(rs2).d
  19 @FSUB64(rm, rd, rs1, rs2)               RM      FPX     FR(rd).f64 = f64_sub(F64(rs1), F64(rs2))                        n       FR(rd).d = FR(rs1).d - FR(rs2).d
  20 @FMUL64(rm, rd, rs1, rs2)               RM      FPX     FR(rd).f64 = f64_mul(F64(rs1), F64(rs2))                        n       FR(rd).d = FR(rs1).d * FR(rs2).d
  21 @FDIV64(rm, rd, rs1, rs2)               RM      FPX     FR(rd).f64 = f64_div(F64(rs1), F64(rs2))                        n       FR(rd).d = FR(rs1).d / FR(rs2).d
  22
  23 @FSQRT32(rm, rd, rs1)                   RM      FPX     FR(rd).f32 = f32_sqrt(F32(rs1))                                 n       FR(rd).f = sqrtf(FR(rs1).f); box(rd)
  24 @FSQRT64(rm, rd, rs1)                   RM      FPX     FR(rd).f64 = f64_sqrt(F64(rs1))                                 n       FR(rd).d = sqrt (FR(rs1).d)
  25
  26 @FCVTWS( rm, rd, rs1)                   RM      FPX     IR(rd).l  = (long)f32_to_i32( F32(rs1), RM, true)               n       IR(rd).l  = (long)(          int)FR(rs1).f
  27 @FCVTWUS(rm, rd, rs1)                   RM      FPX     IR(rd).l  = (long)f32_to_ui32(F32(rs1), RM, true)               n       IR(rd).l  = (long)(unsigned  int)FR(rs1).f
  28 @FCVTLS( rm, rd, rs1)                   RM      FPX     IR(rd).l  =       f32_to_i64( F32(rs1), RM, true)               n       IR(rd).l  =       (         long)FR(rs1).f
  29 @FCVTLUS(rm, rd, rs1)                   RM      FPX     IR(rd).ul =       f32_to_ui64(F32(rs1), RM, true)               n       IR(rd).ul =       (unsigned long)FR(rs1).f
  30
  31 @FCVTWD( rm, rd, rs1)                   RM      FPX     IR(rd).l  = (long)f64_to_i64( F64(rs1), RM, true)               n       IR(rd).l  = (long)(          int)FR(rs1).d
  32 @FCVTWUD(rm, rd, rs1)                   RM      FPX     IR(rd).l  = (long)f64_to_ui64(F64(rs1), RM, true)               n       IR(rd).l  = (long)(unsigned  int)FR(rs1).d
  33 @FCVTLD( rm, rd, rs1)                   RM      FPX     IR(rd).l  =       f64_to_i64( F64(rs1), RM, true)               n       IR(rd).l  =       (         long)FR(rs1).d
  34 @FCVTLUD(rm, rd, rs1)                   RM      FPX     IR(rd).ul =       f64_to_ui64(F64(rs1), RM, true)               n       IR(rd).ul =       (unsigned long)FR(rs1).d
  35
  36 @FCVTSW( rm, rd, rs1)                   RM      FPX     FR(rd).f32 =  i32_to_f32(IR(rs1).i )                            n       FR(rd).f = (float)IR(rs1).i;  box(rd)
  37 @FCVTSWU(rm, rd, rs1)                   RM      FPX     FR(rd).f32 = ui32_to_f32(IR(rs1).ui)                            n       FR(rd).f = (float)IR(rs1).ui; box(rd)
  38 @FCVTSL( rm, rd, rs1)                   RM      FPX     FR(rd).f32 =  i64_to_f32(IR(rs1).l )                            n       FR(rd).f = (float)IR(rs1).l;  box(rd)
  39 @FCVTSLU(rm, rd, rs1)                   RM      FPX     FR(rd).f32 = ui64_to_f32(IR(rs1).ul)                            n       FR(rd).f = (float)IR(rs1).ul; box(rd)
  40
  41 @FCVTDW( rm, rd, rs1)                   RM      FPX     FR(rd).f64 =  i32_to_f64(IR(rs1).i )                            n       FR(rd).d = (double)IR(rs1).i
  42 @FCVTDWU(rm, rd, rs1)                   RM      FPX     FR(rd).f64 = ui32_to_f64(IR(rs1).ui)                            n       FR(rd).d = (double)IR(rs1).ui
  43 @FCVTDL( rm, rd, rs1)                   RM      FPX     FR(rd).f64 =  i64_to_f64(IR(rs1).l )                            n       FR(rd).d = (double)IR(rs1).l
  44 @FCVTDLU(rm, rd, rs1)                   RM      FPX     FR(rd).f64 = ui64_to_f64(IR(rs1).ul)                            n       FR(rd).d = (double)IR(rs1).ul
  45
  46 @FCVTSD(rm, rd, rs1)                    RM      FPX     FR(rd).f32 = f64_to_f32(F64(rs1))                               n       FR(rd).f = (float )FR(rs1).d; box(rd)
  47 @FCVTDS(rm, rd, rs1)                    RM      FPX     FR(rd).f64 = f32_to_f64(F32(rs1))                               n       FR(rd).d = (double)FR(rs1).f
  48
  49 @FEQS(rd, rs1, rs2)                     -       FPX     IR(rd).l = f32_eq(F32(rs1), F32(rs2))                           n       IR(rd).l = (FR(rs1).f == FR(rs2).f) ? 1:0
  50 @FLTS(rd, rs1, rs2)                     -       FPX     IR(rd).l = f32_lt(F32(rs1), F32(rs2))                           n       IR(rd).l = (FR(rs1).f <  FR(rs2).f) ? 1:0
  51 @FLES(rd, rs1, rs2)                     -       FPX     IR(rd).l = f32_le(F32(rs1), F32(rs2))                           n       IR(rd).l = (FR(rs1).f <= FR(rs2).f) ? 1:0
  52
  53 @FEQD(rd, rs1, rs2)                     -       FPX     IR(rd).l = f64_eq(F64(rs1), F64(rs2))                           n       IR(rd).l = (FR(rs1).d == FR(rs2).d) ? 1:0
  54 @FLTD(rd, rs1, rs2)                     -       FPX     IR(rd).l = f64_lt(F64(rs1), F64(rs2))                           n       IR(rd).l = (FR(rs1).d <  FR(rs2).d) ? 1:0
  55 @FLED(rd, rs1, rs2)                     -       FPX     IR(rd).l = f64_le(F64(rs1), F64(rs2))                           n       IR(rd).l = (FR(rs1).d <= FR(rs2).d) ? 1:0
  56
  57 @FMINS(rd, rs1, rs2)                    -       FPX     FR(rd).f32 = f32_min(F32(rs1), F32(rs2))                        n       FR(rd).f = (FR(rs1).f < FR(rs2).f) ? FR(rs1).f : FR(rs2).f; box(rd)
  58 @FMAXS(rd, rs1, rs2)                    -       FPX     FR(rd).f32 = f32_max(F32(rs1), F32(rs2))                        n       FR(rd).f = (FR(rs1).f > FR(rs2).f) ? FR(rs1).f : FR(rs2).f; box(rd)
  59
  60 @FMIND(rd, rs1, rs2)                    -       FPX     FR(rd).f64 = f64_min(F64(rs1), F64(rs2))                        n       FR(rd).d = (FR(rs1).d < FR(rs2).d) ? FR(rs1).d : FR(rs2).d
  61 @FMAXD(rd, rs1, rs2)                    -       FPX     FR(rd).f64 = f64_max(F64(rs1), F64(rs2))                        n       FR(rd).d = (FR(rs1).d > FR(rs2).d) ? FR(rs1).d : FR(rs2).d