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[cavatools.git] / caveat / Instructions.def
1 #
2 # INTEGER/CONTROL UNIT FP/DATA UNIT
3 # f = fused multiply-add
4 # integer multiplier = n m = floating point multiplier
5 # integer divider = e d = floating point divider
6 # a = floating point adder
7 # integer ALU = i j = integer ALU
8 # shifter = s t = shifter
9 # branch unit = b
10 # load unit = r
11 # store unit = w
12 # special unit = x
13 #
14 # C = Compressed Instruction Set
15 # F = Single Precision Floating Point
16 # D = Double Precision Floating Point
17 # A = Atomic Memory Operation
18 #
19 # Upper 16 Bits Lower 16 Bits Opcode Asm Parameters Flag,Operands Execution Statement
20 #------------------------|----------------------------------| ------------ -------------------- -------------------- --------------------------------------
21
22 # 16-Bit Instructions
23 @ 000 {5:4|9:6|2|3} crd[3] 00 C.ADDI4SPN rd,rs1,immed iC,crd+8,SP IR(rd).l = IR(rs1).l + immed
24 @ 001 {5:3} cs1[3] {7:6} cfd[3] 00 C.FLD fd,immed(rs1) rCD,cfd+8,cs1+8 FR(rd).d = LOAD_D(IR(rs1).l+immed, 2)
25 @ 010 {5:3} cs1[3] {2|6} crd[3] 00 C.LW rd,immed(rs1) rC,crd+8,cs1+8 IR(rd).l = LOAD_W(IR(rs1).l+immed, 2)
26 @ 011 {5:3} cs1[3] {7:6} crd[3] 00 C.LD rd,immed(rs1) rC,crd+8,cs1+8 IR(rd).l = LOAD_L(IR(rs1).l+immed, 2)
27 @ 101 {5:3} cs1[3] {7:6} ds2[3] 00 C.FSD fs2,immed(rs1) wCD,-,cs1+8,ds2+8 STORE_D(IR(rs1).l+immed, 2, FR(rs2).d)
28 @ 110 {5:3} cs1[3] {2|6} cs2[3] 00 C.SW rs2,immed(rs1) wC,-,cs1+8,cs2+8 STORE_W(IR(rs1).l+immed, 2, IR(rs2).i)
29 @ 111 {5:3} cs1[3] {7:6} cs2[3] 00 C.SD rs2,immed(rs1) wC,-,cs1+8,cs2+8 STORE_L(IR(rs1).l+immed, 2, IR(rs2).l)
30
31 @ 000 {-5} 00000 {4:0} 01 C.NOP - iC,- { }
32 @ 000 {-5} rd[5] {4:0} 01 C.ADDI rd,immed iC,rd IR(rd).l = IR(rd).l + immed
33 @ 001 {-5} rd[5] {4:0} 01 C.ADDIW rd,immed iC,rd IR(rd).l = (long)(IR(rd).i + immed)
34 @ 010 {-5} rd[5] {4:0} 01 C.LI rd,immed iC,rd IR(rd).l = immed
35 @ 011 {-9} 00010 {4|6|8:7|5} 01 C.ADDI16SP rd,immed iC,rd,SP IR(rd).l = IR(rd).l + immed
36 @ 011 {-17} rd[5] {16:12} 01 C.LUI rd,constant iC,rd IR(rd).l = constant
37
38 @ 100 {5} 00 cs1[3] {4:0} 01 C.SRLI rd,immed sC,cs1+8 IR(rd).ul = IR(rd).ul >> immed
39 @ 100 {5} 01 cs1[3] {4:0} 01 C.SRAI rd,immed sC,cs1+8 IR(rd).l = IR(rd).l >> immed
40 @ 100 {-5} 10 cs1[3] {4:0} 01 C.ANDI rd,immed iC,cs1+8 IR(rd).l = IR(rd).l & immed
41
42 @ 100 0 11 cs1[3] 00 cs2[3] 01 C.SUB rd,rs2 iC,cs1+8,-,cs2+8 IR(rd).l = IR(rd).l - IR(rs2).l
43 @ 100 0 11 cs1[3] 01 cs2[3] 01 C.XOR rd,rs2 iC,cs1+8,-,cs2+8 IR(rd).ul = IR(rd).ul ^ IR(rs2).ul
44 @ 100 0 11 cs1[3] 10 cs2[3] 01 C.OR rd,rs2 iC,cs1+8,-,cs2+8 IR(rd).ul = IR(rd).ul | IR(rs2).ul
45 @ 100 0 11 cs1[3] 11 cs2[3] 01 C.AND rd,rs2 iC,cs1+8,-,cs2+8 IR(rd).ul = IR(rd).ul & IR(rs2).ul
46 @ 100 1 11 cs1[3] 00 cs2[3] 01 C.SUBW rd,rs2 iC,cs1+8,-,cs2+8 IR(rd).l = (long)(IR(rd).i - IR(rs2).i)
47 @ 100 1 11 cs1[3] 01 cs2[3] 01 C.ADDW rd,rs2 iC,cs1+8,-,cs2+8 IR(rd).l = (long)(IR(rd).i + IR(rs2).i)
48
49 @ 101 {-11|4|9:8|10|6|7|3:1|5} 01 C.J immed bC,- GOTO(PC+immed, 2)
50 @ 110 {-8|4:3} cs1[3] {7:6|2:1|5} 01 C.BEQZ rs1,immed bC,-,cs1+8 if (IR(rs1).l == 0) GOTO(PC+immed, 2)
51 @ 111 {-8|4:3} cs1[3] {7:6|2:1|5} 01 C.BNEZ rs1,immed bC,-,cs1+8 if (IR(rs1).l != 0) GOTO(PC+immed, 2)
52
53 @ 000 {5} rd[5] {4:0} 10 C.SLLI rd,immed sC,rd IR(rd).ul = IR(rd).ul << immed
54 @ 001 {5} fd[5] {4:3|8:6} 10 C.FLDSP fd,immed(sp) rDC,fd,SP FR(rd).d = LOAD_D(IR(rs1).l+immed, 2)
55 @ 010 {5} rd[5] {4:2|7:6} 10 C.LWSP rd,immed(sp) rC,rd,SP IR(rd).l = LOAD_W(IR(rs1).l+immed, 2)
56 @ 011 {5} rd[5] {4:3|8:6} 10 C.LDSP rd,immed(sp) rC,rd,SP IR(rd).l = LOAD_L(IR(rs1).l+immed, 2)
57
58 @ 100 0 00001 00000 10 C.RET rd bC,RA RETURN(IR( rd).l, 2)
59 @ 100 0 rd[5] 00000 10 C.JR rd bC,rd GOTO( IR( rd).l, 2)
60 @ 100 1 00000 00000 10 C.EBREAK - bC,RA EBRK(0L, 2)
61 @ 100 1 rd[5] 00000 10 C.JALR rd,rs1 bC,RA,rd CALL( IR(rs1).l, 2)
62
63 @ 100 0 rd[5] crs2[5] 10 C.MV rd,rs2 iC,rd,-,crs2 IR(rd).l = IR(rs2).l
64 @ 100 1 rd[5] crs2[5] 10 C.ADD rd,rs2 iC,rd,-,crs2 IR(rd).l = IR(rd).l + IR(rs2).l
65 @ 101 {5:3|8:6} cfs2[5] 10 C.FSDSP fs2,immed(sp) wCD,-,SP,cfs2 STORE_D(IR(rs1).l+immed, 2, FR(rs2).d)
66 @ 110 {5:2|7:6} crs2[5] 10 C.SWSP rs2,immed(sp) wC,-,SP,crs2 STORE_W(IR(rs1).l+immed, 2, IR(rs2).i)
67 @ 111 {5:3|8:6} crs2[5] 10 C.SDSP rs2,immed(sp) wC,-,SP,crs2 STORE_L(IR(rs1).l+immed, 2, IR(rs2).l)
68
69
70 # 32-Bit Instructions
71
72 @ {-11:0} rs1[5] 000 rd[5] 00000 11 LB rd,immed(rs1) r,rd,rs1 IR(rd).l = (long)LOAD_B( IR(rs1).l+immed, 4)
73 @ {-11:0} rs1[5] 001 rd[5] 00000 11 LH rd,immed(rs1) r,rd,rs1 IR(rd).l = (long)LOAD_H( IR(rs1).l+immed, 4)
74 @ {-11:0} rs1[5] 010 rd[5] 00000 11 LW rd,immed(rs1) r,rd,rs1 IR(rd).l = LOAD_W( IR(rs1).l+immed, 4)
75 @ {-11:0} rs1[5] 011 rd[5] 00000 11 LD rd,immed(rs1) r,rd,rs1 IR(rd).l = LOAD_L( IR(rs1).l+immed, 4)
76 @ {-11:0} rs1[5] 100 rd[5] 00000 11 LBU rd,immed(rs1) r,rd,rs1 IR(rd).ul = (unsigned long)LOAD_UB(IR(rs1).l+immed, 4)
77 @ {-11:0} rs1[5] 101 rd[5] 00000 11 LHU rd,immed(rs1) r,rd,rs1 IR(rd).ul = (unsigned long)LOAD_UH(IR(rs1).l+immed, 4)
78 @ {-11:0} rs1[5] 110 rd[5] 00000 11 LWU rd,immed(rs1) r,rd,rs1 IR(rd).ul = LOAD_UW(IR(rs1).l+immed, 4)
79 @ {-11:0} rs1[5] 010 fd[5] 00001 11 FLW fd,immed(rs1) rF,fd,rs1 FR(rd).f = LOAD_F( IR(rs1).l+immed, 4); box(rd)
80 @ {-11:0} rs1[5] 011 fd[5] 00001 11 FLD fd,immed(rs1) rD,fd,rs1 FR(rd).d = LOAD_D( IR(rs1).l+immed, 4)
81
82 @ {-11:5} rs2[5] rs1[5] 000 {4:0} 01000 11 SB rs2,immed(rs1) w,-,rs1,rs2 STORE_B(IR(rs1).l+immed, 4, IR(rs2).l)
83 @ {-11:5} rs2[5] rs1[5] 001 {4:0} 01000 11 SH rs2,immed(rs1) w,-,rs1,rs2 STORE_H(IR(rs1).l+immed, 4, IR(rs2).l)
84 @ {-11:5} rs2[5] rs1[5] 010 {4:0} 01000 11 SW rs2,immed(rs1) w,-,rs1,rs2 STORE_W(IR(rs1).l+immed, 4, IR(rs2).l)
85 @ {-11:5} rs2[5] rs1[5] 011 {4:0} 01000 11 SD rs2,immed(rs1) w,-,rs1,rs2 STORE_L(IR(rs1).l+immed, 4, IR(rs2).l)
86 @ {-11:5} fs2[5] rs1[5] 010 {4:0} 01001 11 FSW fs2,immed(rs1) wF,-,rs1,fs2 STORE_F(IR(rs1).l+immed, 4, FR(rs2).f)
87 @ {-11:5} fs2[5] rs1[5] 011 {4:0} 01001 11 FSD fs2,immed(rs1) wD,-,rs1,fs2 STORE_D(IR(rs1).l+immed, 4, FR(rs2).d)
88
89 @ {-12|10:5} rs2[5] rs1[5] 000 {4:1|11} 11000 11 BEQ rs1,rs2,immed b,-,rs1,rs2 if (IR(rs1).l == IR(rs2).l ) GOTO(PC+immed, 4)
90 @ {-12|10:5} rs2[5] rs1[5] 001 {4:1|11} 11000 11 BNE rs1,rs2,immed b,-,rs1,rs2 if (IR(rs1).l != IR(rs2).l ) GOTO(PC+immed, 4)
91 @ {-12|10:5} rs2[5] rs1[5] 100 {4:1|11} 11000 11 BLT rs1,rs2,immed b,-,rs1,rs2 if (IR(rs1).l < IR(rs2).l ) GOTO(PC+immed, 4)
92 @ {-12|10:5} rs2[5] rs1[5] 101 {4:1|11} 11000 11 BGE rs1,rs2,immed b,-,rs1,rs2 if (IR(rs1).l >= IR(rs2).l ) GOTO(PC+immed, 4)
93 @ {-12|10:5} rs2[5] rs1[5] 110 {4:1|11} 11000 11 BLTU rs1,rs2,immed b,-,rs1,rs2 if (IR(rs1).ul < IR(rs2).ul) GOTO(PC+immed, 4)
94 @ {-12|10:5} rs2[5] rs1[5] 111 {4:1|11} 11000 11 BGEU rs1,rs2,immed b,-,rs1,rs2 if (IR(rs1).ul >= IR(rs2).ul) GOTO(PC+immed, 4)
95
96 @ 000000000000 00001 000 00000 11001 11 RET rs1 b,-,RA RETURN(IR(rs1).l + immed & ~0x1L, 4)
97 @ {-11:0} rs1[5] 000 00000 11001 11 JR rs1,immed b,-,rs1 GOTO(( IR(rs1).l + immed) & ~0x1L, 4)
98 @ {-11:0} rs1[5] 000 rd[5] 11001 11 JALR rd,rs1,immed b,rd,rs1 CALL(( IR(rs1).l + immed) & ~0x1L, 4)
99 @ {-20|10:1|11|19:12} 00000 11011 11 J constant b,- GOTO( PC + constant, 4)
100 @ {-20|10:1|11|19:12} rd[5] 11011 11 JAL rd,constant b,rd CALL( PC + constant, 4)
101
102 @ {-11:0} 00000 000 rd[5] 00100 11 LI rd,immed i,rd IR(rd).l = immed
103 @ {-31:12} rd[5] 01101 11 LUI rd,constant i,rd IR(rd).l = constant
104 @ {-31:12} rd[5] 00101 11 AUIPC rd,constant i,rd IR(rd).l = constant + PC
105
106 @ {-11:0} rs1[5] 000 rd[5] 00100 11 ADDI rd,rs1,immed i,rd,rs1 IR(rd).l = IR(rs1).l + immed
107 @ 000000 {5:0} rs1[5] 001 rd[5] 00100 11 SLLI rd,rs1,immed s,rd,rs1 IR(rd).ul = IR(rs1).ul << immed
108 @ {-11:0} rs1[5] 010 rd[5] 00100 11 SLTI rd,rs1,immed i,rd,rs1 IR(rd).l = (IR(rs1).l < immed) ? 1:0
109 @ {-11:0} rs1[5] 011 rd[5] 00100 11 SLTIU rd,rs1,immed i,rd,rs1 IR(rd).ul = (IR(rs1).ul < (unsigned long)immed) ? 1:0
110 @ {-11:0} rs1[5] 100 rd[5] 00100 11 XORI rd,rs1,immed i,rd,rs1 IR(rd).l = IR(rs1).l ^ immed
111 @ 000000 {5:0} rs1[5] 101 rd[5] 00100 11 SRLI rd,rs1,immed s,rd,rs1 IR(rd).ul = IR(rs1).ul >> immed
112 @ 010000 {5:0} rs1[5] 101 rd[5] 00100 11 SRAI rd,rs1,immed s,rd,rs1 IR(rd).l = IR(rs1).l >> immed
113 @ {-11:0} rs1[5] 110 rd[5] 00100 11 ORI rd,rs1,immed i,rd,rs1 IR(rd).l = IR(rs1).l | immed
114 @ {-11:0} rs1[5] 111 rd[5] 00100 11 ANDI rd,rs1,immed i,rd,rs1 IR(rd).l = IR(rs1).l & immed
115
116 @ {-11:0} rs1[5] 000 rd[5] 00110 11 ADDIW rd,rs1,immed i,rd,rs1 IR(rd).l = (long)(IR(rs1).i + immed)
117 @ 0000000 {4:0} rs1[5] 001 rd[5] 00110 11 SLLIW rd,rs1,immed s,rd,rs1 IR(rd).l = (long)(IR(rs1).ui << immed)
118 @ 0000000 {4:0} rs1[5] 101 rd[5] 00110 11 SRLIW rd,rs1,immed s,rd,rs1 IR(rd).l = (long)(IR(rs1).ui >> immed)
119 @ 0100000 {4:0} rs1[5] 101 rd[5] 00110 11 SRAIW rd,rs1,immed s,rd,rs1 IR(rd).l = (long)(IR(rs1).i >> immed)
120
121 @ 0000000 rs2[5] rs1[5] 000 rd[5] 01100 11 ADD rd,rs1,rs2 i,rd,rs1,rs2 IR(rd).l = IR(rs1).l + IR(rs2).l
122 @ 0100000 rs2[5] rs1[5] 000 rd[5] 01100 11 SUB rd,rs1,rs2 i,rd,rs1,rs2 IR(rd).l = IR(rs1).l - IR(rs2).l
123 @ 0000000 rs2[5] rs1[5] 001 rd[5] 01100 11 SLL rd,rs1,rs2 s,rd,rs1,rs2 IR(rd).ul = IR(rs1).ul << IR(rs2).ul
124 @ 0000000 rs2[5] rs1[5] 010 rd[5] 01100 11 SLT rd,rs1,rs2 i,rd,rs1,rs2 IR(rd).l = (IR(rs1).l < IR(rs2).l ) ? 1:0;
125 @ 0000000 rs2[5] rs1[5] 011 rd[5] 01100 11 SLTU rd,rs1,rs2 i,rd,rs1,rs2 IR(rd).l = (IR(rs1).ul < IR(rs2).ul) ? 1:0;
126 @ 0000000 rs2[5] rs1[5] 100 rd[5] 01100 11 XOR rd,rs1,rs2 i,rd,rs1,rs2 IR(rd).ul = IR(rs1).ul ^ IR(rs2).ul
127 @ 0000000 rs2[5] rs1[5] 101 rd[5] 01100 11 SRL rd,rs1,rs2 s,rd,rs1,rs2 IR(rd).ul = IR(rs1).ul >> IR(rs2).ul
128 @ 0100000 rs2[5] rs1[5] 101 rd[5] 01100 11 SRA rd,rs1,rs2 s,rd,rs1,rs2 IR(rd).l = IR(rs1).l >> IR(rs2).l
129 @ 0000000 rs2[5] rs1[5] 110 rd[5] 01100 11 OR rd,rs1,rs2 i,rd,rs1,rs2 IR(rd).ul = IR(rs1).ul | IR(rs2).ul
130 @ 0000000 rs2[5] rs1[5] 111 rd[5] 01100 11 AND rd,rs1,rs2 i,rd,rs1,rs2 IR(rd).ul = IR(rs1).ul & IR(rs2).ul
131
132 @ 0000000 rs2[5] rs1[5] 000 rd[5] 01110 11 ADDW rd,rs1,rs2 i,rd,rs1,rs2 IR(rd).l = (long)(IR(rs1).i + IR(rs2).i)
133 @ 0100000 rs2[5] rs1[5] 000 rd[5] 01110 11 SUBW rd,rs1,rs2 i,rd,rs1,rs2 IR(rd).l = (long)(IR(rs1).i - IR(rs2).i)
134 @ 0000000 rs2[5] rs1[5] 001 rd[5] 01110 11 SLLW rd,rs1,rs2 s,rd,rs1,rs2 IR(rd).l = (long)(IR(rs1).ui << IR(rs2).ui)
135 @ 0000000 rs2[5] rs1[5] 101 rd[5] 01110 11 SRLW rd,rs1,rs2 s,rd,rs1,rs2 IR(rd).l = (long)(IR(rs1).ui >> IR(rs2).ui)
136 @ 0100000 rs2[5] rs1[5] 101 rd[5] 01110 11 SRAW rd,rs1,rs2 s,rd,rs1,rs2 IR(rd).l = (long)(IR(rs1).i >> IR(rs2).i)
137
138 @ 0000001 rs2[5] rs1[5] 000 rd[5] 01100 11 MUL rd,rs1,rs2 n,rd,rs1,rs2 IR(rd).l = IR(rs1).l * IR(rs2).l
139 @ 0000001 rs2[5] rs1[5] 001 rd[5] 01100 11 MULH rd,rs1,rs2 n,rd,rs1,rs2 IR(rd).l = mulh (IR(rs1).l, IR(rs2).l )
140 @ 0000001 rs2[5] rs1[5] 010 rd[5] 01100 11 MULHSU rd,rs1,rs2 n,rd,rs1,rs2 IR(rd).l = mulhsu(IR(rs1).l, IR(rs2).ul)
141 @ 0000001 rs2[5] rs1[5] 011 rd[5] 01100 11 MULHU rd,rs1,rs2 n,rd,rs1,rs2 IR(rd).ul = mulhu (IR(rs1).ul, IR(rs2).ul)
142 @ 0000001 rs2[5] rs1[5] 100 rd[5] 01100 11 DIV rd,rs1,rs2 t,rd,rs1,rs2 IR(rd).l = IR(rs1).l / IR(rs2).l
143 @ 0000001 rs2[5] rs1[5] 101 rd[5] 01100 11 DIVU rd,rs1,rs2 t,rd,rs1,rs2 IR(rd).ul = IR(rs1).ul / IR(rs2).ul
144 @ 0000001 rs2[5] rs1[5] 110 rd[5] 01100 11 REM rd,rs1,rs2 t,rd,rs1,rs2 IR(rd).l = IR(rs1).l % IR(rs2).l
145 @ 0000001 rs2[5] rs1[5] 111 rd[5] 01100 11 REMU rd,rs1,rs2 t,rd,rs1,rs2 IR(rd).ul = IR(rs1).ul % IR(rs2).ul
146
147 @ 0000001 rs2[5] rs1[5] 000 rd[5] 01110 11 MULW rd,rs1,rs2 n,rd,rs1,rs2 IR(rd).l = (long)(IR(rs1).i * IR(rs2).i)
148 @ 0000001 rs2[5] rs1[5] 100 rd[5] 01110 11 DIVW rd,rs1,rs2 t,rd,rs1,rs2 IR(rd).l = (long)(IR(rs1).i / IR(rs2).i)
149 @ 0000001 rs2[5] rs1[5] 101 rd[5] 01110 11 DIVUW rd,rs1,rs2 t,rd,rs1,rs2 IR(rd).l = (long)(IR(rs1).ui / IR(rs2).ui)
150 @ 0000001 rs2[5] rs1[5] 110 rd[5] 01110 11 REMW rd,rs1,rs2 t,rd,rs1,rs2 IR(rd).l = (long)(IR(rs1).i % IR(rs2).i)
151 @ 0000001 rs2[5] rs1[5] 111 rd[5] 01110 11 REMUW rd,rs1,rs2 t,rd,rs1,rs2 IR(rd).l = (long)(IR(rs1).ui % IR(rs2).ui)
152
153
154 # Floating point
155
156
157 @ fs3[5] 00 fs2[5] fs1[5] 111 fd[5] 10000 11 FMADD_dyn.S fd,fs1,fs2,fs3 fF,fd,fs1,fs2,fs3 FMADD32_dyn(rd, rs1, rs2, rs3)
158 @ fs3[5] 00 fs2[5] fs1[5] 111 fd[5] 10001 11 FMSUB_dyn.S fd,fs1,fs2,fs3 fF,fd,fs1,fs2,fs3 FMSUB32_dyn(rd, rs1, rs2, rs3)
159 @ fs3[5] 00 fs2[5] fs1[5] 111 fd[5] 10010 11 FNMSUB_dyn.S fd,fs1,fs2,fs3 fF,fd,fs1,fs2,fs3 FNMSUB32_dyn(rd, rs1, rs2, rs3)
160 @ fs3[5] 00 fs2[5] fs1[5] 111 fd[5] 10011 11 FNMADD_dyn.S fd,fs1,fs2,rs3 fF,fd,fs1,fs2,fs3 FNMADD32_dyn(rd, rs1, rs2, rs3)
161 @ 0000000 fs2[5] fs1[5] 111 fd[5] 10100 11 FADD_dyn.S fd,fs1,fs2 aF,fd,fs1,fs2 FADD32_dyn(rd, rs1, rs2)
162 @ 0000100 fs2[5] fs1[5] 111 fd[5] 10100 11 FSUB_dyn.S fd,fs1,fs2 aF,fd,fs1,fs2 FSUB32_dyn(rd, rs1, rs2)
163 @ 0001000 fs2[5] fs1[5] 111 fd[5] 10100 11 FMUL_dyn.S fd,fs1,fs2 mF,fd,fs1,fs2 FMUL32_dyn(rd, rs1, rs2)
164 @ 0001100 fs2[5] fs1[5] 111 fd[5] 10100 11 FDIV_dyn.S fd,fs1,fs2 dF,fd,fs1,fs2 FDIV32_dyn(rd, rs1, rs2)
165 @ 0101100 00000 fs1[5] 111 fd[5] 10100 11 FSQRT_dyn.S fd,fs1 dF,fd,fs1 FSQRT32_dyn(rd, rs1)
166
167 @ 1100000 00000 fs1[5] 111 rd[5] 10100 11 FCVT_dyn.W.S rd,fs1 aF,rd,fs1 FCVTWS_dyn(rd, rs1)
168 @ 1100000 00001 fs1[5] 111 rd[5] 10100 11 FCVT_dyn.WU.S rd,fs1 aF,rd,fs1 FCVTWUS_dyn(rd, rs1)
169 @ 1100000 00010 fs1[5] 111 rd[5] 10100 11 FCVT_dyn.L.S rd,fs1 aF,rd,fs1 FCVTLS_dyn(rd, rs1)
170 @ 1100000 00011 fs1[5] 111 rd[5] 10100 11 FCVT_dyn.LU.S rd,fs1 aF,rd,fs1 FCVTLUS_dyn(rd, rs1)
171 @ 1101000 00000 rs1[5] 111 fd[5] 10100 11 FCVT_dyn.S.W fd,rs1 aF,fd,rs1 FCVTSW_dyn(rd, rs1)
172 @ 1101000 00001 rs1[5] 111 fd[5] 10100 11 FCVT_dyn.S.WU fd,rs1 aF,fd,rs1 FCVTSWU_dyn(rd, rs1)
173 @ 1101000 00010 rs1[5] 111 fd[5] 10100 11 FCVT_dyn.S.L fd,rs1 aF,fd,rs1 FCVTSL_dyn(rd, rs1)
174 @ 1101000 00011 rs1[5] 111 fd[5] 10100 11 FCVT_dyn.S.LU fd,rs1 aF,fd,rs1 FCVTSLU_dyn(rd, rs1)
175
176 @ fs3[5] 01 fs2[5] fs1[5] 111 fd[5] 10000 11 FMADD_dyn.D fd,fs1,fs2,fs3 fD,fd,fs1,fs2,fs3 FMADD64_dyn(rd, rs1, rs2, rs3)
177 @ fs3[5] 01 fs2[5] fs1[5] 111 fd[5] 10001 11 FMSUB_dyn.D fd,fs1,fs2,fs3 fD,fd,fs1,fs2,fs3 FMSUB64_dyn(rd, rs1, rs2, rs3)
178 @ fs3[5] 01 fs2[5] fs1[5] 111 fd[5] 10010 11 FNMSUB_dyn.D fd,fs1,fs2,fs3 fD,fd,fs1,fs2,fs3 FNMSUB64_dyn(rd, rs1, rs2, rs3)
179 @ fs3[5] 01 fs2[5] fs1[5] 111 fd[5] 10011 11 FNMADD_dyn.D fd,fs1,fs2,fs3 fD,fd,fs1,fs2,fs3 FNMADD64_dyn(rd, rs1, rs2, rs3)
180 @ 0000001 fs2[5] fs1[5] 111 fd[5] 10100 11 FADD_dyn.D fd,fs1,fs2 aD,fd,fs1,fs2 FADD64_dyn(rd, rs1, rs2)
181 @ 0000101 fs2[5] fs1[5] 111 fd[5] 10100 11 FSUB_dyn.D fd,fs1,fs2 aD,fd,fs1,fs2 FSUB64_dyn(rd, rs1, rs2)
182 @ 0001001 fs2[5] fs1[5] 111 fd[5] 10100 11 FMUL_dyn.D fd,fs1,fs2 mD,fd,fs1,fs2 FMUL64_dyn(rd, rs1, rs2)
183 @ 0001101 fs2[5] fs1[5] 111 fd[5] 10100 11 FDIV_dyn.D fd,fs1,fs2 dD,fd,fs1,fs2 FDIV64_dyn(rd, rs1, rs2)
184 @ 0101101 00000 fs1[5] 111 fd[5] 10100 11 FSQRT_dyn.D fd,fs1 dD,fd,fs1 FSQRT64_dyn(rd, rs1)
185
186 @ 1100001 00000 fs1[5] 111 rd[5] 10100 11 FCVT_dyn.W.D rd,fs1 aD,rd,fs1 FCVTWD_dyn(rd, rs1)
187 @ 1100001 00001 fs1[5] 111 rd[5] 10100 11 FCVT_dyn.WU.D rd,fs1 aD,rd,fs1 FCVTWUD_dyn(rd, rs1)
188 @ 1100001 00010 fs1[5] 111 rd[5] 10100 11 FCVT_dyn.L.D rd,fs1 aD,rd,fs1 FCVTLD_dyn(rd, rs1)
189 @ 1100001 00011 fs1[5] 111 rd[5] 10100 11 FCVT_dyn.LU.D rd,fs1 aD,rd,fs1 FCVTLUD_dyn(rd, rs1)
190 @ 1101001 00000 rs1[5] 111 fd[5] 10100 11 FCVT_dyn.D.W fd,rs1 aD,fd,rs1 FCVTDW_dyn(rd, rs1)
191 @ 1101001 00001 rs1[5] 111 fd[5] 10100 11 FCVT_dyn.D.WU fd,rs1 aD,fd,rs1 FCVTDWU_dyn(rd, rs1)
192 @ 1101001 00010 rs1[5] 111 fd[5] 10100 11 FCVT_dyn.D.L fd,rs1 aD,fd,rs1 FCVTDL_dyn(rd, rs1)
193 @ 1101001 00011 rs1[5] 111 fd[5] 10100 11 FCVT_dyn.D.LU fd,rs1 aD,fd,rs1 FCVTDLU_dyn(rd, rs1)
194
195 @ 0100000 00001 fs1[5] 111 rd[5] 10100 11 FCVT_dyn.S.D fd,fs1 aD,rd,fs1 FCVTSD_dyn(rd, rs1)
196 @ 0100001 00000 fs1[5] 111 rd[5] 10100 11 FCVT_dyn.D.S fd,fs1 aD,rd,fs1 FCVTDS_dyn(rd, rs1)
197
198
199
200
201
202
203
204
205 @ fs3[5] 00 fs2[5] fs1[5] {2:0} fd[5] 10000 11 FMADD_rm.S fd,fs1,fs2,fs3 fF,fd,fs1,fs2,fs3 FMADD32(immed, rd, rs1, rs2, rs3)
206 @ fs3[5] 00 fs2[5] fs1[5] {2:0} fd[5] 10001 11 FMSUB_rm.S fd,fs1,fs2,fs3 fF,fd,fs1,fs2,fs3 FMSUB32(immed, rd, rs1, rs2, rs3)
207 @ fs3[5] 00 fs2[5] fs1[5] {2:0} fd[5] 10010 11 FNMSUB_rm.S fd,fs1,fs2,fs3 fF,fd,fs1,fs2,fs3 FNMSUB32(immed, rd, rs1, rs2, rs3)
208 @ fs3[5] 00 fs2[5] fs1[5] {2:0} fd[5] 10011 11 FNMADD_rm.S fd,fs1,fs2,rs3 fF,fd,fs1,fs2,fs3 FNMADD32(immed, rd, rs1, rs2, rs3)
209 @ 0000000 fs2[5] fs1[5] {2:0} fd[5] 10100 11 FADD_rm.S fd,fs1,fs2 aF,fd,fs1,fs2 FADD32(immed, rd, rs1, rs2)
210 @ 0000100 fs2[5] fs1[5] {2:0} fd[5] 10100 11 FSUB_rm.S fd,fs1,fs2 aF,fd,fs1,fs2 FSUB32(immed, rd, rs1, rs2)
211 @ 0001000 fs2[5] fs1[5] {2:0} fd[5] 10100 11 FMUL_rm.S fd,fs1,fs2 mF,fd,fs1,fs2 FMUL32(immed, rd, rs1, rs2)
212 @ 0001100 fs2[5] fs1[5] {2:0} fd[5] 10100 11 FDIV_rm.S fd,fs1,fs2 dF,fd,fs1,fs2 FDIV32(immed, rd, rs1, rs2)
213 @ 0101100 00000 fs1[5] {2:0} fd[5] 10100 11 FSQRT_rm.S fd,fs1 dF,fd,fs1 FSQRT32(immed, rd, rs1)
214
215 @ 1100000 00000 fs1[5] {2:0} rd[5] 10100 11 FCVT_rm.W.S rd,fs1 aF,rd,fs1 FCVTWS(immed, rd, rs1)
216 @ 1100000 00001 fs1[5] {2:0} rd[5] 10100 11 FCVT_rm.WU.S rd,fs1 aF,rd,fs1 FCVTWUS(immed, rd, rs1)
217 @ 1100000 00010 fs1[5] {2:0} rd[5] 10100 11 FCVT_rm.L.S rd,fs1 aF,rd,fs1 FCVTLS(immed, rd, rs1)
218 @ 1100000 00011 fs1[5] {2:0} rd[5] 10100 11 FCVT_rm.LU.S rd,fs1 aF,rd,fs1 FCVTLUS(immed, rd, rs1)
219 @ 1101000 00000 rs1[5] {2:0} fd[5] 10100 11 FCVT_rm.S.W fd,rs1 aF,fd,rs1 FCVTSW(immed, rd, rs1)
220 @ 1101000 00001 rs1[5] {2:0} fd[5] 10100 11 FCVT_rm.S.WU fd,rs1 aF,fd,rs1 FCVTSWU(immed, rd, rs1)
221 @ 1101000 00010 rs1[5] {2:0} fd[5] 10100 11 FCVT_rm.S.L fd,rs1 aF,fd,rs1 FCVTSL(immed, rd, rs1)
222 @ 1101000 00011 rs1[5] {2:0} fd[5] 10100 11 FCVT_rm.S.LU fd,rs1 aF,fd,rs1 FCVTSLU(immed, rd, rs1)
223
224 @ fs3[5] 01 fs2[5] fs1[5] {2:0} fd[5] 10000 11 FMADD_rm.D fd,fs1,fs2,fs3 fD,fd,fs1,fs2,fs3 FMADD64(immed, rd, rs1, rs2, rs3)
225 @ fs3[5] 01 fs2[5] fs1[5] {2:0} fd[5] 10001 11 FMSUB_rm.D fd,fs1,fs2,fs3 fD,fd,fs1,fs2,fs3 FMSUB64(immed, rd, rs1, rs2, rs3)
226 @ fs3[5] 01 fs2[5] fs1[5] {2:0} fd[5] 10010 11 FNMSUB_rm.D fd,fs1,fs2,fs3 fD,fd,fs1,fs2,fs3 FNMSUB64(immed, rd, rs1, rs2, rs3)
227 @ fs3[5] 01 fs2[5] fs1[5] {2:0} fd[5] 10011 11 FNMADD_rm.D fd,fs1,fs2,fs3 fD,fd,fs1,fs2,fs3 FNMADD64(immed, rd, rs1, rs2, rs3)
228 @ 0000001 fs2[5] fs1[5] {2:0} fd[5] 10100 11 FADD_rm.D fd,fs1,fs2 aD,fd,fs1,fs2 FADD64(immed, rd, rs1, rs2)
229 @ 0000101 fs2[5] fs1[5] {2:0} fd[5] 10100 11 FSUB_rm.D fd,fs1,fs2 aD,fd,fs1,fs2 FSUB64(immed, rd, rs1, rs2)
230 @ 0001001 fs2[5] fs1[5] {2:0} fd[5] 10100 11 FMUL_rm.D fd,fs1,fs2 mD,fd,fs1,fs2 FMUL64(immed, rd, rs1, rs2)
231 @ 0001101 fs2[5] fs1[5] {2:0} fd[5] 10100 11 FDIV_rm.D fd,fs1,fs2 dD,fd,fs1,fs2 FDIV64(immed, rd, rs1, rs2)
232 @ 0101101 00000 fs1[5] {2:0} fd[5] 10100 11 FSQRT_rm.D fd,fs1 dD,fd,fs1 FSQRT64(immed, rd, rs1)
233
234 @ 1100001 00000 fs1[5] {2:0} rd[5] 10100 11 FCVT_rm.W.D rd,fs1 aD,rd,fs1 FCVTWD(immed, rd, rs1)
235 @ 1100001 00001 fs1[5] {2:0} rd[5] 10100 11 FCVT_rm.WU.D rd,fs1 aD,rd,fs1 FCVTWUD(immed, rd, rs1)
236 @ 1100001 00010 fs1[5] {2:0} rd[5] 10100 11 FCVT_rm.L.D rd,fs1 aD,rd,fs1 FCVTLD(immed, rd, rs1)
237 @ 1100001 00011 fs1[5] {2:0} rd[5] 10100 11 FCVT_rm.LU.D rd,fs1 aD,rd,fs1 FCVTLUD(immed, rd, rs1)
238 @ 1101001 00000 rs1[5] {2:0} fd[5] 10100 11 FCVT_rm.D.W fd,rs1 aD,fd,rs1 FCVTDW(immed, rd, rs1)
239 @ 1101001 00001 rs1[5] {2:0} fd[5] 10100 11 FCVT_rm.D.WU fd,rs1 aD,fd,rs1 FCVTDWU(immed, rd, rs1)
240 @ 1101001 00010 rs1[5] {2:0} fd[5] 10100 11 FCVT_rm.D.L fd,rs1 aD,fd,rs1 FCVTDL(immed, rd, rs1)
241 @ 1101001 00011 rs1[5] {2:0} fd[5] 10100 11 FCVT_rm.D.LU fd,rs1 aD,fd,rs1 FCVTDLU(immed, rd, rs1)
242
243 @ 0100000 00001 fs1[5] {2:0} rd[5] 10100 11 FCVT_rm.S.D fd,fs1 aD,rd,fs1 FCVTSD(immed, rd, rs1)
244 @ 0100001 00000 fs1[5] {2:0} rd[5] 10100 11 FCVT_rm.D.S fd,fs1 aD,rd,fs1 FCVTDS(immed, rd, rs1)
245
246
247
248
249
250
251 @ 1010000 fs2[5] fs1[5] 010 rd[5] 10100 11 FEQ.S rd,fs1,fs2 jF,rd,fs1,fs2 FEQS(rd, rs1, rs2)
252 @ 1010000 fs2[5] fs1[5] 001 rd[5] 10100 11 FLT.S rd,fs1,fs2 jF,rd,fs1,fs2 FLTS(rd, rs1, rs2)
253 @ 1010000 fs2[5] fs1[5] 000 rd[5] 10100 11 FLE.S rd,fs1,fs2 jF,rd,fs1,fs2 FLES(rd, rs1, rs2)
254 @ 0010100 fs2[5] fs1[5] 000 fd[5] 10100 11 FMIN.S fd,fs1,fs2 jF,fd,fs1,fs2 FMINS(rd, rs1, rs2)
255 @ 0010100 fs2[5] fs1[5] 001 fd[5] 10100 11 FMAX.S fd,fs1,fs2 jF,fd,fs1,fs2 FMAXS(rd, rs1, rs2)
256
257 @ 1010001 fs2[5] fs1[5] 010 rd[5] 10100 11 FEQ.D rd,fs1,fs2 jD,rd,fs1,fs2 FEQD(rd, rs1, rs2)
258 @ 1010001 fs2[5] fs1[5] 001 rd[5] 10100 11 FLT.D rd,fs1,fs2 jD,rd,fs1,fs2 FLTD(rd, rs1, rs2)
259 @ 1010001 fs2[5] fs1[5] 000 rd[5] 10100 11 FLE.D rd,fs1,fs2 jD,rd,fs1,fs2 FLED(rd, rs1, rs2)
260 @ 0010101 fs2[5] fs1[5] 000 fd[5] 10100 11 FMIN.D fd,fs1,fs2 jD,fd,fs1,fs2 FMIND(rd, rs1, rs2)
261 @ 0010101 fs2[5] fs1[5] 001 fd[5] 10100 11 FMAX.D fd,fs1,fs2 jD,fd,fs1,fs2 FMAXD(rd, rs1, rs2)
262
263 @ 0010000 fs2[5] fs1[5] 000 fd[5] 10100 11 FSGNJ.S fd,fs1,fs2 jF,fd,fs1,fs2 FR(rd).ui = sgnj32(rs1, rs2, 0,0); box(rd)
264 @ 0010000 fs2[5] fs1[5] 001 fd[5] 10100 11 FSGNJN.S fd,fs1,fs2 jF,fd,fs1,fs2 FR(rd).ui = sgnj32(rs1, rs2, 1,0); box(rd)
265 @ 0010000 fs2[5] fs1[5] 010 fd[5] 10100 11 FSGNJX.S fd,fs1,fs2 jF,fd,fs1,fs2 FR(rd).ui = sgnj32(rs1, rs2, 0,1); box(rd)
266
267 @ 0010001 fs2[5] fs1[5] 000 fd[5] 10100 11 FSGNJ.D fd,fs1,fs2 jD,fd,fs1,fs2 FR(rd).ul = sgnj64(rs1, rs2, 0,0)
268 @ 0010001 fs2[5] fs1[5] 001 fd[5] 10100 11 FSGNJN.D fd,fs1,fs2 jD,fd,fs1,fs2 FR(rd).ul = sgnj64(rs1, rs2, 1,0)
269 @ 0010001 fs2[5] fs1[5] 010 fd[5] 10100 11 FSGNJX.D fd,fs1,fs2 jD,fd,fs1,fs2 FR(rd).ul = sgnj64(rs1, rs2, 0,1)
270
271 @ 1110000 00000 fs1[5] 000 rd[5] 10100 11 FMV.X.W rd,fs1 jF,rd,fs1 IR(rd).ul = FR(rs1).ul
272 @ 1111000 00000 rs1[5] 000 fd[5] 10100 11 FMV.W.X fd,rs1 jF,fd,rs1 FR(rd).ul = IR(rs1).ul
273
274 @ 1110001 00000 fs1[5] 000 rd[5] 10100 11 FMV.X.D rd,fs1 jD,rd,fs1 IR(rd).ul = FR(rs1).ul
275 @ 1111001 00000 rs1[5] 000 fd[5] 10100 11 FMV.D.X fd,rs1 jD,fd,rs1 FR(rd).ul = IR(rs1).ul
276
277
278 # Special Instructions
279
280 @ 00000000000 0 00000 000 00000 11100 11 ECALL - x,- ECALL(4)
281 @ {10:0} 1 00000 000 00000 11100 11 EBREAK constant x,- EBRK(constant, 4)
282
283 @ {11:0} rs1[5] 001 rd[5] 11100 11 CSRRW rd,rs1,constant x,rd,rs1 DOCSR(constant, 4)
284 @ {11:0} rs1[5] 010 rd[5] 11100 11 CSRRS rd,rs1,constant x,rd,rs1 DOCSR(constant,4)
285 @ {11:0} rs1[5] 011 rd[5] 11100 11 CSRRC rd,rs1,constant x,rd,rs1 DOCSR(constant, 4)
286
287 @ {11:0} {16:12} 101 rd[5] 11100 11 CSRRWI rd,constant x,rd DOCSR(constant & 0xfff, 4)
288 @ {11:0} {16:12} 110 rd[5] 11100 11 CSRRSI rd,constant x,rd DOCSR(constant & 0xfff, 4)
289 @ {11:0} {16:12} 111 rd[5] 11100 11 CSRRCI rd,constant x,rd DOCSR(constant & 0xfff, 4)
290
291 @ 00010 {1:0} 00000 rs1[5] 010 rd[5] 01011 11 LR.W rd,rs1 rA,rd,rs1 LR_W(rd, rs1)
292 @ 00010 {1:0} 00000 rs1[5] 011 rd[5] 01011 11 LR.D rd,rs1 rA,rd,rs1 LR_L(rd, rs1)
293 @ 00011 {1:0} rs2[5] rs1[5] 010 rd[5] 01011 11 SC.W rd,rs1,rs2 wA,rd,rs1,rs2 SC_W(rd, rs1, rs2)
294 @ 00011 {1:0} rs2[5] rs1[5] 011 rd[5] 01011 11 SC.D rd,rs1,rs2 wA,rd,rs1,rs2 SC_L(rd, rs1, rs2)
295
296 @ 00001 {1:0} rs2[5] rs1[5] 010 rd[5] 01011 11 AMOSWAP.W rd,rs1,rs2 wA,rd,rs1,rs2 AMOSWAP_W(rd, rs1, rs2)
297 @ 00001 {1:0} rs2[5] rs1[5] 011 rd[5] 01011 11 AMOSWAP.D rd,rs1,rs2 wA,rd,rs1,rs2 AMOSWAP_L(rd, rs1, rs2)
298
299 @ 00000 {1:0} rs2[5] rs1[5] 010 rd[5] 01011 11 AMOADD.W rd,rs1,rs2 wA,rd,rs1,rs2 AMOADD_W(rd, rs1, rs2)
300 @ 00100 {1:0} rs2[5] rs1[5] 010 rd[5] 01011 11 AMOXOR.W rd,rs1,rs2 wA,rd,rs1,rs2 AMOXOR_W(rd, rs1, rs2)
301 @ 01000 {1:0} rs2[5] rs1[5] 010 rd[5] 01011 11 AMOOR.W rd,rs1,rs2 wA,rd,rs1,rs2 AMOOR_W(rd, rs1, rs2)
302 @ 01100 {1:0} rs2[5] rs1[5] 010 rd[5] 01011 11 AMOAND.W rd,rs1,rs2 wA,rd,rs1,rs2 AMOAND_W(rd, rs1, rs2)
303
304 @ 10000 {1:0} rs2[5] rs1[5] 010 rd[5] 01011 11 AMOMIN.W rd,rs1,rs2 wA,rd,rs1,rs2 AMOMIN_W(rd, rs1, rs2)
305 @ 10100 {1:0} rs2[5] rs1[5] 010 rd[5] 01011 11 AMOMAX.W rd,rs1,rs2 wA,rd,rs1,rs2 AMOMAX_W(rd, rs1, rs2)
306 @ 11000 {1:0} rs2[5] rs1[5] 010 rd[5] 01011 11 AMOMINU.W rd,rs1,rs2 wA,rd,rs1,rs2 AMOMINU_W(rd, rs1, rs2)
307 @ 11100 {1:0} rs2[5] rs1[5] 010 rd[5] 01011 11 AMOMAXU.W rd,rs1,rs2 wA,rd,rs1,rs2 AMOMAXU_W(rd, rs1, rs2)
308
309 @ 00000 {1:0} rs2[5] rs1[5] 011 rd[5] 01011 11 AMOADD.D rd,rs1,rs2 wA,rd,rs1,rs2 AMOADD_L(rd, rs1, rs2)
310 @ 00100 {1:0} rs2[5] rs1[5] 011 rd[5] 01011 11 AMOXOR.D rd,rs1,rs2 wA,rd,rs1,rs2 AMOXOR_L(rd, rs1, rs2)
311 @ 01000 {1:0} rs2[5] rs1[5] 011 rd[5] 01011 11 AMOOR.D rd,rs1,rs2 wA,rd,rs1,rs2 AMOOR_L(rd, rs1, rs2)
312 @ 01100 {1:0} rs2[5] rs1[5] 011 rd[5] 01011 11 AMOAND.D rd,rs1,rs2 wA,rd,rs1,rs2 AMOAND_L(rd, rs1, rs2)
313
314 @ 10000 {1:0} rs2[5] rs1[5] 011 rd[5] 01011 11 AMOMIN.D rd,rs1,rs2 wA,rd,rs1,rs2 AMOMIN_L(rd, rs1, rs2)
315 @ 10100 {1:0} rs2[5] rs1[5] 011 rd[5] 01011 11 AMOMAX.D rd,rs1,rs2 wA,rd,rs1,rs2 AMOMAX_L(rd, rs1, rs2)
316 @ 11000 {1:0} rs2[5] rs1[5] 011 rd[5] 01011 11 AMOMINU.D rd,rs1,rs2 wA,rd,rs1,rs2 AMOMINU_L(rd, rs1, rs2)
317 @ 11100 {1:0} rs2[5] rs1[5] 011 rd[5] 01011 11 AMOMAXU.D rd,rs1,rs2 wA,rd,rs1,rs2 AMOMAXU_L(rd, rs1, rs2)
318
319 @ {-11:0} rs1[5] 000 rd[5] 00011 11 FENCE rd,rs1,immed xA,rd,rs1 FENCE(rd, rs1, immed)