caveat/caveat_fp.h

   1 #pragma once
   2
   3 #define SOFT_FP
   4 #ifndef NO_FP_MACROS
   5 #define FMADD32( rm, rd, rs1, rs2, rs3) SRM(rm); FR(rd).f32 = f32_mulAdd( F32(rs1), F32(rs2),  F32(rs3)); SET_FPX; SRM(cpu->state.fcsr.rmode);
   6 #define FMADD32_dyn(rd, rs1, rs2, rs3) FR(rd).f32 = f32_mulAdd( F32(rs1), F32(rs2),  F32(rs3)); SET_FPX;
   7 #define FMSUB32( rm, rd, rs1, rs2, rs3) SRM(rm); FR(rd).f32 = f32_mulAdd( F32(rs1), F32(rs2), NF32(rs3)); SET_FPX; SRM(cpu->state.fcsr.rmode);
   8 #define FMSUB32_dyn(rd, rs1, rs2, rs3) FR(rd).f32 = f32_mulAdd( F32(rs1), F32(rs2), NF32(rs3)); SET_FPX;
   9 #define FNMADD32(rm, rd, rs1, rs2, rs3) SRM(rm); FR(rd).f32 = f32_mulAdd(NF32(rs1), F32(rs2), NF32(rs3)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  10 #define FNMADD32_dyn(rd, rs1, rs2, rs3) FR(rd).f32 = f32_mulAdd(NF32(rs1), F32(rs2), NF32(rs3)); SET_FPX;
  11 #define FNMSUB32(rm, rd, rs1, rs2, rs3) SRM(rm); FR(rd).f32 = f32_mulAdd(NF32(rs1), F32(rs2),  F32(rs3)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  12 #define FNMSUB32_dyn(rd, rs1, rs2, rs3) FR(rd).f32 = f32_mulAdd(NF32(rs1), F32(rs2),  F32(rs3)); SET_FPX;
  13 #define FMADD64( rm, rd, rs1, rs2, rs3) SRM(rm); FR(rd).f64 = f64_mulAdd( F64(rs1), F64(rs2),  F64(rs3)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  14 #define FMADD64_dyn(rd, rs1, rs2, rs3) FR(rd).f64 = f64_mulAdd( F64(rs1), F64(rs2),  F64(rs3)); SET_FPX;
  15 #define FMSUB64( rm, rd, rs1, rs2, rs3) SRM(rm); FR(rd).f64 = f64_mulAdd( F64(rs1), F64(rs2), NF64(rs3)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  16 #define FMSUB64_dyn(rd, rs1, rs2, rs3) FR(rd).f64 = f64_mulAdd( F64(rs1), F64(rs2), NF64(rs3)); SET_FPX;
  17 #define FNMADD64(rm, rd, rs1, rs2, rs3) SRM(rm); FR(rd).f64 = f64_mulAdd(NF64(rs1), F64(rs2), NF64(rs3)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  18 #define FNMADD64_dyn(rd, rs1, rs2, rs3) FR(rd).f64 = f64_mulAdd(NF64(rs1), F64(rs2), NF64(rs3)); SET_FPX;
  19 #define FNMSUB64(rm, rd, rs1, rs2, rs3) SRM(rm); FR(rd).f64 = f64_mulAdd(NF64(rs1), F64(rs2),  F64(rs3)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  20 #define FNMSUB64_dyn(rd, rs1, rs2, rs3) FR(rd).f64 = f64_mulAdd(NF64(rs1), F64(rs2),  F64(rs3)); SET_FPX;
  21 #define FADD32(rm, rd, rs1, rs2) SRM(rm); FR(rd).f32 = f32_add(F32(rs1), F32(rs2)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  22 #define FADD32_dyn(rd, rs1, rs2) FR(rd).f32 = f32_add(F32(rs1), F32(rs2)); SET_FPX;
  23 #define FSUB32(rm, rd, rs1, rs2) SRM(rm); FR(rd).f32 = f32_sub(F32(rs1), F32(rs2)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  24 #define FSUB32_dyn(rd, rs1, rs2) FR(rd).f32 = f32_sub(F32(rs1), F32(rs2)); SET_FPX;
  25 #define FMUL32(rm, rd, rs1, rs2) SRM(rm); FR(rd).f32 = f32_mul(F32(rs1), F32(rs2)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  26 #define FMUL32_dyn(rd, rs1, rs2) FR(rd).f32 = f32_mul(F32(rs1), F32(rs2)); SET_FPX;
  27 #define FDIV32(rm, rd, rs1, rs2) SRM(rm); FR(rd).f32 = f32_div(F32(rs1), F32(rs2)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  28 #define FDIV32_dyn(rd, rs1, rs2) FR(rd).f32 = f32_div(F32(rs1), F32(rs2)); SET_FPX;
  29 #define FADD64(rm, rd, rs1, rs2) SRM(rm); FR(rd).f64 = f64_add(F64(rs1), F64(rs2)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  30 #define FADD64_dyn(rd, rs1, rs2) FR(rd).f64 = f64_add(F64(rs1), F64(rs2)); SET_FPX;
  31 #define FSUB64(rm, rd, rs1, rs2) SRM(rm); FR(rd).f64 = f64_sub(F64(rs1), F64(rs2)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  32 #define FSUB64_dyn(rd, rs1, rs2) FR(rd).f64 = f64_sub(F64(rs1), F64(rs2)); SET_FPX;
  33 #define FMUL64(rm, rd, rs1, rs2) SRM(rm); FR(rd).f64 = f64_mul(F64(rs1), F64(rs2)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  34 #define FMUL64_dyn(rd, rs1, rs2) FR(rd).f64 = f64_mul(F64(rs1), F64(rs2)); SET_FPX;
  35 #define FDIV64(rm, rd, rs1, rs2) SRM(rm); FR(rd).f64 = f64_div(F64(rs1), F64(rs2)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  36 #define FDIV64_dyn(rd, rs1, rs2) FR(rd).f64 = f64_div(F64(rs1), F64(rs2)); SET_FPX;
  37 #define FSQRT32(rm, rd, rs1) SRM(rm); FR(rd).f32 = f32_sqrt(F32(rs1)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  38 #define FSQRT32_dyn(rd, rs1) FR(rd).f32 = f32_sqrt(F32(rs1)); SET_FPX;
  39 #define FSQRT64(rm, rd, rs1) SRM(rm); FR(rd).f64 = f64_sqrt(F64(rs1)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  40 #define FSQRT64_dyn(rd, rs1) FR(rd).f64 = f64_sqrt(F64(rs1)); SET_FPX;
  41 #define FCVTWS( rm, rd, rs1) SRM(rm); IR(rd).l  = (long)f32_to_i32( F32(rs1), RM, true); SET_FPX; SRM(cpu->state.fcsr.rmode);
  42 #define FCVTWS_dyn(rd, rs1) IR(rd).l  = (long)f32_to_i32( F32(rs1), RM, true); SET_FPX;
  43 #define FCVTWUS(rm, rd, rs1) SRM(rm); IR(rd).l  = (long)f32_to_ui32(F32(rs1), RM, true); SET_FPX; SRM(cpu->state.fcsr.rmode);
  44 #define FCVTWUS_dyn(rd, rs1) IR(rd).l  = (long)f32_to_ui32(F32(rs1), RM, true); SET_FPX;
  45 #define FCVTLS( rm, rd, rs1) SRM(rm); IR(rd).l  =       f32_to_i64( F32(rs1), RM, true); SET_FPX; SRM(cpu->state.fcsr.rmode);
  46 #define FCVTLS_dyn(rd, rs1) IR(rd).l  =       f32_to_i64( F32(rs1), RM, true); SET_FPX;
  47 #define FCVTLUS(rm, rd, rs1) SRM(rm); IR(rd).ul =       f32_to_ui64(F32(rs1), RM, true); SET_FPX; SRM(cpu->state.fcsr.rmode);
  48 #define FCVTLUS_dyn(rd, rs1) IR(rd).ul =       f32_to_ui64(F32(rs1), RM, true); SET_FPX;
  49 #define FCVTWD( rm, rd, rs1) SRM(rm); IR(rd).l  = (long)f64_to_i64( F64(rs1), RM, true); SET_FPX; SRM(cpu->state.fcsr.rmode);
  50 #define FCVTWD_dyn(rd, rs1) IR(rd).l  = (long)f64_to_i64( F64(rs1), RM, true); SET_FPX;
  51 #define FCVTWUD(rm, rd, rs1) SRM(rm); IR(rd).l  = (long)f64_to_ui64(F64(rs1), RM, true); SET_FPX; SRM(cpu->state.fcsr.rmode);
  52 #define FCVTWUD_dyn(rd, rs1) IR(rd).l  = (long)f64_to_ui64(F64(rs1), RM, true); SET_FPX;
  53 #define FCVTLD( rm, rd, rs1) SRM(rm); IR(rd).l  =       f64_to_i64( F64(rs1), RM, true); SET_FPX; SRM(cpu->state.fcsr.rmode);
  54 #define FCVTLD_dyn(rd, rs1) IR(rd).l  =       f64_to_i64( F64(rs1), RM, true); SET_FPX;
  55 #define FCVTLUD(rm, rd, rs1) SRM(rm); IR(rd).ul =       f64_to_ui64(F64(rs1), RM, true); SET_FPX; SRM(cpu->state.fcsr.rmode);
  56 #define FCVTLUD_dyn(rd, rs1) IR(rd).ul =       f64_to_ui64(F64(rs1), RM, true); SET_FPX;
  57 #define FCVTSW( rm, rd, rs1) SRM(rm); FR(rd).f32 =  i32_to_f32(IR(rs1).i ); SET_FPX; SRM(cpu->state.fcsr.rmode);
  58 #define FCVTSW_dyn(rd, rs1) FR(rd).f32 =  i32_to_f32(IR(rs1).i ); SET_FPX;
  59 #define FCVTSWU(rm, rd, rs1) SRM(rm); FR(rd).f32 = ui32_to_f32(IR(rs1).ui); SET_FPX; SRM(cpu->state.fcsr.rmode);
  60 #define FCVTSWU_dyn(rd, rs1) FR(rd).f32 = ui32_to_f32(IR(rs1).ui); SET_FPX;
  61 #define FCVTSL( rm, rd, rs1) SRM(rm); FR(rd).f32 =  i64_to_f32(IR(rs1).l ); SET_FPX; SRM(cpu->state.fcsr.rmode);
  62 #define FCVTSL_dyn(rd, rs1) FR(rd).f32 =  i64_to_f32(IR(rs1).l ); SET_FPX;
  63 #define FCVTSLU(rm, rd, rs1) SRM(rm); FR(rd).f32 = ui64_to_f32(IR(rs1).ul); SET_FPX; SRM(cpu->state.fcsr.rmode);
  64 #define FCVTSLU_dyn(rd, rs1) FR(rd).f32 = ui64_to_f32(IR(rs1).ul); SET_FPX;
  65 #define FCVTDW( rm, rd, rs1) SRM(rm); FR(rd).f64 =  i32_to_f64(IR(rs1).i ); SET_FPX; SRM(cpu->state.fcsr.rmode);
  66 #define FCVTDW_dyn(rd, rs1) FR(rd).f64 =  i32_to_f64(IR(rs1).i ); SET_FPX;
  67 #define FCVTDWU(rm, rd, rs1) SRM(rm); FR(rd).f64 = ui32_to_f64(IR(rs1).ui); SET_FPX; SRM(cpu->state.fcsr.rmode);
  68 #define FCVTDWU_dyn(rd, rs1) FR(rd).f64 = ui32_to_f64(IR(rs1).ui); SET_FPX;
  69 #define FCVTDL( rm, rd, rs1) SRM(rm); FR(rd).f64 =  i64_to_f64(IR(rs1).l ); SET_FPX; SRM(cpu->state.fcsr.rmode);
  70 #define FCVTDL_dyn(rd, rs1) FR(rd).f64 =  i64_to_f64(IR(rs1).l ); SET_FPX;
  71 #define FCVTDLU(rm, rd, rs1) SRM(rm); FR(rd).f64 = ui64_to_f64(IR(rs1).ul); SET_FPX; SRM(cpu->state.fcsr.rmode);
  72 #define FCVTDLU_dyn(rd, rs1) FR(rd).f64 = ui64_to_f64(IR(rs1).ul); SET_FPX;
  73 #define FCVTSD(rm, rd, rs1) SRM(rm); FR(rd).f32 = f64_to_f32(F64(rs1)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  74 #define FCVTSD_dyn(rd, rs1) FR(rd).f32 = f64_to_f32(F64(rs1)); SET_FPX;
  75 #define FCVTDS(rm, rd, rs1) SRM(rm); FR(rd).f64 = f32_to_f64(F32(rs1)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  76 #define FCVTDS_dyn(rd, rs1) FR(rd).f64 = f32_to_f64(F32(rs1)); SET_FPX;
  77 #define FEQS(rd, rs1, rs2) IR(rd).l = f32_eq(F32(rs1), F32(rs2)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  78 #define FLTS(rd, rs1, rs2) IR(rd).l = f32_lt(F32(rs1), F32(rs2)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  79 #define FLES(rd, rs1, rs2) IR(rd).l = f32_le(F32(rs1), F32(rs2)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  80 #define FEQD(rd, rs1, rs2) IR(rd).l = f64_eq(F64(rs1), F64(rs2)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  81 #define FLTD(rd, rs1, rs2) IR(rd).l = f64_lt(F64(rs1), F64(rs2)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  82 #define FLED(rd, rs1, rs2) IR(rd).l = f64_le(F64(rs1), F64(rs2)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  83 #define FMINS(rd, rs1, rs2) FR(rd).f32 = f32_min(F32(rs1), F32(rs2)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  84 #define FMAXS(rd, rs1, rs2) FR(rd).f32 = f32_max(F32(rs1), F32(rs2)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  85 #define FMIND(rd, rs1, rs2) FR(rd).f64 = f64_min(F64(rs1), F64(rs2)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  86 #define FMAXD(rd, rs1, rs2) FR(rd).f64 = f64_max(F64(rs1), F64(rs2)); SET_FPX; SRM(cpu->state.fcsr.rmode);
  87 #endif