Use correct ir_width for libresoc JTAG TAP.
[libresoc-litex.git] / cocotb / README.md
1 # Usage
2
3 Cocotb is Makefile based. In order to support different configuration and
4 simulators, run scripts are provided that call the Makefile:
5
6 * run_iverilator.sh: Run pre-layout testbench with Icarus Verilog.
7 * clean.sh: clean up all outputs.
8
9 # Dependency
10
11 * cocotb: `pip install cocotb`
12 * c4m-jtag: install according to HDL workflow
13 * iverilog: `apt install iverilog`
14 * `../libresoc.v`, `../ls180.v`: run `make ls180_verilog` in soc directory,
15 `make ls180` in parent directory.
16 Version with SRAMs is currently not supported.
17