coldboot/coldboot.c

   1 #include <stdint.h>
   2 #include <stdbool.h>
   3
   4 #include "console.h"
   5 #include "microwatt_soc.h"
   6 #include "io.h"
   7
   8 #include <stdlib.h>
   9 #include <stdint.h>
  10 #include <gram.h>
  11
  12 #include "elf64.h"
  13
  14 static inline uint32_t read32(const void *addr)
  15 {
  16         return *(volatile uint32_t *)addr;
  17 }
  18
  19 static inline void write32(void *addr, uint32_t value)
  20 {
  21         *(volatile uint32_t *)addr = value;
  22 }
  23
  24 struct uart_regs {
  25         uint32_t divisor;
  26         uint32_t rx_data;
  27         uint32_t rx_rdy;
  28         uint32_t rx_err;
  29         uint32_t tx_data;
  30         uint32_t tx_rdy;
  31         uint32_t zero0; // reserved
  32         uint32_t zero1; // reserved
  33         uint32_t ev_status;
  34         uint32_t ev_pending;
  35         uint32_t ev_enable;
  36 };
  37
  38 void uart_writeuint32(uint32_t val) {
  39         const char lut[] = { '0', '1', '2', '3', '4', '5', '6', '7',
  40                          '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
  41         uint8_t *val_arr = (uint8_t*)(&val);
  42         size_t i;
  43
  44         for (i = 0; i < 4; i++) {
  45                 putchar(lut[(val_arr[3-i] >> 4) & 0xF]);
  46                 putchar(lut[val_arr[3-i] & 0xF]);
  47         }
  48 }
  49
  50 void memcpy(void *dest, void *src, size_t n) {
  51     int i;
  52     //cast src and dest to char*
  53     char *src_char = (char *)src;
  54     char *dest_char = (char *)dest;
  55     for (i=0; i<n; i++) {
  56 #if 1
  57         if ((i % 4096) == 0) {
  58             puts("memcpy ");
  59             uart_writeuint32(i);
  60             puts("\r\n");
  61         }
  62 #endif
  63         dest_char[i] = src_char[i]; //copy contents byte by byte
  64     }
  65 }
  66
  67 void isr(void) {
  68
  69 }
  70
  71 // WARNING
  72 // KESTREL SPECIFIC
  73 #define TERCEL_SPI_REG_SYS_PHY_CFG1     0x10
  74 #define TERCEL_SPI_REG_SYS_FLASH_CFG5       0x24
  75 #define TERCEL_SPI_PHY_CLOCK_DIVISOR_MASK   0xff
  76 #define TERCEL_SPI_PHY_CLOCK_DIVISOR_SHIFT  0
  77 #define TERCEL_SPI_FLASH_EN_MULTCYC_READ_MASK   0x1
  78 #define TERCEL_SPI_FLASH_EN_MULTCYC_READ_SHIFT  0
  79 static inline uint32_t read_tercel_register(uint8_t reg)
  80 {
  81         return readl((unsigned long)(SPI_FCTRL_BASE+reg));
  82 }
  83
  84 static inline void write_tercel_register(uint8_t reg, uint32_t value)
  85 {
  86         writel(value, (unsigned long)(SPI_FCTRL_BASE+reg));
  87 }
  88
  89 // TODO: need to use this
  90 // https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-litex/litex/-/blob/master/litex/soc/software/bios/boot.c#L575
  91 static bool fl_read(void *dst, uint32_t offset, uint32_t size)
  92 {
  93     uint8_t *d = dst;
  94     memcpy(d, (void *)(unsigned long)(SPI_FLASH_BASE + offset), size);
  95     return true;
  96 }
  97
  98 static unsigned long copy_flash(unsigned int offset)
  99 {
 100     Elf64_Ehdr ehdr;
 101     Elf64_Phdr ph;
 102     unsigned int i, poff, size, off;
 103     void *addr;
 104
 105     // WARNING
 106     // KESTREL SPECIFIC
 107     // Set SPI clock cycle divider to 1
 108     uint32_t dword;
 109     dword = read_tercel_register(TERCEL_SPI_REG_SYS_PHY_CFG1);
 110     dword &= ~(TERCEL_SPI_PHY_CLOCK_DIVISOR_MASK <<
 111                TERCEL_SPI_PHY_CLOCK_DIVISOR_SHIFT);
 112     dword |= ((1 & TERCEL_SPI_PHY_CLOCK_DIVISOR_MASK) <<
 113                    TERCEL_SPI_PHY_CLOCK_DIVISOR_SHIFT);
 114     write_tercel_register(TERCEL_SPI_REG_SYS_PHY_CFG1, dword);
 115     // Enable read merging
 116     dword = read_tercel_register(TERCEL_SPI_REG_SYS_FLASH_CFG5);
 117     dword |= (TERCEL_SPI_FLASH_EN_MULTCYC_READ_MASK <<
 118               TERCEL_SPI_FLASH_EN_MULTCYC_READ_SHIFT);
 119     write_tercel_register(TERCEL_SPI_REG_SYS_FLASH_CFG5, dword);
 120
 121     puts("Trying flash...\r\n");
 122     if (!fl_read(&ehdr, offset, sizeof(ehdr)))
 123         return -1ul;
 124     if (!IS_ELF(ehdr) || ehdr.e_ident[EI_CLASS] != ELFCLASS64) {
 125         puts("Doesn't look like an elf64\r\n");
 126         goto dump;
 127     }
 128     if (ehdr.e_ident[EI_DATA] != ELFDATA2LSB ||
 129         ehdr.e_machine != EM_PPC64) {
 130         puts("Not a ppc64le binary\r\n");
 131         goto dump;
 132     }
 133
 134     poff = offset + ehdr.e_phoff;
 135     for (i = 0; i < ehdr.e_phnum; i++) {
 136         if (!fl_read(&ph, poff, sizeof(ph)))
 137             goto dump;
 138         if (ph.p_type != PT_LOAD)
 139             continue;
 140
 141         /* XXX Add bound checking ! */
 142         size = ph.p_filesz;
 143         addr = (void *)ph.p_vaddr;
 144         off  = offset + ph.p_offset;
 145         //printf("Copy segment %d (0x%x bytes) to %p\n", i, size, addr);
 146         puts("Copy segment ");
 147         uart_writeuint32(i);
 148         puts(" size ");
 149         uart_writeuint32(size);
 150         puts(" addr ");
 151         uart_writeuint32((uint32_t)(unsigned long)addr);
 152         puts("\r\n");
 153         fl_read(addr, off, size);
 154         poff += ehdr.e_phentsize;
 155     }
 156
 157     puts("Booting from DRAM at");
 158     uart_writeuint32((unsigned int)ehdr.e_entry);
 159     puts("\r\n");
 160
 161     puts("Dump DRAM\r\n");
 162     for (i = 0; i < 64; i++) {
 163         uart_writeuint32(readl(ehdr.e_entry+(i*4)));
 164         puts(" ");
 165         if ((i & 7) == 7) puts("\r\n");
 166     }
 167     puts("\r\n");
 168
 169     //flush_cpu_icache();
 170     return ehdr.e_entry;
 171 dump:
 172     puts("HDR: \r\n");
 173     for (i = 0; i < 8; i++) {
 174         uart_writeuint32(ehdr.e_ident[i]);
 175         puts("\r\n");
 176     }
 177
 178     return -1ul;
 179 }
 180
 181
 182 // XXX
 183 // Defining gram_[read|write] allows a trace of all register
 184 // accesses to be dumped to console for debugging purposes.
 185 // To use, define GRAM_RW_FUNC in gram.h
 186 uint32_t gram_read(const struct gramCtx *ctx, void *addr) {
 187         uint32_t dword;
 188
 189         puts("gram_read: ");
 190         uart_writeuint32((unsigned long)addr);
 191         dword = readl((unsigned long)addr);
 192         puts(": ");
 193         uart_writeuint32((unsigned long)dword);
 194         puts("\n");
 195
 196         return dword;
 197 }
 198
 199 int gram_write(const struct gramCtx *ctx, void *addr, uint32_t value) {
 200         puts("gram_write: ");
 201         uart_writeuint32((unsigned long)addr);
 202         puts(": ");
 203         uart_writeuint32((unsigned long)value);
 204         writel(value, (unsigned long)addr);
 205         puts("\n");
 206
 207         return 0;
 208 }
 209
 210 int main(void) {
 211         const int kNumIterations = 14;
 212         int res, failcnt = 0;
 213         uint32_t tmp;
 214     unsigned long ftr, spi_offs=0x0;
 215         volatile uint32_t *ram = (uint32_t*)MEMORY_BASE;
 216
 217         console_init();
 218         //puts("Firmware launched...\n");
 219
 220 #if 1
 221     puts(" Soc signature: ");
 222     tmp = readl(SYSCON_BASE + SYS_REG_SIGNATURE);
 223     uart_writeuint32(tmp);
 224     puts("  Soc features: ");
 225     ftr = readl(SYSCON_BASE + SYS_REG_INFO);
 226     if (ftr & SYS_REG_INFO_HAS_UART)
 227         puts("UART ");
 228     if (ftr & SYS_REG_INFO_HAS_DRAM)
 229         puts("DRAM ");
 230     if (ftr & SYS_REG_INFO_HAS_BRAM)
 231         puts("BRAM ");
 232     if (ftr & SYS_REG_INFO_HAS_SPI_FLASH)
 233         puts("SPIFLASH ");
 234     if (ftr & SYS_REG_INFO_HAS_LITEETH)
 235         puts("ETHERNET ");
 236     puts("\r\n");
 237
 238     if (ftr & SYS_REG_INFO_HAS_SPI_FLASH) {
 239         puts("SPI Offset: ");
 240         spi_offs = readl(SYSCON_BASE + SYS_REG_SPI_INFO);
 241         uart_writeuint32(spi_offs);
 242         puts("\r\n");
 243     }
 244
 245 #endif
 246
 247 #if 1
 248 #if 1
 249     // print out configuration parameters for QSPI
 250         volatile uint32_t *qspi_cfg = (uint32_t*)SPI_FCTRL_BASE;
 251     for (int k=0; k < 2; k++) {
 252         tmp = readl((unsigned long)&(qspi_cfg[k]));
 253         puts("cfg");
 254         uart_writeuint32(k);
 255         puts(" ");
 256         uart_writeuint32(tmp);
 257         puts("\n");
 258     }
 259 #endif
 260         volatile uint32_t *qspi = (uint32_t*)spi_offs;
 261     //volatile uint8_t *qspi_bytes = (uint8_t*)spi_offs;
 262      // let's not, eh? writel(0xDEAF0123, (unsigned long)&(qspi[0]));
 263      // tmp = readl((unsigned long)&(qspi[0]));
 264     for (int i=0;i<256;i++) {
 265       tmp = readl((unsigned long)&(qspi[i]));
 266       uart_writeuint32(tmp);
 267       puts(" ");
 268       if ((i & 0x7) == 0x7) puts("\r\n");
 269     }
 270     puts("\r\n");
 271     /*
 272     for (i=0;i<256;i++) {
 273       tmp = readb((unsigned long)&(qspi_bytes[i]));
 274       uart_writeuint32(tmp);
 275       puts(" ");
 276     }
 277     */
 278 #if 0
 279     while (1) {
 280         // quick read
 281         tmp = readl((unsigned long)&(qspi[0x1000/4]));
 282         puts("read 0x1000");
 283         uart_writeuint32(tmp);
 284         putchar(10);
 285     }
 286     while (1) {
 287         unsigned char c = getchar();
 288         putchar(c);
 289         if (c == 13) { // if CR send LF
 290
 291             // quick read
 292             tmp = readl((unsigned long)&(qspi[1<<i]));
 293             puts("read ");
 294             uart_writeuint32(1<<i);
 295             puts(" ");
 296             uart_writeuint32(tmp);
 297             putchar(10);
 298             i++;
 299         }
 300     }
 301
 302     return 0;
 303 #endif
 304 #endif
 305 #if 0
 306         volatile uint32_t *hyperram = (uint32_t*)0xa0000000;
 307     writel(0xDEAF0123, (unsigned long)&(hyperram[0]));
 308     tmp = readl((unsigned long)&(hyperram[0]));
 309     while (1) {
 310         unsigned char c = getchar();
 311         putchar(c);
 312         if (c == 13) { // if CR send LF
 313
 314             // quick write/read
 315             writel(0xDEAF0123+i, (unsigned long)&(hyperram[1<<i]));
 316             tmp = readl((unsigned long)&(hyperram[1<<i]));
 317             puts("read ");
 318             uart_writeuint32(1<<i);
 319             puts(" ");
 320             uart_writeuint32(tmp);
 321             putchar(10);
 322             i++;
 323         }
 324     }
 325
 326     return 0;
 327 #endif
 328
 329     // init DRAM only if SYSCON says it exists (duh)
 330     if (ftr & SYS_REG_INFO_HAS_DRAM)
 331     {
 332         puts("DRAM init... ");
 333
 334         struct gramCtx ctx;
 335 #if 1
 336         struct gramProfile profile = {
 337             .mode_registers = {
 338                 0xb20, 0x806, 0x200, 0x0
 339             },
 340             .rdly_p0 = 2,
 341             .rdly_p1 = 2,
 342         };
 343 #endif
 344 #if 0
 345         struct gramProfile profile = {
 346             .mode_registers = {
 347                 0x0320, 0x0006, 0x0200, 0x0000
 348             },
 349             .rdly_p0 = 1,
 350             .rdly_p1 = 1,
 351         };
 352 #endif
 353         struct gramProfile profile2;
 354         gram_init(&ctx, &profile, (void*)MEMORY_BASE,
 355                                   (void*)DRAM_CTRL_BASE,
 356                                   (void*)DRAM_INIT_BASE);
 357         puts("done\n");
 358
 359         puts("MR profile: ");
 360         uart_writeuint32(profile.mode_registers[0]);
 361         puts(" ");
 362         uart_writeuint32(profile.mode_registers[1]);
 363         puts(" ");
 364         uart_writeuint32(profile.mode_registers[2]);
 365         puts(" ");
 366         uart_writeuint32(profile.mode_registers[3]);
 367         puts("\n");
 368
 369         // FIXME
 370         // Early read test for WB access sim
 371         //uart_writeuint32(*ram);
 372
 373 #if 1
 374         puts("Rdly\np0: ");
 375         for (size_t i = 0; i < 8; i++) {
 376             profile2.rdly_p0 = i;
 377             gram_load_calibration(&ctx, &profile2);
 378             gram_reset_burstdet(&ctx);
 379
 380             for (size_t j = 0; j < 128; j++) {
 381                 tmp = readl((unsigned long)&(ram[i]));
 382             }
 383             if (gram_read_burstdet(&ctx, 0)) {
 384                 puts("1");
 385             } else {
 386                 puts("0");
 387             }
 388         }
 389         puts("\n");
 390
 391         puts("Rdly\np1: ");
 392         for (size_t i = 0; i < 8; i++) {
 393             profile2.rdly_p1 = i;
 394             gram_load_calibration(&ctx, &profile2);
 395             gram_reset_burstdet(&ctx);
 396             for (size_t j = 0; j < 128; j++) {
 397                 tmp = readl((unsigned long)&(ram[i]));
 398             }
 399             if (gram_read_burstdet(&ctx, 1)) {
 400                 puts("1");
 401             } else {
 402                 puts("0");
 403             }
 404         }
 405         puts("\n");
 406
 407         puts("Auto calibrating... ");
 408         res = gram_generate_calibration(&ctx, &profile2);
 409         if (res != GRAM_ERR_NONE) {
 410             puts("failed\n");
 411             gram_load_calibration(&ctx, &profile);
 412         } else {
 413             gram_load_calibration(&ctx, &profile2);
 414         }
 415         puts("done\n");
 416
 417         puts("Auto calibration profile:");
 418         puts("p0 rdly:");
 419         uart_writeuint32(profile2.rdly_p0);
 420         puts(" p1 rdly:");
 421         uart_writeuint32(profile2.rdly_p1);
 422         puts("\n");
 423 #endif
 424
 425         puts("Reloading built-in calibration profile...");
 426         gram_load_calibration(&ctx, &profile);
 427
 428         puts("DRAM test... \n");
 429         for (size_t i = 0; i < kNumIterations; i++) {
 430             writel(0xDEAF0000 | i*4, (unsigned long)&(ram[i]));
 431         }
 432
 433 #if 0
 434         for (int dly = 0; dly < 8; dly++) {
 435             failcnt = 0;
 436             profile2.rdly_p0 = dly;
 437             profile2.rdly_p1 = dly;
 438             puts("p0 rdly:");
 439             uart_writeuint32(profile2.rdly_p0);
 440             puts(" p1 rdly:");
 441             uart_writeuint32(profile2.rdly_p1);
 442             gram_load_calibration(&ctx, &profile2);
 443             for (size_t i = 0; i < kNumIterations; i++) {
 444                 if (readl((unsigned long)&(ram[i])) != (0xDEAF0000 | i*4)) {
 445                     puts("fail : *(0x");
 446                     uart_writeuint32((unsigned long)(&ram[i]));
 447                     puts(") = ");
 448                     uart_writeuint32(readl((unsigned long)&(ram[i])));
 449                     puts("\n");
 450                     failcnt++;
 451
 452                     if (failcnt > 10) {
 453                         puts("Test canceled (more than 10 errors)\n");
 454                         break;
 455                     }
 456                 }
 457             }
 458         }
 459 #else
 460         failcnt = 0;
 461         for (size_t i = 0; i < kNumIterations; i++) {
 462             if (readl((unsigned long)&(ram[i])) != (0xDEAF0000 | i*4)) {
 463                 puts("fail : *(0x");
 464                 uart_writeuint32((unsigned long)(&ram[i]));
 465                 puts(") = ");
 466                 uart_writeuint32(readl((unsigned long)&(ram[i])));
 467                 puts("\n");
 468                 failcnt++;
 469
 470                 if (failcnt > 10) {
 471                     puts("Test canceled (more than 10 errors)\n");
 472                     break;
 473                 }
 474             }
 475         }
 476     }
 477 #endif
 478         puts("done\n");
 479
 480     // memcpy from SPI Flash then boot
 481     if ((ftr & SYS_REG_INFO_HAS_SPI_FLASH) &&
 482         (failcnt == 0))
 483     {
 484         // identify ELF, copy if present, and get the start address
 485         unsigned long faddr = copy_flash(spi_offs);
 486         if (faddr != -1ul) {
 487             // jump to absolute address
 488             return faddr;
 489         }
 490     }
 491
 492         return 0;
 493 }
 494