coldboot/coldboot.c

   1 #include <stdint.h>
   2 #include <stdbool.h>
   3
   4 #include "console.h"
   5 #include "microwatt_soc.h"
   6 #include "io.h"
   7
   8 #include <stdlib.h>
   9 #include <stdint.h>
  10 #include <gram.h>
  11
  12 #include "elf64.h"
  13
  14 static inline uint32_t read32(const void *addr)
  15 {
  16         return *(volatile uint32_t *)addr;
  17 }
  18
  19 static inline void write32(void *addr, uint32_t value)
  20 {
  21         *(volatile uint32_t *)addr = value;
  22 }
  23
  24 struct uart_regs {
  25         uint32_t divisor;
  26         uint32_t rx_data;
  27         uint32_t rx_rdy;
  28         uint32_t rx_err;
  29         uint32_t tx_data;
  30         uint32_t tx_rdy;
  31         uint32_t zero0; // reserved
  32         uint32_t zero1; // reserved
  33         uint32_t ev_status;
  34         uint32_t ev_pending;
  35         uint32_t ev_enable;
  36 };
  37
  38 void uart_writeuint32(uint32_t val) {
  39         const char lut[] = { '0', '1', '2', '3', '4', '5', '6', '7',
  40                          '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
  41         uint8_t *val_arr = (uint8_t*)(&val);
  42         size_t i;
  43
  44         for (i = 0; i < 4; i++) {
  45                 putchar(lut[(val_arr[3-i] >> 4) & 0xF]);
  46                 putchar(lut[val_arr[3-i] & 0xF]);
  47         }
  48 }
  49
  50 void memcpy(void *dest, void *src, size_t n) {
  51     int i;
  52     //cast src and dest to char*
  53     char *src_char = (char *)src;
  54     char *dest_char = (char *)dest;
  55     for (i=0; i<n; i++) {
  56 #if 1
  57         if ((i % 4096) == 0) {
  58             puts("memcpy ");
  59             uart_writeuint32(i);
  60             puts("\r\n");
  61         }
  62 #endif
  63         dest_char[i] = src_char[i]; //copy contents byte by byte
  64     }
  65 }
  66
  67 void isr(void) {
  68
  69 }
  70
  71 // WARNING
  72 // KESTREL SPECIFIC
  73 #define TERCEL_SPI_REG_SYS_PHY_CFG1     0x10
  74 #define TERCEL_SPI_REG_SYS_FLASH_CFG5       0x24
  75 #define TERCEL_SPI_PHY_CLOCK_DIVISOR_MASK   0xff
  76 #define TERCEL_SPI_PHY_CLOCK_DIVISOR_SHIFT  0
  77 #define TERCEL_SPI_FLASH_EN_MULTCYC_READ_MASK   0x1
  78 #define TERCEL_SPI_FLASH_EN_MULTCYC_READ_SHIFT  0
  79 static inline uint32_t read_tercel_register(uint8_t reg)
  80 {
  81         return readl((unsigned long)(SPI_FCTRL_BASE+reg));
  82 }
  83
  84 static inline void write_tercel_register(uint8_t reg, uint32_t value)
  85 {
  86         writel(value, (unsigned long)(SPI_FCTRL_BASE+reg));
  87 }
  88
  89 // TODO: need to use this
  90 // https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-litex/litex/-/blob/master/litex/soc/software/bios/boot.c#L575
  91 static bool fl_read(void *dst, uint32_t offset, uint32_t size)
  92 {
  93     uint8_t *d = dst;
  94     memcpy(d, (void *)(unsigned long)(SPI_FLASH_BASE + offset), size);
  95     return true;
  96 }
  97
  98 static unsigned long copy_flash(unsigned int offset)
  99 {
 100     Elf64_Ehdr ehdr;
 101     Elf64_Phdr ph;
 102     unsigned int i, poff, size, off;
 103     void *addr;
 104
 105     // WARNING
 106     // KESTREL SPECIFIC
 107     // Set SPI clock cycle divider to 1
 108     uint32_t dword;
 109     dword = read_tercel_register(TERCEL_SPI_REG_SYS_PHY_CFG1);
 110     dword &= ~(TERCEL_SPI_PHY_CLOCK_DIVISOR_MASK <<
 111                TERCEL_SPI_PHY_CLOCK_DIVISOR_SHIFT);
 112     dword |= ((1 & TERCEL_SPI_PHY_CLOCK_DIVISOR_MASK) <<
 113                    TERCEL_SPI_PHY_CLOCK_DIVISOR_SHIFT);
 114     write_tercel_register(TERCEL_SPI_REG_SYS_PHY_CFG1, dword);
 115     // Enable read merging
 116     dword = read_tercel_register(TERCEL_SPI_REG_SYS_FLASH_CFG5);
 117     dword |= (TERCEL_SPI_FLASH_EN_MULTCYC_READ_MASK <<
 118               TERCEL_SPI_FLASH_EN_MULTCYC_READ_SHIFT);
 119     write_tercel_register(TERCEL_SPI_REG_SYS_FLASH_CFG5, dword);
 120
 121     puts("Trying flash...\r\n");
 122     if (!fl_read(&ehdr, offset, sizeof(ehdr)))
 123         return -1ul;
 124     if (!IS_ELF(ehdr) || ehdr.e_ident[EI_CLASS] != ELFCLASS64) {
 125         puts("Doesn't look like an elf64\r\n");
 126         goto dump;
 127     }
 128     if (ehdr.e_ident[EI_DATA] != ELFDATA2LSB ||
 129         ehdr.e_machine != EM_PPC64) {
 130         puts("Not a ppc64le binary\r\n");
 131         goto dump;
 132     }
 133
 134     poff = offset + ehdr.e_phoff;
 135     for (i = 0; i < ehdr.e_phnum; i++) {
 136         if (!fl_read(&ph, poff, sizeof(ph)))
 137             goto dump;
 138         if (ph.p_type != PT_LOAD)
 139             continue;
 140
 141         /* XXX Add bound checking ! */
 142         size = ph.p_filesz;
 143         addr = (void *)ph.p_vaddr;
 144         off  = offset + ph.p_offset;
 145         //printf("Copy segment %d (0x%x bytes) to %p\n", i, size, addr);
 146         puts("Copy segment ");
 147         uart_writeuint32(i);
 148         puts(" size ");
 149         uart_writeuint32(size);
 150         puts(" addr ");
 151         uart_writeuint32((uint32_t)(unsigned long)addr);
 152         puts("\r\n");
 153         fl_read(addr, off, size);
 154         poff += ehdr.e_phentsize;
 155     }
 156
 157     puts("Booting from DRAM at");
 158     uart_writeuint32((unsigned int)ehdr.e_entry);
 159     //flush_cpu_icache();
 160     return ehdr.e_entry;
 161 dump:
 162     puts("HDR: \r\n");
 163     for (i = 0; i < 8; i++) {
 164         uart_writeuint32(ehdr.e_ident[i]);
 165         puts("\r\n");
 166     }
 167
 168     return -1ul;
 169 }
 170
 171
 172 // XXX
 173 // Defining gram_[read|write] allows a trace of all register
 174 // accesses to be dumped to console for debugging purposes.
 175 // To use, define GRAM_RW_FUNC in gram.h
 176 uint32_t gram_read(const struct gramCtx *ctx, void *addr) {
 177         uint32_t dword;
 178
 179         puts("gram_read: ");
 180         uart_writeuint32((unsigned long)addr);
 181         dword = readl((unsigned long)addr);
 182         puts(": ");
 183         uart_writeuint32((unsigned long)dword);
 184         puts("\n");
 185
 186         return dword;
 187 }
 188
 189 int gram_write(const struct gramCtx *ctx, void *addr, uint32_t value) {
 190         puts("gram_write: ");
 191         uart_writeuint32((unsigned long)addr);
 192         puts(": ");
 193         uart_writeuint32((unsigned long)value);
 194         writel(value, (unsigned long)addr);
 195         puts("\n");
 196
 197         return 0;
 198 }
 199
 200 int main(void) {
 201         const int kNumIterations = 14;
 202         int res, failcnt = 0;
 203         uint32_t tmp;
 204     unsigned long ftr, spi_offs=0x0;
 205         volatile uint32_t *ram = (uint32_t*)MEMORY_BASE;
 206
 207         console_init();
 208         //puts("Firmware launched...\n");
 209
 210 #if 1
 211     puts(" Soc signature: ");
 212     tmp = readl(SYSCON_BASE + SYS_REG_SIGNATURE);
 213     uart_writeuint32(tmp);
 214     puts("  Soc features: ");
 215     ftr = readl(SYSCON_BASE + SYS_REG_INFO);
 216     if (ftr & SYS_REG_INFO_HAS_UART)
 217         puts("UART ");
 218     if (ftr & SYS_REG_INFO_HAS_DRAM)
 219         puts("DRAM ");
 220     if (ftr & SYS_REG_INFO_HAS_BRAM)
 221         puts("BRAM ");
 222     if (ftr & SYS_REG_INFO_HAS_SPI_FLASH)
 223         puts("SPIFLASH ");
 224     if (ftr & SYS_REG_INFO_HAS_LITEETH)
 225         puts("ETHERNET ");
 226     puts("\r\n");
 227
 228     if (ftr & SYS_REG_INFO_HAS_SPI_FLASH) {
 229         puts("SPI Offset: ");
 230         spi_offs = readl(SYSCON_BASE + SYS_REG_SPI_INFO);
 231         uart_writeuint32(spi_offs);
 232         puts("\r\n");
 233     }
 234
 235 #endif
 236
 237 #if 1
 238 #if 1
 239     // print out configuration parameters for QSPI
 240         volatile uint32_t *qspi_cfg = (uint32_t*)SPI_FCTRL_BASE;
 241     for (int k=0; k < 2; k++) {
 242         tmp = readl((unsigned long)&(qspi_cfg[k]));
 243         puts("cfg");
 244         uart_writeuint32(k);
 245         puts(" ");
 246         uart_writeuint32(tmp);
 247         puts("\n");
 248     }
 249 #endif
 250         volatile uint32_t *qspi = (uint32_t*)spi_offs;
 251     //volatile uint8_t *qspi_bytes = (uint8_t*)spi_offs;
 252      // let's not, eh? writel(0xDEAF0123, (unsigned long)&(qspi[0]));
 253      // tmp = readl((unsigned long)&(qspi[0]));
 254     for (int i=0;i<256;i++) {
 255       tmp = readl((unsigned long)&(qspi[i]));
 256       uart_writeuint32(tmp);
 257       puts(" ");
 258       if ((i & 0x7) == 0x7) puts("\r\n");
 259     }
 260     puts("\r\n");
 261     /*
 262     for (i=0;i<256;i++) {
 263       tmp = readb((unsigned long)&(qspi_bytes[i]));
 264       uart_writeuint32(tmp);
 265       puts(" ");
 266     }
 267     */
 268 #if 0
 269     while (1) {
 270         // quick read
 271         tmp = readl((unsigned long)&(qspi[0x1000/4]));
 272         puts("read 0x1000");
 273         uart_writeuint32(tmp);
 274         putchar(10);
 275     }
 276     while (1) {
 277         unsigned char c = getchar();
 278         putchar(c);
 279         if (c == 13) { // if CR send LF
 280
 281             // quick read
 282             tmp = readl((unsigned long)&(qspi[1<<i]));
 283             puts("read ");
 284             uart_writeuint32(1<<i);
 285             puts(" ");
 286             uart_writeuint32(tmp);
 287             putchar(10);
 288             i++;
 289         }
 290     }
 291
 292     return 0;
 293 #endif
 294 #endif
 295 #if 0
 296         volatile uint32_t *hyperram = (uint32_t*)0xa0000000;
 297     writel(0xDEAF0123, (unsigned long)&(hyperram[0]));
 298     tmp = readl((unsigned long)&(hyperram[0]));
 299     while (1) {
 300         unsigned char c = getchar();
 301         putchar(c);
 302         if (c == 13) { // if CR send LF
 303
 304             // quick write/read
 305             writel(0xDEAF0123+i, (unsigned long)&(hyperram[1<<i]));
 306             tmp = readl((unsigned long)&(hyperram[1<<i]));
 307             puts("read ");
 308             uart_writeuint32(1<<i);
 309             puts(" ");
 310             uart_writeuint32(tmp);
 311             putchar(10);
 312             i++;
 313         }
 314     }
 315
 316     return 0;
 317 #endif
 318
 319     for (int persistence=0; persistence < 1000; persistence++) {
 320         puts("DRAM init... ");
 321
 322         struct gramCtx ctx;
 323 #if 1
 324         struct gramProfile profile = {
 325             .mode_registers = {
 326                 0xb20, 0x806, 0x200, 0x0
 327             },
 328             .rdly_p0 = 2,
 329             .rdly_p1 = 2,
 330         };
 331 #endif
 332 #if 0
 333         struct gramProfile profile = {
 334             .mode_registers = {
 335                 0x0320, 0x0006, 0x0200, 0x0000
 336             },
 337             .rdly_p0 = 1,
 338             .rdly_p1 = 1,
 339         };
 340 #endif
 341         struct gramProfile profile2;
 342         gram_init(&ctx, &profile, (void*)MEMORY_BASE,
 343                                   (void*)DRAM_CTRL_BASE,
 344                                   (void*)DRAM_INIT_BASE);
 345         puts("done\n");
 346
 347         puts("MR profile: ");
 348         uart_writeuint32(profile.mode_registers[0]);
 349         puts(" ");
 350         uart_writeuint32(profile.mode_registers[1]);
 351         puts(" ");
 352         uart_writeuint32(profile.mode_registers[2]);
 353         puts(" ");
 354         uart_writeuint32(profile.mode_registers[3]);
 355         puts("\n");
 356
 357         // FIXME
 358         // Early read test for WB access sim
 359         //uart_writeuint32(*ram);
 360
 361 #if 1
 362         puts("Rdly\np0: ");
 363         for (size_t i = 0; i < 8; i++) {
 364             profile2.rdly_p0 = i;
 365             gram_load_calibration(&ctx, &profile2);
 366             gram_reset_burstdet(&ctx);
 367
 368             for (size_t j = 0; j < 128; j++) {
 369                 tmp = readl((unsigned long)&(ram[i]));
 370             }
 371             if (gram_read_burstdet(&ctx, 0)) {
 372                 puts("1");
 373             } else {
 374                 puts("0");
 375             }
 376         }
 377         puts("\n");
 378
 379         puts("Rdly\np1: ");
 380         for (size_t i = 0; i < 8; i++) {
 381             profile2.rdly_p1 = i;
 382             gram_load_calibration(&ctx, &profile2);
 383             gram_reset_burstdet(&ctx);
 384             for (size_t j = 0; j < 128; j++) {
 385                 tmp = readl((unsigned long)&(ram[i]));
 386             }
 387             if (gram_read_burstdet(&ctx, 1)) {
 388                 puts("1");
 389             } else {
 390                 puts("0");
 391             }
 392         }
 393         puts("\n");
 394
 395         puts("Auto calibrating... ");
 396         res = gram_generate_calibration(&ctx, &profile2);
 397         if (res != GRAM_ERR_NONE) {
 398             puts("failed\n");
 399             gram_load_calibration(&ctx, &profile);
 400         } else {
 401             gram_load_calibration(&ctx, &profile2);
 402         }
 403         puts("done\n");
 404
 405         puts("Auto calibration profile:");
 406         puts("p0 rdly:");
 407         uart_writeuint32(profile2.rdly_p0);
 408         puts(" p1 rdly:");
 409         uart_writeuint32(profile2.rdly_p1);
 410         puts("\n");
 411 #endif
 412
 413         puts("Reloading built-in calibration profile...");
 414         gram_load_calibration(&ctx, &profile);
 415
 416         puts("DRAM test... \n");
 417         for (size_t i = 0; i < kNumIterations; i++) {
 418             writel(0xDEAF0000 | i*4, (unsigned long)&(ram[i]));
 419         }
 420
 421 #if 0
 422         for (int dly = 0; dly < 8; dly++) {
 423             failcnt = 0;
 424             profile2.rdly_p0 = dly;
 425             profile2.rdly_p1 = dly;
 426             puts("p0 rdly:");
 427             uart_writeuint32(profile2.rdly_p0);
 428             puts(" p1 rdly:");
 429             uart_writeuint32(profile2.rdly_p1);
 430             gram_load_calibration(&ctx, &profile2);
 431             for (size_t i = 0; i < kNumIterations; i++) {
 432                 if (readl((unsigned long)&(ram[i])) != (0xDEAF0000 | i*4)) {
 433                     puts("fail : *(0x");
 434                     uart_writeuint32((unsigned long)(&ram[i]));
 435                     puts(") = ");
 436                     uart_writeuint32(readl((unsigned long)&(ram[i])));
 437                     puts("\n");
 438                     failcnt++;
 439
 440                     if (failcnt > 10) {
 441                         puts("Test canceled (more than 10 errors)\n");
 442                         break;
 443                     }
 444                 }
 445             }
 446         }
 447 #else
 448         failcnt = 0;
 449         for (size_t i = 0; i < kNumIterations; i++) {
 450             if (readl((unsigned long)&(ram[i])) != (0xDEAF0000 | i*4)) {
 451                 puts("fail : *(0x");
 452                 uart_writeuint32((unsigned long)(&ram[i]));
 453                 puts(") = ");
 454                 uart_writeuint32(readl((unsigned long)&(ram[i])));
 455                 puts("\n");
 456                 failcnt++;
 457
 458                 if (failcnt > 10) {
 459                     puts("Test canceled (more than 10 errors)\n");
 460                     break;
 461                 }
 462             }
 463         }
 464         if (failcnt == 0) { // fiinally...
 465             break;
 466         }
 467     }
 468 #endif
 469         puts("done\n");
 470
 471     // memcpy from SPI Flash to SDRAM then boot
 472     if ((ftr & SYS_REG_INFO_HAS_SPI_FLASH) &&
 473         (ftr & SYS_REG_INFO_HAS_DRAM) &&
 474         (failcnt == 0))
 475     {
 476         // identify ELF, copy if present, and get the start address
 477         unsigned long faddr = copy_flash(spi_offs);
 478         if (faddr != -1ul) {
 479             // jump to absolute address
 480             return faddr;
 481         }
 482     }
 483
 484         return 0;
 485 }
 486