coldboot/coldboot.c

   1 #include <stdint.h>
   2 #include <stdbool.h>
   3
   4 #include "console.h"
   5 #include "microwatt_soc.h"
   6 #include "io.h"
   7
   8 #include <stdlib.h>
   9 #include <stdint.h>
  10 #include <gram.h>
  11
  12 static inline uint32_t read32(const void *addr)
  13 {
  14         return *(volatile uint32_t *)addr;
  15 }
  16
  17 static inline void write32(void *addr, uint32_t value)
  18 {
  19         *(volatile uint32_t *)addr = value;
  20 }
  21
  22 struct uart_regs {
  23         uint32_t divisor;
  24         uint32_t rx_data;
  25         uint32_t rx_rdy;
  26         uint32_t rx_err;
  27         uint32_t tx_data;
  28         uint32_t tx_rdy;
  29         uint32_t zero0; // reserved
  30         uint32_t zero1; // reserved
  31         uint32_t ev_status;
  32         uint32_t ev_pending;
  33         uint32_t ev_enable;
  34 };
  35
  36 void memcpy(void *dest, void *src, size_t n) {
  37    int i;
  38    //cast src and dest to char*
  39    char *src_char = (char *)src;
  40    char *dest_char = (char *)dest;
  41    for (i=0; i<n; i++)
  42           dest_char[i] = src_char[i]; //copy contents byte by byte
  43 }
  44
  45 void uart_writeuint32(uint32_t val) {
  46         const char lut[] = { '0', '1', '2', '3', '4', '5', '6', '7',
  47                          '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
  48         uint8_t *val_arr = (uint8_t*)(&val);
  49         size_t i;
  50
  51         for (i = 0; i < 4; i++) {
  52                 putchar(lut[(val_arr[3-i] >> 4) & 0xF]);
  53                 putchar(lut[val_arr[3-i] & 0xF]);
  54         }
  55 }
  56
  57 void isr(void) {
  58
  59 }
  60
  61 // XXX
  62 // Defining gram_[read|write] allows a trace of all register
  63 // accesses to be dumped to console for debugging purposes.
  64 // To use, define GRAM_RW_FUNC in gram.h
  65 uint32_t gram_read(const struct gramCtx *ctx, void *addr) {
  66         uint32_t dword;
  67
  68         puts("gram_read: ");
  69         uart_writeuint32((unsigned long)addr);
  70         dword = readl((unsigned long)addr);
  71         puts(": ");
  72         uart_writeuint32((unsigned long)dword);
  73         puts("\n");
  74
  75         return dword;
  76 }
  77
  78 int gram_write(const struct gramCtx *ctx, void *addr, uint32_t value) {
  79         puts("gram_write: ");
  80         uart_writeuint32((unsigned long)addr);
  81         puts(": ");
  82         uart_writeuint32((unsigned long)value);
  83         writel(value, (unsigned long)addr);
  84         puts("\n");
  85
  86         return 0;
  87 }
  88
  89 int main(void) {
  90         const int kNumIterations = 14;
  91         int res, failcnt = 0;
  92         uint32_t tmp;
  93     unsigned long ftr, val;
  94         volatile uint32_t *ram = (uint32_t*)DRAM_BASE;
  95
  96         console_init();
  97         //puts("Firmware launched...\n");
  98
  99 #if 1
 100     puts(" Soc signature: ");
 101     tmp = readl(SYSCON_BASE + SYS_REG_SIGNATURE);
 102     uart_writeuint32(tmp);
 103     puts("  Soc features: ");
 104     ftr = readl(SYSCON_BASE + SYS_REG_INFO);
 105     if (ftr & SYS_REG_INFO_HAS_UART)
 106         puts("UART ");
 107     if (ftr & SYS_REG_INFO_HAS_DRAM)
 108         puts("DRAM ");
 109     if (ftr & SYS_REG_INFO_HAS_BRAM)
 110         puts("BRAM ");
 111     if (ftr & SYS_REG_INFO_HAS_SPI_FLASH)
 112         puts("SPIFLASH ");
 113     if (ftr & SYS_REG_INFO_HAS_LITEETH)
 114         puts("ETHERNET ");
 115     puts("\r\n");
 116
 117     if (ftr & SYS_REG_INFO_HAS_SPI_FLASH) {
 118         puts("SPI Offset: ");
 119         val = readl(SYSCON_BASE + SYS_REG_SPI_INFO);
 120         uart_writeuint32(val);
 121         puts("\r\n");
 122     }
 123
 124 #endif
 125
 126 #if 0
 127 #if 1
 128     // print out configuration parameters for QSPI
 129         volatile uint32_t *qspi_cfg = (uint32_t*)0xc0003000;
 130     for (int k=0; k < 2; k++) {
 131         tmp = readl((unsigned long)&(qspi_cfg[k]));
 132         //puts("cfg");
 133         //uart_writeuint32(k);
 134         //puts(" ");
 135         //uart_writeuint32(tmp);
 136         //puts("\n");
 137     }
 138 #endif
 139         volatile uint32_t *qspi = (uint32_t*)0x10000000;
 140        volatile uint8_t *qspi_bytes = (uint8_t*)0x10000000;
 141      // let's not, eh? writel(0xDEAF0123, (unsigned long)&(qspi[0]));
 142      // tmp = readl((unsigned long)&(qspi[0]));
 143 for (i=0;i<1000;i++) {
 144   tmp = readl((unsigned long)&(qspi[i]));
 145   uart_writeuint32(tmp);
 146   puts(" ");
 147 }
 148 putchar(10);
 149 putchar(10);
 150 for (i=0;i<1000;i++) {
 151   tmp = readb((unsigned long)&(qspi_bytes[i]));
 152   uart_writeuint32(tmp);
 153   puts(" ");
 154 }
 155 #if 1
 156     while (1) {
 157         // quick read
 158         tmp = readl((unsigned long)&(qspi[0x1000/4]));
 159         puts("read 0x1000");
 160         uart_writeuint32(tmp);
 161         putchar(10);
 162     }
 163 #endif
 164     while (1) {
 165         unsigned char c = getchar();
 166         putchar(c);
 167         if (c == 13) { // if CR send LF
 168
 169             // quick read
 170             tmp = readl((unsigned long)&(qspi[1<<i]));
 171             puts("read ");
 172             uart_writeuint32(1<<i);
 173             puts(" ");
 174             uart_writeuint32(tmp);
 175             putchar(10);
 176             i++;
 177         }
 178     }
 179
 180     return 0;
 181 #endif
 182 #if 0
 183         volatile uint32_t *hyperram = (uint32_t*)0xa0000000;
 184     writel(0xDEAF0123, (unsigned long)&(hyperram[0]));
 185     tmp = readl((unsigned long)&(hyperram[0]));
 186     while (1) {
 187         unsigned char c = getchar();
 188         putchar(c);
 189         if (c == 13) { // if CR send LF
 190
 191             // quick write/read
 192             writel(0xDEAF0123+i, (unsigned long)&(hyperram[1<<i]));
 193             tmp = readl((unsigned long)&(hyperram[1<<i]));
 194             puts("read ");
 195             uart_writeuint32(1<<i);
 196             puts(" ");
 197             uart_writeuint32(tmp);
 198             putchar(10);
 199             i++;
 200         }
 201     }
 202
 203     return 0;
 204 #endif
 205
 206     for (int persistence=0; persistence < 1000; persistence++) {
 207         puts("DRAM init... ");
 208
 209         struct gramCtx ctx;
 210 #if 1
 211         struct gramProfile profile = {
 212             .mode_registers = {
 213                 0xb20, 0x806, 0x200, 0x0
 214             },
 215             .rdly_p0 = 2,
 216             .rdly_p1 = 2,
 217         };
 218 #endif
 219 #if 0
 220         struct gramProfile profile = {
 221             .mode_registers = {
 222                 0x0320, 0x0006, 0x0200, 0x0000
 223             },
 224             .rdly_p0 = 1,
 225             .rdly_p1 = 1,
 226         };
 227 #endif
 228         struct gramProfile profile2;
 229         gram_init(&ctx, &profile, (void*)DRAM_BASE,
 230                                   (void*)DRAM_CTRL_BASE,
 231                                   (void*)DRAM_INIT_BASE);
 232         puts("done\n");
 233
 234         puts("MR profile: ");
 235         uart_writeuint32(profile.mode_registers[0]);
 236         puts(" ");
 237         uart_writeuint32(profile.mode_registers[1]);
 238         puts(" ");
 239         uart_writeuint32(profile.mode_registers[2]);
 240         puts(" ");
 241         uart_writeuint32(profile.mode_registers[3]);
 242         puts("\n");
 243
 244         // FIXME
 245         // Early read test for WB access sim
 246         //uart_writeuint32(*ram);
 247
 248 #if 1
 249         puts("Rdly\np0: ");
 250         for (size_t i = 0; i < 8; i++) {
 251             profile2.rdly_p0 = i;
 252             gram_load_calibration(&ctx, &profile2);
 253             gram_reset_burstdet(&ctx);
 254
 255             for (size_t j = 0; j < 128; j++) {
 256                 tmp = readl((unsigned long)&(ram[i]));
 257             }
 258             if (gram_read_burstdet(&ctx, 0)) {
 259                 puts("1");
 260             } else {
 261                 puts("0");
 262             }
 263         }
 264         puts("\n");
 265
 266         puts("Rdly\np1: ");
 267         for (size_t i = 0; i < 8; i++) {
 268             profile2.rdly_p1 = i;
 269             gram_load_calibration(&ctx, &profile2);
 270             gram_reset_burstdet(&ctx);
 271             for (size_t j = 0; j < 128; j++) {
 272                 tmp = readl((unsigned long)&(ram[i]));
 273             }
 274             if (gram_read_burstdet(&ctx, 1)) {
 275                 puts("1");
 276             } else {
 277                 puts("0");
 278             }
 279         }
 280         puts("\n");
 281
 282         puts("Auto calibrating... ");
 283         res = gram_generate_calibration(&ctx, &profile2);
 284         if (res != GRAM_ERR_NONE) {
 285             puts("failed\n");
 286             gram_load_calibration(&ctx, &profile);
 287         } else {
 288             gram_load_calibration(&ctx, &profile2);
 289         }
 290         puts("done\n");
 291
 292         puts("Auto calibration profile:");
 293         puts("p0 rdly:");
 294         uart_writeuint32(profile2.rdly_p0);
 295         puts(" p1 rdly:");
 296         uart_writeuint32(profile2.rdly_p1);
 297         puts("\n");
 298 #endif
 299
 300         puts("Reloading built-in calibration profile...");
 301         gram_load_calibration(&ctx, &profile);
 302
 303         puts("DRAM test... \n");
 304         for (size_t i = 0; i < kNumIterations; i++) {
 305             writel(0xDEAF0000 | i*4, (unsigned long)&(ram[i]));
 306         }
 307
 308 #if 0
 309         for (int dly = 0; dly < 8; dly++) {
 310             failcnt = 0;
 311             profile2.rdly_p0 = dly;
 312             profile2.rdly_p1 = dly;
 313             puts("p0 rdly:");
 314             uart_writeuint32(profile2.rdly_p0);
 315             puts(" p1 rdly:");
 316             uart_writeuint32(profile2.rdly_p1);
 317             gram_load_calibration(&ctx, &profile2);
 318             for (size_t i = 0; i < kNumIterations; i++) {
 319                 if (readl((unsigned long)&(ram[i])) != (0xDEAF0000 | i*4)) {
 320                     puts("fail : *(0x");
 321                     uart_writeuint32((unsigned long)(&ram[i]));
 322                     puts(") = ");
 323                     uart_writeuint32(readl((unsigned long)&(ram[i])));
 324                     puts("\n");
 325                     failcnt++;
 326
 327                     if (failcnt > 10) {
 328                         puts("Test canceled (more than 10 errors)\n");
 329                         break;
 330                     }
 331                 }
 332             }
 333         }
 334 #else
 335         failcnt = 0;
 336         for (size_t i = 0; i < kNumIterations; i++) {
 337             if (readl((unsigned long)&(ram[i])) != (0xDEAF0000 | i*4)) {
 338                 puts("fail : *(0x");
 339                 uart_writeuint32((unsigned long)(&ram[i]));
 340                 puts(") = ");
 341                 uart_writeuint32(readl((unsigned long)&(ram[i])));
 342                 puts("\n");
 343                 failcnt++;
 344
 345                 if (failcnt > 10) {
 346                     puts("Test canceled (more than 10 errors)\n");
 347                     break;
 348                 }
 349             }
 350         }
 351         if (failcnt == 0) { // fiinally...
 352             break;
 353         }
 354     }
 355 #endif
 356         puts("done\n");
 357
 358         return 0;
 359 }
 360