5 #include "microwatt_soc.h"
14 static inline void mtspr(int sprnum
, unsigned long val
)
16 __asm__
volatile("mtspr %0,%1" : : "i" (sprnum
), "r" (val
));
19 static inline uint32_t read32(const void *addr
)
21 return *(volatile uint32_t *)addr
;
24 static inline void write32(void *addr
, uint32_t value
)
26 *(volatile uint32_t *)addr
= value
;
36 uint32_t zero0
; // reserved
37 uint32_t zero1
; // reserved
43 void uart_writeuint32(uint32_t val
) {
44 const char lut
[] = { '0', '1', '2', '3', '4', '5', '6', '7',
45 '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
46 uint8_t *val_arr
= (uint8_t*)(&val
);
49 for (i
= 0; i
< 4; i
++) {
50 putchar(lut
[(val_arr
[3-i
] >> 4) & 0xF]);
51 putchar(lut
[val_arr
[3-i
] & 0xF]);
55 void memcpy(void *dest
, void *src
, size_t n
) {
57 //cast src and dest to char*
58 char *src_char
= (char *)src
;
59 char *dest_char
= (char *)dest
;
62 if ((i
% 4096) == 0) {
68 dest_char
[i
] = src_char
[i
]; //copy contents byte by byte
78 #define TERCEL_SPI_REG_SYS_PHY_CFG1 0x10
79 #define TERCEL_SPI_REG_SYS_FLASH_CFG5 0x24
80 #define TERCEL_SPI_PHY_CLOCK_DIVISOR_MASK 0xff
81 #define TERCEL_SPI_PHY_CLOCK_DIVISOR_SHIFT 0
82 #define TERCEL_SPI_FLASH_EN_MULTCYC_READ_MASK 0x1
83 #define TERCEL_SPI_FLASH_EN_MULTCYC_READ_SHIFT 0
84 static inline uint32_t read_tercel_register(uint8_t reg
)
86 return readl((unsigned long)(SPI_FCTRL_BASE
+reg
));
89 static inline void write_tercel_register(uint8_t reg
, uint32_t value
)
91 writel(value
, (unsigned long)(SPI_FCTRL_BASE
+reg
));
94 // TODO: need to use this
95 // https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-firmware/bare-metal-firmware/-/blob/master/main.c#L2328
97 /* this is a "level 1" speed-up, which gets an initial improvement of 10-50x
98 * over the default speed (which is a scant 100 bytes per second).
100 static void crank_up_qspi_level1(void)
102 // WARNING: KESTREL SPECIFIC
103 // Set SPI clock cycle divider to 1
105 dword
= read_tercel_register(TERCEL_SPI_REG_SYS_PHY_CFG1
);
106 dword
&= ~(TERCEL_SPI_PHY_CLOCK_DIVISOR_MASK
<<
107 TERCEL_SPI_PHY_CLOCK_DIVISOR_SHIFT
);
108 dword
|= ((1 & TERCEL_SPI_PHY_CLOCK_DIVISOR_MASK
) <<
109 TERCEL_SPI_PHY_CLOCK_DIVISOR_SHIFT
);
110 write_tercel_register(TERCEL_SPI_REG_SYS_PHY_CFG1
, dword
);
111 // Enable read merging
112 dword
= read_tercel_register(TERCEL_SPI_REG_SYS_FLASH_CFG5
);
113 dword
|= (TERCEL_SPI_FLASH_EN_MULTCYC_READ_MASK
<<
114 TERCEL_SPI_FLASH_EN_MULTCYC_READ_SHIFT
);
115 write_tercel_register(TERCEL_SPI_REG_SYS_FLASH_CFG5
, dword
);
118 static bool fl_read(void *dst
, uint32_t offset
, uint32_t size
)
121 memcpy(d
, (void *)(unsigned long)(SPI_FLASH_BASE
+ offset
), size
);
125 static unsigned long copy_flash(unsigned int offset
, unsigned int dst_offs
)
129 unsigned int i
, poff
, size
, off
;
132 puts("Trying flash...\r\n");
133 if (!fl_read(&ehdr
, offset
, sizeof(ehdr
)))
135 if (!IS_ELF(ehdr
) || ehdr
.e_ident
[EI_CLASS
] != ELFCLASS64
) {
136 puts("Doesn't look like an elf64\r\n");
139 if (ehdr
.e_ident
[EI_DATA
] != ELFDATA2LSB
||
140 ehdr
.e_machine
!= EM_PPC64
) {
141 puts("Not a ppc64le binary\r\n");
145 poff
= offset
+ ehdr
.e_phoff
;
146 for (i
= 0; i
< ehdr
.e_phnum
; i
++) {
147 if (!fl_read(&ph
, poff
, sizeof(ph
)))
149 if (ph
.p_type
!= PT_LOAD
)
152 /* XXX Add bound checking ! */
154 addr
= (void *)ph
.p_vaddr
;
155 off
= offset
+ ph
.p_offset
;
156 //printf("Copy segment %d (0x%x bytes) to %p\n", i, size, addr);
157 puts("Copy segment ");
160 uart_writeuint32(size
);
162 uart_writeuint32((uint32_t)(unsigned long)addr
);
164 fl_read(addr
+dst_offs
, off
, size
);
165 poff
+= ehdr
.e_phentsize
;
168 puts("Booting from DRAM at");
169 uart_writeuint32((unsigned int)(dst_offs
+ehdr
.e_entry
));
172 puts("Dump DRAM\r\n");
173 for (i
= 0; i
< 64; i
++) {
174 uart_writeuint32(readl(dst_offs
+ehdr
.e_entry
+(i
*4)));
176 if ((i
& 7) == 7) puts("\r\n");
180 //flush_cpu_icache();
181 return dst_offs
+ehdr
.e_entry
;
184 for (i
= 0; i
< 8; i
++) {
185 uart_writeuint32(ehdr
.e_ident
[i
]);
194 // Defining gram_[read|write] allows a trace of all register
195 // accesses to be dumped to console for debugging purposes.
196 // To use, define GRAM_RW_FUNC in gram.h
197 uint32_t gram_read(const struct gramCtx
*ctx
, void *addr
) {
201 uart_writeuint32((unsigned long)addr
);
202 dword
= readl((unsigned long)addr
);
204 uart_writeuint32((unsigned long)dword
);
210 int gram_write(const struct gramCtx
*ctx
, void *addr
, uint32_t value
) {
211 puts("gram_write: ");
212 uart_writeuint32((unsigned long)addr
);
214 uart_writeuint32((unsigned long)value
);
215 writel(value
, (unsigned long)addr
);
222 const int kNumIterations
= 14;
223 int res
, failcnt
= 0;
225 unsigned long ftr
, spi_offs
=0x0;
226 volatile uint32_t *ram
= (uint32_t*)MEMORY_BASE
;
229 //puts("Firmware launched...\n");
232 puts(" Soc signature: ");
233 tmp
= readl(SYSCON_BASE
+ SYS_REG_SIGNATURE
);
234 uart_writeuint32(tmp
);
235 puts(" Soc features: ");
236 ftr
= readl(SYSCON_BASE
+ SYS_REG_INFO
);
237 if (ftr
& SYS_REG_INFO_HAS_UART
)
239 if (ftr
& SYS_REG_INFO_HAS_DRAM
)
241 if (ftr
& SYS_REG_INFO_HAS_BRAM
)
243 if (ftr
& SYS_REG_INFO_HAS_SPI_FLASH
)
245 if (ftr
& SYS_REG_INFO_HAS_LITEETH
)
249 if (ftr
& SYS_REG_INFO_HAS_SPI_FLASH
) {
250 // speed up the QSPI to at least a sane level
251 crank_up_qspi_level1();
253 puts("SPI Offset: ");
254 spi_offs
= readl(SYSCON_BASE
+ SYS_REG_SPI_INFO
);
255 uart_writeuint32(spi_offs
);
263 // print out configuration parameters for QSPI
264 volatile uint32_t *qspi_cfg
= (uint32_t*)SPI_FCTRL_BASE
;
265 for (int k
=0; k
< 2; k
++) {
266 tmp
= readl((unsigned long)&(qspi_cfg
[k
]));
270 uart_writeuint32(tmp
);
274 volatile uint32_t *qspi
= (uint32_t*)SPI_FLASH_BASE
;
275 //volatile uint8_t *qspi_bytes = (uint8_t*)spi_offs;
276 // let's not, eh? writel(0xDEAF0123, (unsigned long)&(qspi[0]));
277 // tmp = readl((unsigned long)&(qspi[0]));
278 for (int i
=0;i
<256;i
++) {
279 tmp
= readl((unsigned long)&(qspi
[i
]));
280 uart_writeuint32(tmp
);
282 if ((i
& 0x7) == 0x7) puts("\r\n");
286 for (i=0;i<256;i++) {
287 tmp = readb((unsigned long)&(qspi_bytes[i]));
288 uart_writeuint32(tmp);
295 tmp
= readl((unsigned long)&(qspi
[0x1000/4]));
297 uart_writeuint32(tmp
);
301 unsigned char c
= getchar();
303 if (c
== 13) { // if CR send LF
306 tmp
= readl((unsigned long)&(qspi
[1<<i
]));
308 uart_writeuint32(1<<i
);
310 uart_writeuint32(tmp
);
320 volatile uint32_t *hyperram
= (uint32_t*)0xa0000000;
321 writel(0xDEAF0123, (unsigned long)&(hyperram
[0]));
322 tmp
= readl((unsigned long)&(hyperram
[0]));
324 unsigned char c
= getchar();
326 if (c
== 13) { // if CR send LF
329 writel(0xDEAF0123+i
, (unsigned long)&(hyperram
[1<<i
]));
330 tmp
= readl((unsigned long)&(hyperram
[1<<i
]));
332 uart_writeuint32(1<<i
);
334 uart_writeuint32(tmp
);
343 // init DRAM only if SYSCON says it exists (duh)
344 if (ftr
& SYS_REG_INFO_HAS_DRAM
)
346 puts("DRAM init... ");
350 struct gramProfile profile
= {
352 0xb20, 0x806, 0x200, 0x0
359 struct gramProfile profile
= {
361 0x0320, 0x0006, 0x0200, 0x0000
367 struct gramProfile profile2
;
368 gram_init(&ctx
, &profile
, (void*)MEMORY_BASE
,
369 (void*)DRAM_CTRL_BASE
,
370 (void*)DRAM_INIT_BASE
);
373 puts("MR profile: ");
374 uart_writeuint32(profile
.mode_registers
[0]);
376 uart_writeuint32(profile
.mode_registers
[1]);
378 uart_writeuint32(profile
.mode_registers
[2]);
380 uart_writeuint32(profile
.mode_registers
[3]);
384 // Early read test for WB access sim
385 //uart_writeuint32(*ram);
389 for (size_t i
= 0; i
< 8; i
++) {
390 profile2
.rdly_p0
= i
;
391 gram_load_calibration(&ctx
, &profile2
);
392 gram_reset_burstdet(&ctx
);
394 for (size_t j
= 0; j
< 128; j
++) {
395 tmp
= readl((unsigned long)&(ram
[i
]));
397 if (gram_read_burstdet(&ctx
, 0)) {
406 for (size_t i
= 0; i
< 8; i
++) {
407 profile2
.rdly_p1
= i
;
408 gram_load_calibration(&ctx
, &profile2
);
409 gram_reset_burstdet(&ctx
);
410 for (size_t j
= 0; j
< 128; j
++) {
411 tmp
= readl((unsigned long)&(ram
[i
]));
413 if (gram_read_burstdet(&ctx
, 1)) {
421 puts("Auto calibrating... ");
422 res
= gram_generate_calibration(&ctx
, &profile2
);
423 if (res
!= GRAM_ERR_NONE
) {
425 gram_load_calibration(&ctx
, &profile
);
427 gram_load_calibration(&ctx
, &profile2
);
431 puts("Auto calibration profile:");
433 uart_writeuint32(profile2
.rdly_p0
);
435 uart_writeuint32(profile2
.rdly_p1
);
439 puts("Reloading built-in calibration profile...");
440 gram_load_calibration(&ctx
, &profile
);
442 puts("DRAM test... \n");
443 for (size_t i
= 0; i
< kNumIterations
; i
++) {
444 writel(0xDEAF0000 | i
*4, (unsigned long)&(ram
[i
]));
448 for (int dly
= 0; dly
< 8; dly
++) {
450 profile2
.rdly_p0
= dly
;
451 profile2
.rdly_p1
= dly
;
453 uart_writeuint32(profile2
.rdly_p0
);
455 uart_writeuint32(profile2
.rdly_p1
);
456 gram_load_calibration(&ctx
, &profile2
);
457 for (size_t i
= 0; i
< kNumIterations
; i
++) {
458 if (readl((unsigned long)&(ram
[i
])) != (0xDEAF0000 | i
*4)) {
460 uart_writeuint32((unsigned long)(&ram
[i
]));
462 uart_writeuint32(readl((unsigned long)&(ram
[i
])));
467 puts("Test canceled (more than 10 errors)\n");
475 for (size_t i
= 0; i
< kNumIterations
; i
++) {
476 if (readl((unsigned long)&(ram
[i
])) != (0xDEAF0000 | i
*4)) {
478 uart_writeuint32((unsigned long)(&ram
[i
]));
480 uart_writeuint32(readl((unsigned long)&(ram
[i
])));
485 puts("Test canceled (more than 10 errors)\n");
494 #if 0 // ooo, annoying: won't work. no idea why
495 // temporary hard-hack: boot directly from QSPI. really
496 // should do something like detect at least... something
497 if ((ftr
& SYS_REG_INFO_HAS_SPI_FLASH
))
499 // jump to absolute address
500 mtspr(8, SPI_FLASH_BASE
); // move address to LR
501 __asm__
volatile("blr");
506 // memcpy from SPI Flash then boot
507 if ((ftr
& SYS_REG_INFO_HAS_SPI_FLASH
) &&
511 puts("ELF @ QSPI\n");
512 // identify ELF, copy if present, and get the start address
513 unsigned long faddr = copy_flash(spi_offs,
516 // jump to absolute address
517 mtspr(8, faddr); // move address to LR
518 __asm__ volatile("blr");
520 // works with head.S which copies r3 into ctr then does bctr
525 // another terrible hack: copy from flash at offset 0x600000
526 // a block of size 0x600000 into mem address 0x600000, then
527 // jump to it. this allows a dtb image to be executed
528 uint32_t *mem
= (uint32_t*)0x600000;
529 fl_read(mem
, 0x600000, 0x600000);
530 mtspr(8, 0x600000); // move address to LR
531 __asm__
volatile("blr");