common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9     -- Processor Version Number
  10     constant PVR_MICROWATT  : std_ulogic_vector(31 downto 0) := x"00630000";
  11
  12     -- MSR bit numbers
  13     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  14     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  15     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  16     constant MSR_FP  : integer := (63 - 50);    -- Floating Point available
  17     constant MSR_FE0 : integer := (63 - 52);    -- Floating Exception mode
  18     constant MSR_SE  : integer := (63 - 53);    -- Single-step bit of TE field
  19     constant MSR_BE  : integer := (63 - 54);    -- Branch trace bit of TE field
  20     constant MSR_FE1 : integer := (63 - 55);    -- Floating Exception mode
  21     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  22     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  23     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  24     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  25
  26     -- SPR numbers
  27     subtype spr_num_t is integer range 0 to 1023;
  28
  29     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  30
  31     constant SPR_XER    : spr_num_t := 1;
  32     constant SPR_LR     : spr_num_t := 8;
  33     constant SPR_CTR    : spr_num_t := 9;
  34     constant SPR_TAR    : spr_num_t := 815;
  35     constant SPR_DSISR  : spr_num_t := 18;
  36     constant SPR_DAR    : spr_num_t := 19;
  37     constant SPR_TB     : spr_num_t := 268;
  38     constant SPR_TBU    : spr_num_t := 269;
  39     constant SPR_DEC    : spr_num_t := 22;
  40     constant SPR_SRR0   : spr_num_t := 26;
  41     constant SPR_SRR1   : spr_num_t := 27;
  42     constant SPR_CFAR   : spr_num_t := 28;
  43     constant SPR_HSRR0  : spr_num_t := 314;
  44     constant SPR_HSRR1  : spr_num_t := 315;
  45     constant SPR_SPRG0  : spr_num_t := 272;
  46     constant SPR_SPRG1  : spr_num_t := 273;
  47     constant SPR_SPRG2  : spr_num_t := 274;
  48     constant SPR_SPRG3  : spr_num_t := 275;
  49     constant SPR_SPRG3U : spr_num_t := 259;
  50     constant SPR_HSPRG0 : spr_num_t := 304;
  51     constant SPR_HSPRG1 : spr_num_t := 305;
  52     constant SPR_PID    : spr_num_t := 48;
  53     constant SPR_PRTBL  : spr_num_t := 720;
  54     constant SPR_PVR    : spr_num_t := 287;
  55
  56     -- GPR indices in the register file (GPR only)
  57     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  58
  59     -- Extended GPR index (can hold an SPR or a FPR)
  60     subtype gspr_index_t is std_ulogic_vector(6 downto 0);
  61
  62     -- FPR indices
  63     subtype fpr_index_t is std_ulogic_vector(4 downto 0);
  64
  65     -- Some SPRs are stored in the register file, they use the magic
  66     -- GPR numbers above 31.
  67     --
  68     -- The function fast_spr_num() returns the corresponding fast
  69     -- pseudo-GPR number for a given SPR number. The result MSB
  70     -- indicates if this is indeed a fast SPR. If clear, then
  71     -- the SPR is not stored in the GPR file.
  72     --
  73     -- FPRs are also stored in the register file, using GSPR
  74     -- numbers from 64 to 95.
  75     --
  76     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  77
  78     -- Indices conversion functions
  79     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  80     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  81     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  82     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  83     function fpr_to_gspr(f: fpr_index_t) return gspr_index_t;
  84
  85     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  86     -- in the CR file as a kind of CR extension (with a separate write
  87     -- control). The rest is stored as a fast SPR.
  88     type xer_common_t is record
  89         ca : std_ulogic;
  90         ca32 : std_ulogic;
  91         ov : std_ulogic;
  92         ov32 : std_ulogic;
  93         so : std_ulogic;
  94     end record;
  95     constant xerc_init : xer_common_t := (others => '0');
  96
  97     -- FPSCR bit numbers
  98     constant FPSCR_FX     : integer := 63 - 32;
  99     constant FPSCR_FEX    : integer := 63 - 33;
 100     constant FPSCR_VX     : integer := 63 - 34;
 101     constant FPSCR_OX     : integer := 63 - 35;
 102     constant FPSCR_UX     : integer := 63 - 36;
 103     constant FPSCR_ZX     : integer := 63 - 37;
 104     constant FPSCR_XX     : integer := 63 - 38;
 105     constant FPSCR_VXSNAN : integer := 63 - 39;
 106     constant FPSCR_VXISI  : integer := 63 - 40;
 107     constant FPSCR_VXIDI  : integer := 63 - 41;
 108     constant FPSCR_VXZDZ  : integer := 63 - 42;
 109     constant FPSCR_VXIMZ  : integer := 63 - 43;
 110     constant FPSCR_VXVC   : integer := 63 - 44;
 111     constant FPSCR_FR     : integer := 63 - 45;
 112     constant FPSCR_FI     : integer := 63 - 46;
 113     constant FPSCR_C      : integer := 63 - 47;
 114     constant FPSCR_FL     : integer := 63 - 48;
 115     constant FPSCR_FG     : integer := 63 - 49;
 116     constant FPSCR_FE     : integer := 63 - 50;
 117     constant FPSCR_FU     : integer := 63 - 51;
 118     constant FPSCR_VXSOFT : integer := 63 - 53;
 119     constant FPSCR_VXSQRT : integer := 63 - 54;
 120     constant FPSCR_VXCVI  : integer := 63 - 55;
 121     constant FPSCR_VE     : integer := 63 - 56;
 122     constant FPSCR_OE     : integer := 63 - 57;
 123     constant FPSCR_UE     : integer := 63 - 58;
 124     constant FPSCR_ZE     : integer := 63 - 59;
 125     constant FPSCR_XE     : integer := 63 - 60;
 126     constant FPSCR_NI     : integer := 63 - 61;
 127     constant FPSCR_RN     : integer := 63 - 63;
 128
 129     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
 130
 131     -- For now, fixed 16 sources, make this either a parametric
 132     -- package of some sort or an unconstrainted array.
 133     type ics_to_icp_t is record
 134         -- Level interrupts only, ICS just keeps prsenting the
 135         -- highest priority interrupt. Once handling edge, something
 136         -- smarter involving handshake & reject support will be needed
 137         src : std_ulogic_vector(3 downto 0);
 138         pri : std_ulogic_vector(7 downto 0);
 139     end record;
 140
 141     -- This needs to die...
 142     type ctrl_t is record
 143         tb: std_ulogic_vector(63 downto 0);
 144         dec: std_ulogic_vector(63 downto 0);
 145         msr: std_ulogic_vector(63 downto 0);
 146         cfar: std_ulogic_vector(63 downto 0);
 147         irq_state : irq_state_t;
 148         srr1: std_ulogic_vector(63 downto 0);
 149     end record;
 150
 151     type Fetch1ToIcacheType is record
 152         req: std_ulogic;
 153         virt_mode : std_ulogic;
 154         priv_mode : std_ulogic;
 155         big_endian : std_ulogic;
 156         stop_mark: std_ulogic;
 157         sequential: std_ulogic;
 158         nia: std_ulogic_vector(63 downto 0);
 159     end record;
 160
 161     type IcacheToDecode1Type is record
 162         valid: std_ulogic;
 163         stop_mark: std_ulogic;
 164         fetch_failed: std_ulogic;
 165         nia: std_ulogic_vector(63 downto 0);
 166         insn: std_ulogic_vector(31 downto 0);
 167     end record;
 168
 169     type Decode1ToDecode2Type is record
 170         valid: std_ulogic;
 171         stop_mark : std_ulogic;
 172         nia: std_ulogic_vector(63 downto 0);
 173         insn: std_ulogic_vector(31 downto 0);
 174         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 175         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 176         decode: decode_rom_t;
 177         br_pred: std_ulogic; -- Branch was predicted to be taken
 178     end record;
 179     constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
 180         (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
 181          ispr1 => (others => '0'), ispr2 => (others => '0'), decode => decode_rom_init, br_pred => '0');
 182
 183     type Decode1ToFetch1Type is record
 184         redirect     : std_ulogic;
 185         redirect_nia : std_ulogic_vector(63 downto 0);
 186     end record;
 187
 188     type Decode2ToExecute1Type is record
 189         valid: std_ulogic;
 190         unit : unit_t;
 191         insn_type: insn_type_t;
 192         nia: std_ulogic_vector(63 downto 0);
 193         write_reg: gspr_index_t;
 194         read_reg1: gspr_index_t;
 195         read_reg2: gspr_index_t;
 196         read_data1: std_ulogic_vector(63 downto 0);
 197         read_data2: std_ulogic_vector(63 downto 0);
 198         read_data3: std_ulogic_vector(63 downto 0);
 199         bypass_data1: std_ulogic;
 200         bypass_data2: std_ulogic;
 201         bypass_data3: std_ulogic;
 202         cr: std_ulogic_vector(31 downto 0);
 203         bypass_cr : std_ulogic;
 204         xerc: xer_common_t;
 205         lr: std_ulogic;
 206         rc: std_ulogic;
 207         oe: std_ulogic;
 208         invert_a: std_ulogic;
 209         invert_out: std_ulogic;
 210         input_carry: carry_in_t;
 211         output_carry: std_ulogic;
 212         input_cr: std_ulogic;
 213         output_cr: std_ulogic;
 214         is_32bit: std_ulogic;
 215         is_signed: std_ulogic;
 216         insn: std_ulogic_vector(31 downto 0);
 217         data_len: std_ulogic_vector(3 downto 0);
 218         byte_reverse : std_ulogic;
 219         sign_extend : std_ulogic;                       -- do we need to sign extend?
 220         update : std_ulogic;                            -- is this an update instruction?
 221         reserve : std_ulogic;                           -- set for larx/stcx
 222         br_pred : std_ulogic;
 223     end record;
 224     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 225         (valid => '0', unit => NONE, insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 226          bypass_cr => '0', lr => '0', rc => '0', oe => '0', invert_a => '0',
 227          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 228          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
 229          byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'), read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'), cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'), others => (others => '0'));
 230
 231     type MultiplyInputType is record
 232         valid: std_ulogic;
 233         data1: std_ulogic_vector(63 downto 0);
 234         data2: std_ulogic_vector(63 downto 0);
 235         addend: std_ulogic_vector(127 downto 0);
 236         is_32bit: std_ulogic;
 237         not_result: std_ulogic;
 238     end record;
 239     constant MultiplyInputInit : MultiplyInputType := (valid => '0',
 240                                                        is_32bit => '0', not_result => '0',
 241                                                        others => (others => '0'));
 242
 243     type MultiplyOutputType is record
 244         valid: std_ulogic;
 245         result: std_ulogic_vector(127 downto 0);
 246         overflow : std_ulogic;
 247     end record;
 248     constant MultiplyOutputInit : MultiplyOutputType := (valid => '0', overflow => '0',
 249                                                          others => (others => '0'));
 250
 251     type Execute1ToDividerType is record
 252         valid: std_ulogic;
 253         dividend: std_ulogic_vector(63 downto 0);
 254         divisor: std_ulogic_vector(63 downto 0);
 255         is_signed: std_ulogic;
 256         is_32bit: std_ulogic;
 257         is_extended: std_ulogic;
 258         is_modulus: std_ulogic;
 259         neg_result: std_ulogic;
 260     end record;
 261     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 262                                                               is_extended => '0', is_modulus => '0',
 263                                                               neg_result => '0', others => (others => '0'));
 264
 265     type Decode2ToRegisterFileType is record
 266         read1_enable : std_ulogic;
 267         read1_reg : gspr_index_t;
 268         read2_enable : std_ulogic;
 269         read2_reg : gspr_index_t;
 270         read3_enable : std_ulogic;
 271         read3_reg : gspr_index_t;
 272     end record;
 273
 274     type RegisterFileToDecode2Type is record
 275         read1_data : std_ulogic_vector(63 downto 0);
 276         read2_data : std_ulogic_vector(63 downto 0);
 277         read3_data : std_ulogic_vector(63 downto 0);
 278     end record;
 279
 280     type Decode2ToCrFileType is record
 281         read : std_ulogic;
 282     end record;
 283
 284     type CrFileToDecode2Type is record
 285         read_cr_data   : std_ulogic_vector(31 downto 0);
 286         read_xerc_data : xer_common_t;
 287     end record;
 288
 289     type Execute1ToFetch1Type is record
 290         redirect: std_ulogic;
 291         virt_mode: std_ulogic;
 292         priv_mode: std_ulogic;
 293         big_endian: std_ulogic;
 294         mode_32bit: std_ulogic;
 295         redirect_nia: std_ulogic_vector(63 downto 0);
 296     end record;
 297     constant Execute1ToFetch1Init : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
 298                                                              priv_mode => '0', big_endian => '0',
 299                                                              mode_32bit => '0', others => (others => '0'));
 300
 301     type Execute1ToLoadstore1Type is record
 302         valid : std_ulogic;
 303         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 304         nia : std_ulogic_vector(63 downto 0);
 305         insn : std_ulogic_vector(31 downto 0);
 306         addr1 : std_ulogic_vector(63 downto 0);
 307         addr2 : std_ulogic_vector(63 downto 0);
 308         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 309         write_reg : gspr_index_t;
 310         length : std_ulogic_vector(3 downto 0);
 311         ci : std_ulogic;                                -- cache-inhibited load/store
 312         byte_reverse : std_ulogic;
 313         sign_extend : std_ulogic;                       -- do we need to sign extend?
 314         update : std_ulogic;                            -- is this an update instruction?
 315         update_reg : gpr_index_t;                       -- if so, the register to update
 316         xerc : xer_common_t;
 317         reserve : std_ulogic;                           -- set for larx/stcx.
 318         rc : std_ulogic;                                -- set for stcx.
 319         virt_mode : std_ulogic;                         -- do translation through TLB
 320         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 321         mode_32bit : std_ulogic;                        -- trim addresses to 32 bits
 322         is_32bit : std_ulogic;
 323     end record;
 324     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 325                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 326                                                                      reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 327                                                                      nia => (others => '0'), insn => (others => '0'),
 328                                                                      addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'),
 329                                                                      write_reg => (others => '0'), length => (others => '0'),
 330                                                                      mode_32bit => '0', is_32bit => '0', others => (others => '0'));
 331
 332     type Loadstore1ToExecute1Type is record
 333         busy : std_ulogic;
 334         exception : std_ulogic;
 335         alignment : std_ulogic;
 336         invalid : std_ulogic;
 337         perm_error : std_ulogic;
 338         rc_error : std_ulogic;
 339         badtree : std_ulogic;
 340         segment_fault : std_ulogic;
 341         instr_fault : std_ulogic;
 342     end record;
 343
 344     type Loadstore1ToDcacheType is record
 345         valid : std_ulogic;
 346         load : std_ulogic;                              -- is this a load
 347         dcbz : std_ulogic;
 348         nc : std_ulogic;
 349         reserve : std_ulogic;
 350         virt_mode : std_ulogic;
 351         priv_mode : std_ulogic;
 352         addr : std_ulogic_vector(63 downto 0);
 353         data : std_ulogic_vector(63 downto 0);
 354         byte_sel : std_ulogic_vector(7 downto 0);
 355     end record;
 356
 357     type DcacheToLoadstore1Type is record
 358         valid : std_ulogic;
 359         data : std_ulogic_vector(63 downto 0);
 360         store_done : std_ulogic;
 361         error : std_ulogic;
 362         cache_paradox : std_ulogic;
 363     end record;
 364
 365     type Loadstore1ToMmuType is record
 366         valid : std_ulogic;
 367         tlbie : std_ulogic;
 368         slbia : std_ulogic;
 369         mtspr : std_ulogic;
 370         iside : std_ulogic;
 371         load  : std_ulogic;
 372         priv  : std_ulogic;
 373         sprn  : std_ulogic_vector(9 downto 0);
 374         addr  : std_ulogic_vector(63 downto 0);
 375         rs    : std_ulogic_vector(63 downto 0);
 376     end record;
 377
 378     type MmuToLoadstore1Type is record
 379         done       : std_ulogic;
 380         err        : std_ulogic;
 381         invalid    : std_ulogic;
 382         badtree    : std_ulogic;
 383         segerr     : std_ulogic;
 384         perm_error : std_ulogic;
 385         rc_error   : std_ulogic;
 386         sprval     : std_ulogic_vector(63 downto 0);
 387     end record;
 388
 389     type MmuToDcacheType is record
 390         valid : std_ulogic;
 391         tlbie : std_ulogic;
 392         doall : std_ulogic;
 393         tlbld : std_ulogic;
 394         addr  : std_ulogic_vector(63 downto 0);
 395         pte   : std_ulogic_vector(63 downto 0);
 396     end record;
 397
 398     type DcacheToMmuType is record
 399         stall : std_ulogic;
 400         done  : std_ulogic;
 401         err   : std_ulogic;
 402         data  : std_ulogic_vector(63 downto 0);
 403     end record;
 404
 405     type MmuToIcacheType is record
 406         tlbld : std_ulogic;
 407         tlbie : std_ulogic;
 408         doall : std_ulogic;
 409         addr  : std_ulogic_vector(63 downto 0);
 410         pte   : std_ulogic_vector(63 downto 0);
 411     end record;
 412
 413     type Loadstore1ToWritebackType is record
 414         valid : std_ulogic;
 415         write_enable: std_ulogic;
 416         write_reg : gspr_index_t;
 417         write_data : std_ulogic_vector(63 downto 0);
 418         xerc : xer_common_t;
 419         rc : std_ulogic;
 420         store_done : std_ulogic;
 421     end record;
 422     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 423                                                                        rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
 424
 425     type Execute1ToWritebackType is record
 426         valid: std_ulogic;
 427         rc : std_ulogic;
 428         mode_32bit : std_ulogic;
 429         write_enable : std_ulogic;
 430         write_reg: gspr_index_t;
 431         write_data: std_ulogic_vector(63 downto 0);
 432         write_cr_enable : std_ulogic;
 433         write_cr_mask : std_ulogic_vector(7 downto 0);
 434         write_cr_data : std_ulogic_vector(31 downto 0);
 435         write_xerc_enable : std_ulogic;
 436         xerc : xer_common_t;
 437         exc_write_enable : std_ulogic;
 438         exc_write_reg : gspr_index_t;
 439         exc_write_data : std_ulogic_vector(63 downto 0);
 440     end record;
 441     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', mode_32bit => '0', write_enable => '0',
 442                                                                    write_cr_enable => '0', exc_write_enable => '0',
 443                                                                    write_xerc_enable => '0', xerc => xerc_init,
 444                                    write_data => (others => '0'), write_cr_mask => (others => '0'),
 445                                    write_cr_data => (others => '0'), write_reg => (others => '0'),
 446                                    exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
 447
 448     type Execute1ToFPUType is record
 449         valid   : std_ulogic;
 450         op      : insn_type_t;
 451         nia     : std_ulogic_vector(63 downto 0);
 452         insn    : std_ulogic_vector(31 downto 0);
 453         single  : std_ulogic;
 454         fe_mode : std_ulogic_vector(1 downto 0);
 455         fra     : std_ulogic_vector(63 downto 0);
 456         frb     : std_ulogic_vector(63 downto 0);
 457         frc     : std_ulogic_vector(63 downto 0);
 458         frt     : gspr_index_t;
 459         rc      : std_ulogic;
 460         out_cr  : std_ulogic;
 461     end record;
 462     constant Execute1ToFPUInit : Execute1ToFPUType := (valid => '0', op => OP_ILLEGAL, nia => (others => '0'),
 463                                                        insn  => (others => '0'), fe_mode => "00", rc => '0',
 464                                                        fra => (others => '0'), frb => (others => '0'),
 465                                                        frc => (others => '0'), frt => (others => '0'),
 466                                                        single => '0', out_cr => '0');
 467
 468     type FPUToExecute1Type is record
 469         busy      : std_ulogic;
 470         exception : std_ulogic;
 471         interrupt : std_ulogic;
 472         illegal   : std_ulogic;
 473     end record;
 474     constant FPUToExecute1Init : FPUToExecute1Type := (others => '0');
 475
 476     type FPUToWritebackType is record
 477         valid           : std_ulogic;
 478         write_enable    : std_ulogic;
 479         write_reg       : gspr_index_t;
 480         write_data      : std_ulogic_vector(63 downto 0);
 481         write_cr_enable : std_ulogic;
 482         write_cr_mask   : std_ulogic_vector(7 downto 0);
 483         write_cr_data   : std_ulogic_vector(31 downto 0);
 484     end record;
 485     constant FPUToWritebackInit : FPUToWritebackType :=  (valid => '0', write_enable => '0', write_cr_enable => '0', others => (others => '0'));
 486
 487     type DividerToExecute1Type is record
 488         valid: std_ulogic;
 489         write_reg_data: std_ulogic_vector(63 downto 0);
 490         overflow : std_ulogic;
 491     end record;
 492     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 493                                                                others => (others => '0'));
 494
 495     type WritebackToRegisterFileType is record
 496         write_reg : gspr_index_t;
 497         write_data : std_ulogic_vector(63 downto 0);
 498         write_enable : std_ulogic;
 499     end record;
 500     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
 501
 502     type WritebackToCrFileType is record
 503         write_cr_enable : std_ulogic;
 504         write_cr_mask : std_ulogic_vector(7 downto 0);
 505         write_cr_data : std_ulogic_vector(31 downto 0);
 506         write_xerc_enable : std_ulogic;
 507         write_xerc_data : xer_common_t;
 508     end record;
 509     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 510                                                                write_xerc_data => xerc_init,
 511                                                                write_cr_mask => (others => '0'),
 512                                                                write_cr_data => (others => '0'));
 513
 514 end common;
 515
 516 package body common is
 517     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 518     begin
 519         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 520     end;
 521     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 522        variable n : integer range 0 to 31;
 523        -- tmp variable introduced as workaround for VCS compilation
 524        -- simulation was failing with subtype constraint mismatch error
 525        -- see GitHub PR #173
 526        variable tmp : std_ulogic_vector(4 downto 0);
 527     begin
 528        case spr is
 529        when SPR_LR =>
 530            n := 0;
 531        when SPR_CTR =>
 532            n:= 1;
 533        when SPR_SRR0 =>
 534            n := 2;
 535        when SPR_SRR1 =>
 536            n := 3;
 537        when SPR_HSRR0 =>
 538            n := 4;
 539        when SPR_HSRR1 =>
 540            n := 5;
 541        when SPR_SPRG0 =>
 542            n := 6;
 543        when SPR_SPRG1 =>
 544            n := 7;
 545        when SPR_SPRG2 =>
 546            n := 8;
 547        when SPR_SPRG3 | SPR_SPRG3U =>
 548            n := 9;
 549        when SPR_HSPRG0 =>
 550            n := 10;
 551        when SPR_HSPRG1 =>
 552            n := 11;
 553        when SPR_XER =>
 554            n := 12;
 555        when SPR_TAR =>
 556            n := 13;
 557        when others =>
 558            n := 0;
 559            return "0000000";
 560        end case;
 561        tmp := std_ulogic_vector(to_unsigned(n, 5));
 562        return "01" & tmp;
 563     end;
 564
 565     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 566     begin
 567         return i(4 downto 0);
 568     end;
 569
 570     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 571     begin
 572         return "00" & i;
 573     end;
 574
 575     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 576     begin
 577         if s(5) = '1' then
 578             return s;
 579         else
 580             return gpr_to_gspr(g);
 581         end if;
 582     end;
 583
 584     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 585     begin
 586         return s(5);
 587     end;
 588
 589     function fpr_to_gspr(f: fpr_index_t) return gspr_index_t is
 590     begin
 591         return "10" & f;
 592     end;
 593 end common;