common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.utils.all;
   7 use work.decode_types.all;
   8
   9 package common is
  10     -- Processor Version Number
  11     constant PVR_MICROWATT  : std_ulogic_vector(31 downto 0) := x"00630000";
  12
  13     -- MSR bit numbers
  14     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  15     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  16     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  17     constant MSR_FP  : integer := (63 - 50);    -- Floating Point available
  18     constant MSR_FE0 : integer := (63 - 52);    -- Floating Exception mode
  19     constant MSR_SE  : integer := (63 - 53);    -- Single-step bit of TE field
  20     constant MSR_BE  : integer := (63 - 54);    -- Branch trace bit of TE field
  21     constant MSR_FE1 : integer := (63 - 55);    -- Floating Exception mode
  22     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  23     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  24     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  25     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  26
  27     -- SPR numbers
  28     subtype spr_num_t is integer range 0 to 1023;
  29
  30     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  31
  32     constant SPR_XER    : spr_num_t := 1;
  33     constant SPR_LR     : spr_num_t := 8;
  34     constant SPR_CTR    : spr_num_t := 9;
  35     constant SPR_TAR    : spr_num_t := 815;
  36     constant SPR_DSISR  : spr_num_t := 18;
  37     constant SPR_DAR    : spr_num_t := 19;
  38     constant SPR_TB     : spr_num_t := 268;
  39     constant SPR_TBU    : spr_num_t := 269;
  40     constant SPR_DEC    : spr_num_t := 22;
  41     constant SPR_SRR0   : spr_num_t := 26;
  42     constant SPR_SRR1   : spr_num_t := 27;
  43     constant SPR_CFAR   : spr_num_t := 28;
  44     constant SPR_HSRR0  : spr_num_t := 314;
  45     constant SPR_HSRR1  : spr_num_t := 315;
  46     constant SPR_SPRG0  : spr_num_t := 272;
  47     constant SPR_SPRG1  : spr_num_t := 273;
  48     constant SPR_SPRG2  : spr_num_t := 274;
  49     constant SPR_SPRG3  : spr_num_t := 275;
  50     constant SPR_SPRG3U : spr_num_t := 259;
  51     constant SPR_HSPRG0 : spr_num_t := 304;
  52     constant SPR_HSPRG1 : spr_num_t := 305;
  53     constant SPR_PID    : spr_num_t := 48;
  54     constant SPR_PRTBL  : spr_num_t := 720;
  55     constant SPR_PVR    : spr_num_t := 287;
  56
  57     -- GPR indices in the register file (GPR only)
  58     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  59
  60     -- Extended GPR index (can hold an SPR or a FPR)
  61     subtype gspr_index_t is std_ulogic_vector(6 downto 0);
  62
  63     -- FPR indices
  64     subtype fpr_index_t is std_ulogic_vector(4 downto 0);
  65
  66     -- Some SPRs are stored in the register file, they use the magic
  67     -- GPR numbers above 31.
  68     --
  69     -- The function fast_spr_num() returns the corresponding fast
  70     -- pseudo-GPR number for a given SPR number. The result MSB
  71     -- indicates if this is indeed a fast SPR. If clear, then
  72     -- the SPR is not stored in the GPR file.
  73     --
  74     -- FPRs are also stored in the register file, using GSPR
  75     -- numbers from 64 to 95.
  76     --
  77     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  78
  79     -- Indices conversion functions
  80     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  81     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  82     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  83     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  84     function fpr_to_gspr(f: fpr_index_t) return gspr_index_t;
  85
  86     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  87     -- in the CR file as a kind of CR extension (with a separate write
  88     -- control). The rest is stored as a fast SPR.
  89     type xer_common_t is record
  90         ca : std_ulogic;
  91         ca32 : std_ulogic;
  92         ov : std_ulogic;
  93         ov32 : std_ulogic;
  94         so : std_ulogic;
  95     end record;
  96     constant xerc_init : xer_common_t := (others => '0');
  97
  98     -- FPSCR bit numbers
  99     constant FPSCR_FX     : integer := 63 - 32;
 100     constant FPSCR_FEX    : integer := 63 - 33;
 101     constant FPSCR_VX     : integer := 63 - 34;
 102     constant FPSCR_OX     : integer := 63 - 35;
 103     constant FPSCR_UX     : integer := 63 - 36;
 104     constant FPSCR_ZX     : integer := 63 - 37;
 105     constant FPSCR_XX     : integer := 63 - 38;
 106     constant FPSCR_VXSNAN : integer := 63 - 39;
 107     constant FPSCR_VXISI  : integer := 63 - 40;
 108     constant FPSCR_VXIDI  : integer := 63 - 41;
 109     constant FPSCR_VXZDZ  : integer := 63 - 42;
 110     constant FPSCR_VXIMZ  : integer := 63 - 43;
 111     constant FPSCR_VXVC   : integer := 63 - 44;
 112     constant FPSCR_FR     : integer := 63 - 45;
 113     constant FPSCR_FI     : integer := 63 - 46;
 114     constant FPSCR_C      : integer := 63 - 47;
 115     constant FPSCR_FL     : integer := 63 - 48;
 116     constant FPSCR_FG     : integer := 63 - 49;
 117     constant FPSCR_FE     : integer := 63 - 50;
 118     constant FPSCR_FU     : integer := 63 - 51;
 119     constant FPSCR_VXSOFT : integer := 63 - 53;
 120     constant FPSCR_VXSQRT : integer := 63 - 54;
 121     constant FPSCR_VXCVI  : integer := 63 - 55;
 122     constant FPSCR_VE     : integer := 63 - 56;
 123     constant FPSCR_OE     : integer := 63 - 57;
 124     constant FPSCR_UE     : integer := 63 - 58;
 125     constant FPSCR_ZE     : integer := 63 - 59;
 126     constant FPSCR_XE     : integer := 63 - 60;
 127     constant FPSCR_NI     : integer := 63 - 61;
 128     constant FPSCR_RN     : integer := 63 - 63;
 129
 130     -- Used for tracking instruction completion and pending register writes
 131     constant TAG_COUNT : positive := 4;
 132     constant TAG_NUMBER_BITS : natural := log2(TAG_COUNT);
 133     subtype tag_number_t is integer range 0 to TAG_COUNT - 1;
 134     subtype tag_index_t is unsigned(TAG_NUMBER_BITS - 1 downto 0);
 135     type instr_tag_t is record
 136         tag   : tag_number_t;
 137         valid : std_ulogic;
 138     end record;
 139     constant instr_tag_init : instr_tag_t := (tag => 0, valid => '0');
 140     function tag_match(tag1 : instr_tag_t; tag2 : instr_tag_t) return boolean;
 141
 142     subtype intr_vector_t is integer range 0 to 16#fff#;
 143
 144     -- For now, fixed 16 sources, make this either a parametric
 145     -- package of some sort or an unconstrainted array.
 146     type ics_to_icp_t is record
 147         -- Level interrupts only, ICS just keeps prsenting the
 148         -- highest priority interrupt. Once handling edge, something
 149         -- smarter involving handshake & reject support will be needed
 150         src : std_ulogic_vector(3 downto 0);
 151         pri : std_ulogic_vector(7 downto 0);
 152     end record;
 153
 154     -- This needs to die...
 155     type ctrl_t is record
 156         tb: std_ulogic_vector(63 downto 0);
 157         dec: std_ulogic_vector(63 downto 0);
 158         msr: std_ulogic_vector(63 downto 0);
 159         cfar: std_ulogic_vector(63 downto 0);
 160     end record;
 161
 162     type Fetch1ToIcacheType is record
 163         req: std_ulogic;
 164         virt_mode : std_ulogic;
 165         priv_mode : std_ulogic;
 166         big_endian : std_ulogic;
 167         stop_mark: std_ulogic;
 168         sequential: std_ulogic;
 169         predicted : std_ulogic;
 170         nia: std_ulogic_vector(63 downto 0);
 171     end record;
 172
 173     type IcacheToDecode1Type is record
 174         valid: std_ulogic;
 175         stop_mark: std_ulogic;
 176         fetch_failed: std_ulogic;
 177         nia: std_ulogic_vector(63 downto 0);
 178         insn: std_ulogic_vector(31 downto 0);
 179         big_endian: std_ulogic;
 180         next_predicted: std_ulogic;
 181     end record;
 182
 183     type Decode1ToDecode2Type is record
 184         valid: std_ulogic;
 185         stop_mark : std_ulogic;
 186         nia: std_ulogic_vector(63 downto 0);
 187         insn: std_ulogic_vector(31 downto 0);
 188         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 189         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 190         ispro: gspr_index_t; -- (G)SPR written with LR or CTR
 191         decode: decode_rom_t;
 192         br_pred: std_ulogic; -- Branch was predicted to be taken
 193         big_endian: std_ulogic;
 194     end record;
 195     constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
 196         (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
 197          ispr1 => (others => '0'), ispr2 => (others => '0'), ispro => (others => '0'),
 198          decode => decode_rom_init, br_pred => '0', big_endian => '0');
 199
 200     type Decode1ToFetch1Type is record
 201         redirect     : std_ulogic;
 202         redirect_nia : std_ulogic_vector(63 downto 0);
 203     end record;
 204
 205     type bypass_data_t is record
 206         tag  : instr_tag_t;
 207         data : std_ulogic_vector(63 downto 0);
 208     end record;
 209     constant bypass_data_init : bypass_data_t := (tag => instr_tag_init, data => (others => '0'));
 210
 211     type cr_bypass_data_t is record
 212         tag  : instr_tag_t;
 213         data : std_ulogic_vector(31 downto 0);
 214     end record;
 215     constant cr_bypass_data_init : cr_bypass_data_t := (tag => instr_tag_init, data => (others => '0'));
 216
 217     type Decode2ToExecute1Type is record
 218         valid: std_ulogic;
 219         unit : unit_t;
 220         fac : facility_t;
 221         insn_type: insn_type_t;
 222         nia: std_ulogic_vector(63 downto 0);
 223         instr_tag : instr_tag_t;
 224         write_reg: gspr_index_t;
 225         write_reg_enable: std_ulogic;
 226         read_reg1: gspr_index_t;
 227         read_reg2: gspr_index_t;
 228         read_data1: std_ulogic_vector(63 downto 0);
 229         read_data2: std_ulogic_vector(63 downto 0);
 230         read_data3: std_ulogic_vector(63 downto 0);
 231         cr: std_ulogic_vector(31 downto 0);
 232         xerc: xer_common_t;
 233         lr: std_ulogic;
 234         br_abs: std_ulogic;
 235         rc: std_ulogic;
 236         oe: std_ulogic;
 237         invert_a: std_ulogic;
 238         addm1 : std_ulogic;
 239         invert_out: std_ulogic;
 240         input_carry: carry_in_t;
 241         output_carry: std_ulogic;
 242         input_cr: std_ulogic;
 243         output_cr: std_ulogic;
 244         output_xer: std_ulogic;
 245         is_32bit: std_ulogic;
 246         is_signed: std_ulogic;
 247         insn: std_ulogic_vector(31 downto 0);
 248         data_len: std_ulogic_vector(3 downto 0);
 249         byte_reverse : std_ulogic;
 250         sign_extend : std_ulogic;                       -- do we need to sign extend?
 251         update : std_ulogic;                            -- is this an update instruction?
 252         reserve : std_ulogic;                           -- set for larx/stcx
 253         br_pred : std_ulogic;
 254         result_sel : std_ulogic_vector(2 downto 0);     -- select source of result
 255         sub_select : std_ulogic_vector(2 downto 0);     -- sub-result selection
 256         repeat : std_ulogic;                            -- set if instruction is cracked into two ops
 257         second : std_ulogic;                            -- set if this is the second op
 258     end record;
 259     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 260         (valid => '0', unit => NONE, fac => NONE, insn_type => OP_ILLEGAL, instr_tag => instr_tag_init,
 261          write_reg_enable => '0',
 262          lr => '0', br_abs => '0', rc => '0', oe => '0', invert_a => '0', addm1 => '0',
 263          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0',
 264          output_cr => '0', output_xer => '0',
 265          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
 266          byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'),
 267          read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'),
 268          cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'),
 269          result_sel => "000", sub_select => "000",
 270          repeat => '0', second => '0', others => (others => '0'));
 271
 272     type MultiplyInputType is record
 273         valid: std_ulogic;
 274         data1: std_ulogic_vector(63 downto 0);
 275         data2: std_ulogic_vector(63 downto 0);
 276         addend: std_ulogic_vector(127 downto 0);
 277         is_32bit: std_ulogic;
 278         not_result: std_ulogic;
 279     end record;
 280     constant MultiplyInputInit : MultiplyInputType := (valid => '0',
 281                                                        is_32bit => '0', not_result => '0',
 282                                                        others => (others => '0'));
 283
 284     type MultiplyOutputType is record
 285         valid: std_ulogic;
 286         result: std_ulogic_vector(127 downto 0);
 287         overflow : std_ulogic;
 288     end record;
 289     constant MultiplyOutputInit : MultiplyOutputType := (valid => '0', overflow => '0',
 290                                                          others => (others => '0'));
 291
 292     type Execute1ToDividerType is record
 293         valid: std_ulogic;
 294         dividend: std_ulogic_vector(63 downto 0);
 295         divisor: std_ulogic_vector(63 downto 0);
 296         is_signed: std_ulogic;
 297         is_32bit: std_ulogic;
 298         is_extended: std_ulogic;
 299         is_modulus: std_ulogic;
 300         neg_result: std_ulogic;
 301     end record;
 302     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 303                                                               is_extended => '0', is_modulus => '0',
 304                                                               neg_result => '0', others => (others => '0'));
 305
 306     type Decode2ToRegisterFileType is record
 307         read1_enable : std_ulogic;
 308         read1_reg : gspr_index_t;
 309         read2_enable : std_ulogic;
 310         read2_reg : gspr_index_t;
 311         read3_enable : std_ulogic;
 312         read3_reg : gspr_index_t;
 313     end record;
 314
 315     type RegisterFileToDecode2Type is record
 316         read1_data : std_ulogic_vector(63 downto 0);
 317         read2_data : std_ulogic_vector(63 downto 0);
 318         read3_data : std_ulogic_vector(63 downto 0);
 319     end record;
 320
 321     type Decode2ToCrFileType is record
 322         read : std_ulogic;
 323     end record;
 324
 325     type CrFileToDecode2Type is record
 326         read_cr_data   : std_ulogic_vector(31 downto 0);
 327         read_xerc_data : xer_common_t;
 328     end record;
 329
 330     type Execute1ToLoadstore1Type is record
 331         valid : std_ulogic;
 332         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 333         nia : std_ulogic_vector(63 downto 0);
 334         insn : std_ulogic_vector(31 downto 0);
 335         instr_tag : instr_tag_t;
 336         addr1 : std_ulogic_vector(63 downto 0);
 337         addr2 : std_ulogic_vector(63 downto 0);
 338         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 339         write_reg : gspr_index_t;
 340         length : std_ulogic_vector(3 downto 0);
 341         ci : std_ulogic;                                -- cache-inhibited load/store
 342         byte_reverse : std_ulogic;
 343         sign_extend : std_ulogic;                       -- do we need to sign extend?
 344         update : std_ulogic;                            -- is this an update instruction?
 345         xerc : xer_common_t;
 346         reserve : std_ulogic;                           -- set for larx/stcx.
 347         rc : std_ulogic;                                -- set for stcx.
 348         virt_mode : std_ulogic;                         -- do translation through TLB
 349         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 350         mode_32bit : std_ulogic;                        -- trim addresses to 32 bits
 351         is_32bit : std_ulogic;
 352         repeat : std_ulogic;
 353         second : std_ulogic;
 354         msr : std_ulogic_vector(63 downto 0);
 355     end record;
 356     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type :=
 357         (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 358          sign_extend => '0', update => '0', xerc => xerc_init,
 359          reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 360          nia => (others => '0'), insn => (others => '0'),
 361          instr_tag => instr_tag_init,
 362          addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'),
 363          write_reg => (others => '0'),
 364          length => (others => '0'),
 365          mode_32bit => '0', is_32bit => '0',
 366          repeat => '0', second => '0',
 367          msr => (others => '0'));
 368
 369     type Loadstore1ToExecute1Type is record
 370         busy : std_ulogic;
 371     end record;
 372
 373     type Loadstore1ToDcacheType is record
 374         valid : std_ulogic;
 375         hold : std_ulogic;
 376         load : std_ulogic;                              -- is this a load
 377         dcbz : std_ulogic;
 378         nc : std_ulogic;
 379         reserve : std_ulogic;
 380         atomic : std_ulogic;                            -- part of a multi-transfer atomic op
 381         atomic_last : std_ulogic;
 382         virt_mode : std_ulogic;
 383         priv_mode : std_ulogic;
 384         addr : std_ulogic_vector(63 downto 0);
 385         data : std_ulogic_vector(63 downto 0);          -- valid the cycle after .valid = 1
 386         byte_sel : std_ulogic_vector(7 downto 0);
 387     end record;
 388
 389     type DcacheToLoadstore1Type is record
 390         valid : std_ulogic;
 391         data : std_ulogic_vector(63 downto 0);
 392         store_done : std_ulogic;
 393         error : std_ulogic;
 394         cache_paradox : std_ulogic;
 395     end record;
 396
 397     type Loadstore1ToMmuType is record
 398         valid : std_ulogic;
 399         tlbie : std_ulogic;
 400         slbia : std_ulogic;
 401         mtspr : std_ulogic;
 402         iside : std_ulogic;
 403         load  : std_ulogic;
 404         priv  : std_ulogic;
 405         sprn  : std_ulogic_vector(9 downto 0);
 406         addr  : std_ulogic_vector(63 downto 0);
 407         rs    : std_ulogic_vector(63 downto 0);
 408     end record;
 409
 410     type MmuToLoadstore1Type is record
 411         done       : std_ulogic;
 412         err        : std_ulogic;
 413         invalid    : std_ulogic;
 414         badtree    : std_ulogic;
 415         segerr     : std_ulogic;
 416         perm_error : std_ulogic;
 417         rc_error   : std_ulogic;
 418         sprval     : std_ulogic_vector(63 downto 0);
 419     end record;
 420
 421     type MmuToDcacheType is record
 422         valid : std_ulogic;
 423         tlbie : std_ulogic;
 424         doall : std_ulogic;
 425         tlbld : std_ulogic;
 426         addr  : std_ulogic_vector(63 downto 0);
 427         pte   : std_ulogic_vector(63 downto 0);
 428     end record;
 429
 430     type DcacheToMmuType is record
 431         stall : std_ulogic;
 432         done  : std_ulogic;
 433         err   : std_ulogic;
 434         data  : std_ulogic_vector(63 downto 0);
 435     end record;
 436
 437     type MmuToIcacheType is record
 438         tlbld : std_ulogic;
 439         tlbie : std_ulogic;
 440         doall : std_ulogic;
 441         addr  : std_ulogic_vector(63 downto 0);
 442         pte   : std_ulogic_vector(63 downto 0);
 443     end record;
 444
 445     type Loadstore1ToWritebackType is record
 446         valid : std_ulogic;
 447         instr_tag : instr_tag_t;
 448         write_enable: std_ulogic;
 449         write_reg : gspr_index_t;
 450         write_data : std_ulogic_vector(63 downto 0);
 451         xerc : xer_common_t;
 452         rc : std_ulogic;
 453         store_done : std_ulogic;
 454         interrupt : std_ulogic;
 455         intr_vec : intr_vector_t;
 456         srr0: std_ulogic_vector(63 downto 0);
 457         srr1: std_ulogic_vector(15 downto 0);
 458     end record;
 459     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType :=
 460         (valid => '0', instr_tag => instr_tag_init, write_enable => '0',
 461          write_reg => (others => '0'), write_data => (others => '0'),
 462          xerc => xerc_init, rc => '0', store_done => '0',
 463          interrupt => '0', intr_vec => 0,
 464          srr0 => (others => '0'), srr1 => (others => '0'));
 465
 466     type Execute1ToWritebackType is record
 467         valid: std_ulogic;
 468         instr_tag : instr_tag_t;
 469         rc : std_ulogic;
 470         mode_32bit : std_ulogic;
 471         write_enable : std_ulogic;
 472         write_reg: gspr_index_t;
 473         write_data: std_ulogic_vector(63 downto 0);
 474         write_cr_enable : std_ulogic;
 475         write_cr_mask : std_ulogic_vector(7 downto 0);
 476         write_cr_data : std_ulogic_vector(31 downto 0);
 477         write_xerc_enable : std_ulogic;
 478         xerc : xer_common_t;
 479         interrupt : std_ulogic;
 480         intr_vec : intr_vector_t;
 481         redirect: std_ulogic;
 482         redir_mode: std_ulogic_vector(3 downto 0);
 483         last_nia: std_ulogic_vector(63 downto 0);
 484         br_offset: std_ulogic_vector(63 downto 0);
 485         br_last: std_ulogic;
 486         br_taken: std_ulogic;
 487         abs_br: std_ulogic;
 488         srr1: std_ulogic_vector(15 downto 0);
 489         msr: std_ulogic_vector(63 downto 0);
 490     end record;
 491     constant Execute1ToWritebackInit : Execute1ToWritebackType :=
 492         (valid => '0', instr_tag => instr_tag_init, rc => '0', mode_32bit => '0',
 493          write_enable => '0', write_cr_enable => '0',
 494          write_xerc_enable => '0', xerc => xerc_init,
 495          write_data => (others => '0'), write_cr_mask => (others => '0'),
 496          write_cr_data => (others => '0'), write_reg => (others => '0'),
 497          interrupt => '0', intr_vec => 0, redirect => '0', redir_mode => "0000",
 498          last_nia => (others => '0'), br_offset => (others => '0'),
 499          br_last => '0', br_taken => '0', abs_br => '0',
 500          srr1 => (others => '0'), msr => (others => '0'));
 501
 502     type Execute1ToFPUType is record
 503         valid   : std_ulogic;
 504         op      : insn_type_t;
 505         nia     : std_ulogic_vector(63 downto 0);
 506         itag    : instr_tag_t;
 507         insn    : std_ulogic_vector(31 downto 0);
 508         single  : std_ulogic;
 509         fe_mode : std_ulogic_vector(1 downto 0);
 510         fra     : std_ulogic_vector(63 downto 0);
 511         frb     : std_ulogic_vector(63 downto 0);
 512         frc     : std_ulogic_vector(63 downto 0);
 513         frt     : gspr_index_t;
 514         rc      : std_ulogic;
 515         out_cr  : std_ulogic;
 516     end record;
 517     constant Execute1ToFPUInit : Execute1ToFPUType := (valid => '0', op => OP_ILLEGAL, nia => (others => '0'),
 518                                                        itag => instr_tag_init,
 519                                                        insn  => (others => '0'), fe_mode => "00", rc => '0',
 520                                                        fra => (others => '0'), frb => (others => '0'),
 521                                                        frc => (others => '0'), frt => (others => '0'),
 522                                                        single => '0', out_cr => '0');
 523
 524     type FPUToExecute1Type is record
 525         busy      : std_ulogic;
 526         exception : std_ulogic;
 527     end record;
 528     constant FPUToExecute1Init : FPUToExecute1Type := (others => '0');
 529
 530     type FPUToWritebackType is record
 531         valid           : std_ulogic;
 532         interrupt       : std_ulogic;
 533         instr_tag       : instr_tag_t;
 534         write_enable    : std_ulogic;
 535         write_reg       : gspr_index_t;
 536         write_data      : std_ulogic_vector(63 downto 0);
 537         write_cr_enable : std_ulogic;
 538         write_cr_mask   : std_ulogic_vector(7 downto 0);
 539         write_cr_data   : std_ulogic_vector(31 downto 0);
 540         intr_vec        : intr_vector_t;
 541         srr0            : std_ulogic_vector(63 downto 0);
 542         srr1            : std_ulogic_vector(15 downto 0);
 543     end record;
 544     constant FPUToWritebackInit : FPUToWritebackType :=
 545         (valid => '0', interrupt => '0', instr_tag => instr_tag_init,
 546          write_enable => '0', write_reg => (others => '0'),
 547          write_cr_enable => '0', write_cr_mask => (others => '0'),
 548          write_cr_data => (others => '0'),
 549          intr_vec => 0, srr1 => (others => '0'),
 550          others => (others => '0'));
 551
 552     type DividerToExecute1Type is record
 553         valid: std_ulogic;
 554         write_reg_data: std_ulogic_vector(63 downto 0);
 555         overflow : std_ulogic;
 556     end record;
 557     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 558                                                                others => (others => '0'));
 559
 560     type WritebackToFetch1Type is record
 561         redirect: std_ulogic;
 562         virt_mode: std_ulogic;
 563         priv_mode: std_ulogic;
 564         big_endian: std_ulogic;
 565         mode_32bit: std_ulogic;
 566         redirect_nia: std_ulogic_vector(63 downto 0);
 567         br_nia : std_ulogic_vector(63 downto 0);
 568         br_last : std_ulogic;
 569         br_taken : std_ulogic;
 570     end record;
 571     constant WritebackToFetch1Init : WritebackToFetch1Type :=
 572         (redirect => '0', virt_mode => '0', priv_mode => '0', big_endian => '0',
 573          mode_32bit => '0', redirect_nia => (others => '0'),
 574          br_last => '0', br_taken => '0', br_nia => (others => '0'));
 575
 576     type WritebackToRegisterFileType is record
 577         write_reg : gspr_index_t;
 578         write_data : std_ulogic_vector(63 downto 0);
 579         write_enable : std_ulogic;
 580     end record;
 581     constant WritebackToRegisterFileInit : WritebackToRegisterFileType :=
 582         (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
 583
 584     type WritebackToCrFileType is record
 585         write_cr_enable : std_ulogic;
 586         write_cr_mask : std_ulogic_vector(7 downto 0);
 587         write_cr_data : std_ulogic_vector(31 downto 0);
 588         write_xerc_enable : std_ulogic;
 589         write_xerc_data : xer_common_t;
 590     end record;
 591     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 592                                                                write_xerc_data => xerc_init,
 593                                                                write_cr_mask => (others => '0'),
 594                                                                write_cr_data => (others => '0'));
 595
 596 end common;
 597
 598 package body common is
 599     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 600     begin
 601         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 602     end;
 603     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 604        variable n : integer range 0 to 31;
 605        -- tmp variable introduced as workaround for VCS compilation
 606        -- simulation was failing with subtype constraint mismatch error
 607        -- see GitHub PR #173
 608        variable tmp : std_ulogic_vector(4 downto 0);
 609     begin
 610        case spr is
 611        when SPR_LR =>
 612            n := 0;              -- N.B. decode2 relies on this specific value
 613        when SPR_CTR =>
 614            n := 1;              -- N.B. decode2 relies on this specific value
 615        when SPR_SRR0 =>
 616            n := 2;
 617        when SPR_SRR1 =>
 618            n := 3;
 619        when SPR_HSRR0 =>
 620            n := 4;
 621        when SPR_HSRR1 =>
 622            n := 5;
 623        when SPR_SPRG0 =>
 624            n := 6;
 625        when SPR_SPRG1 =>
 626            n := 7;
 627        when SPR_SPRG2 =>
 628            n := 8;
 629        when SPR_SPRG3 | SPR_SPRG3U =>
 630            n := 9;
 631        when SPR_HSPRG0 =>
 632            n := 10;
 633        when SPR_HSPRG1 =>
 634            n := 11;
 635        when SPR_XER =>
 636            n := 12;
 637        when SPR_TAR =>
 638            n := 13;
 639        when others =>
 640            n := 0;
 641            return "0000000";
 642        end case;
 643        tmp := std_ulogic_vector(to_unsigned(n, 5));
 644        return "01" & tmp;
 645     end;
 646
 647     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 648     begin
 649         return i(4 downto 0);
 650     end;
 651
 652     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 653     begin
 654         return "00" & i;
 655     end;
 656
 657     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 658     begin
 659         if s(5) = '1' then
 660             return s;
 661         else
 662             return gpr_to_gspr(g);
 663         end if;
 664     end;
 665
 666     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 667     begin
 668         return s(5);
 669     end;
 670
 671     function fpr_to_gspr(f: fpr_index_t) return gspr_index_t is
 672     begin
 673         return "10" & f;
 674     end;
 675
 676     function tag_match(tag1 : instr_tag_t; tag2 : instr_tag_t) return boolean is
 677     begin
 678         return tag1.valid = '1' and tag2.valid = '1' and tag1.tag = tag2.tag;
 679     end;
 680 end common;