common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9     -- Processor Version Number
  10     constant PVR_MICROWATT  : std_ulogic_vector(31 downto 0) := x"00630000";
  11
  12     -- MSR bit numbers
  13     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  14     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  15     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  16     constant MSR_FP  : integer := (63 - 50);    -- Floating Point available
  17     constant MSR_FE0 : integer := (63 - 52);    -- Floating Exception mode
  18     constant MSR_SE  : integer := (63 - 53);    -- Single-step bit of TE field
  19     constant MSR_BE  : integer := (63 - 54);    -- Branch trace bit of TE field
  20     constant MSR_FE1 : integer := (63 - 55);    -- Floating Exception mode
  21     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  22     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  23     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  24     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  25
  26     -- SPR numbers
  27     subtype spr_num_t is integer range 0 to 1023;
  28
  29     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  30
  31     constant SPR_XER    : spr_num_t := 1;
  32     constant SPR_LR     : spr_num_t := 8;
  33     constant SPR_CTR    : spr_num_t := 9;
  34     constant SPR_TAR    : spr_num_t := 815;
  35     constant SPR_DSISR  : spr_num_t := 18;
  36     constant SPR_DAR    : spr_num_t := 19;
  37     constant SPR_TB     : spr_num_t := 268;
  38     constant SPR_TBU    : spr_num_t := 269;
  39     constant SPR_DEC    : spr_num_t := 22;
  40     constant SPR_SRR0   : spr_num_t := 26;
  41     constant SPR_SRR1   : spr_num_t := 27;
  42     constant SPR_CFAR   : spr_num_t := 28;
  43     constant SPR_HSRR0  : spr_num_t := 314;
  44     constant SPR_HSRR1  : spr_num_t := 315;
  45     constant SPR_SPRG0  : spr_num_t := 272;
  46     constant SPR_SPRG1  : spr_num_t := 273;
  47     constant SPR_SPRG2  : spr_num_t := 274;
  48     constant SPR_SPRG3  : spr_num_t := 275;
  49     constant SPR_SPRG3U : spr_num_t := 259;
  50     constant SPR_HSPRG0 : spr_num_t := 304;
  51     constant SPR_HSPRG1 : spr_num_t := 305;
  52     constant SPR_PID    : spr_num_t := 48;
  53     constant SPR_PRTBL  : spr_num_t := 720;
  54     constant SPR_PVR    : spr_num_t := 287;
  55
  56     -- GPR indices in the register file (GPR only)
  57     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  58
  59     -- Extended GPR index (can hold an SPR or a FPR)
  60     subtype gspr_index_t is std_ulogic_vector(6 downto 0);
  61
  62     -- FPR indices
  63     subtype fpr_index_t is std_ulogic_vector(4 downto 0);
  64
  65     -- Some SPRs are stored in the register file, they use the magic
  66     -- GPR numbers above 31.
  67     --
  68     -- The function fast_spr_num() returns the corresponding fast
  69     -- pseudo-GPR number for a given SPR number. The result MSB
  70     -- indicates if this is indeed a fast SPR. If clear, then
  71     -- the SPR is not stored in the GPR file.
  72     --
  73     -- FPRs are also stored in the register file, using GSPR
  74     -- numbers from 64 to 95.
  75     --
  76     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  77
  78     -- Indices conversion functions
  79     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  80     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  81     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  82     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  83     function fpr_to_gspr(f: fpr_index_t) return gspr_index_t;
  84
  85     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  86     -- in the CR file as a kind of CR extension (with a separate write
  87     -- control). The rest is stored as a fast SPR.
  88     type xer_common_t is record
  89         ca : std_ulogic;
  90         ca32 : std_ulogic;
  91         ov : std_ulogic;
  92         ov32 : std_ulogic;
  93         so : std_ulogic;
  94     end record;
  95     constant xerc_init : xer_common_t := (others => '0');
  96
  97     -- FPSCR bit numbers
  98     constant FPSCR_FX     : integer := 63 - 32;
  99     constant FPSCR_FEX    : integer := 63 - 33;
 100     constant FPSCR_VX     : integer := 63 - 34;
 101     constant FPSCR_OX     : integer := 63 - 35;
 102     constant FPSCR_UX     : integer := 63 - 36;
 103     constant FPSCR_ZX     : integer := 63 - 37;
 104     constant FPSCR_XX     : integer := 63 - 38;
 105     constant FPSCR_VXSNAN : integer := 63 - 39;
 106     constant FPSCR_VXISI  : integer := 63 - 40;
 107     constant FPSCR_VXIDI  : integer := 63 - 41;
 108     constant FPSCR_VXZDZ  : integer := 63 - 42;
 109     constant FPSCR_VXIMZ  : integer := 63 - 43;
 110     constant FPSCR_VXVC   : integer := 63 - 44;
 111     constant FPSCR_FR     : integer := 63 - 45;
 112     constant FPSCR_FI     : integer := 63 - 46;
 113     constant FPSCR_C      : integer := 63 - 47;
 114     constant FPSCR_FL     : integer := 63 - 48;
 115     constant FPSCR_FG     : integer := 63 - 49;
 116     constant FPSCR_FE     : integer := 63 - 50;
 117     constant FPSCR_FU     : integer := 63 - 51;
 118     constant FPSCR_VXSOFT : integer := 63 - 53;
 119     constant FPSCR_VXSQRT : integer := 63 - 54;
 120     constant FPSCR_VXCVI  : integer := 63 - 55;
 121     constant FPSCR_VE     : integer := 63 - 56;
 122     constant FPSCR_OE     : integer := 63 - 57;
 123     constant FPSCR_UE     : integer := 63 - 58;
 124     constant FPSCR_ZE     : integer := 63 - 59;
 125     constant FPSCR_XE     : integer := 63 - 60;
 126     constant FPSCR_NI     : integer := 63 - 61;
 127     constant FPSCR_RN     : integer := 63 - 63;
 128
 129     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
 130
 131     -- For now, fixed 16 sources, make this either a parametric
 132     -- package of some sort or an unconstrainted array.
 133     type ics_to_icp_t is record
 134         -- Level interrupts only, ICS just keeps prsenting the
 135         -- highest priority interrupt. Once handling edge, something
 136         -- smarter involving handshake & reject support will be needed
 137         src : std_ulogic_vector(3 downto 0);
 138         pri : std_ulogic_vector(7 downto 0);
 139     end record;
 140
 141     -- This needs to die...
 142     type ctrl_t is record
 143         tb: std_ulogic_vector(63 downto 0);
 144         dec: std_ulogic_vector(63 downto 0);
 145         msr: std_ulogic_vector(63 downto 0);
 146         cfar: std_ulogic_vector(63 downto 0);
 147         irq_state : irq_state_t;
 148         srr1: std_ulogic_vector(63 downto 0);
 149     end record;
 150
 151     type Fetch1ToIcacheType is record
 152         req: std_ulogic;
 153         virt_mode : std_ulogic;
 154         priv_mode : std_ulogic;
 155         big_endian : std_ulogic;
 156         stop_mark: std_ulogic;
 157         sequential: std_ulogic;
 158         predicted : std_ulogic;
 159         nia: std_ulogic_vector(63 downto 0);
 160     end record;
 161
 162     type IcacheToDecode1Type is record
 163         valid: std_ulogic;
 164         stop_mark: std_ulogic;
 165         fetch_failed: std_ulogic;
 166         nia: std_ulogic_vector(63 downto 0);
 167         insn: std_ulogic_vector(31 downto 0);
 168         big_endian: std_ulogic;
 169         next_predicted: std_ulogic;
 170     end record;
 171
 172     type Decode1ToDecode2Type is record
 173         valid: std_ulogic;
 174         stop_mark : std_ulogic;
 175         nia: std_ulogic_vector(63 downto 0);
 176         insn: std_ulogic_vector(31 downto 0);
 177         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 178         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 179         ispro: gspr_index_t; -- (G)SPR written with LR or CTR
 180         decode: decode_rom_t;
 181         br_pred: std_ulogic; -- Branch was predicted to be taken
 182         big_endian: std_ulogic;
 183     end record;
 184     constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
 185         (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
 186          ispr1 => (others => '0'), ispr2 => (others => '0'), ispro => (others => '0'),
 187          decode => decode_rom_init, br_pred => '0', big_endian => '0');
 188
 189     type Decode1ToFetch1Type is record
 190         redirect     : std_ulogic;
 191         redirect_nia : std_ulogic_vector(63 downto 0);
 192     end record;
 193
 194     type Decode2ToExecute1Type is record
 195         valid: std_ulogic;
 196         unit : unit_t;
 197         fac : facility_t;
 198         insn_type: insn_type_t;
 199         nia: std_ulogic_vector(63 downto 0);
 200         write_reg: gspr_index_t;
 201         write_reg_enable: std_ulogic;
 202         read_reg1: gspr_index_t;
 203         read_reg2: gspr_index_t;
 204         read_data1: std_ulogic_vector(63 downto 0);
 205         read_data2: std_ulogic_vector(63 downto 0);
 206         read_data3: std_ulogic_vector(63 downto 0);
 207         bypass_data1: std_ulogic;
 208         bypass_data2: std_ulogic;
 209         bypass_data3: std_ulogic;
 210         cr: std_ulogic_vector(31 downto 0);
 211         bypass_cr : std_ulogic;
 212         xerc: xer_common_t;
 213         lr: std_ulogic;
 214         br_abs: std_ulogic;
 215         rc: std_ulogic;
 216         oe: std_ulogic;
 217         invert_a: std_ulogic;
 218         addm1 : std_ulogic;
 219         invert_out: std_ulogic;
 220         input_carry: carry_in_t;
 221         output_carry: std_ulogic;
 222         input_cr: std_ulogic;
 223         output_cr: std_ulogic;
 224         is_32bit: std_ulogic;
 225         is_signed: std_ulogic;
 226         insn: std_ulogic_vector(31 downto 0);
 227         data_len: std_ulogic_vector(3 downto 0);
 228         byte_reverse : std_ulogic;
 229         sign_extend : std_ulogic;                       -- do we need to sign extend?
 230         update : std_ulogic;                            -- is this an update instruction?
 231         reserve : std_ulogic;                           -- set for larx/stcx
 232         br_pred : std_ulogic;
 233         result_sel : std_ulogic_vector(2 downto 0);     -- select source of result
 234         sub_select : std_ulogic_vector(2 downto 0);     -- sub-result selection
 235         repeat : std_ulogic;                            -- set if instruction is cracked into two ops
 236         second : std_ulogic;                            -- set if this is the second op
 237     end record;
 238     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 239         (valid => '0', unit => NONE, fac => NONE, insn_type => OP_ILLEGAL,
 240          write_reg_enable => '0', bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 241          bypass_cr => '0', lr => '0', br_abs => '0', rc => '0', oe => '0', invert_a => '0', addm1 => '0',
 242          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 243          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
 244          byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'),
 245          read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'),
 246          cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'),
 247          result_sel => "000", sub_select => "000",
 248          repeat => '0', second => '0', others => (others => '0'));
 249
 250     type MultiplyInputType is record
 251         valid: std_ulogic;
 252         data1: std_ulogic_vector(63 downto 0);
 253         data2: std_ulogic_vector(63 downto 0);
 254         addend: std_ulogic_vector(127 downto 0);
 255         is_32bit: std_ulogic;
 256         not_result: std_ulogic;
 257     end record;
 258     constant MultiplyInputInit : MultiplyInputType := (valid => '0',
 259                                                        is_32bit => '0', not_result => '0',
 260                                                        others => (others => '0'));
 261
 262     type MultiplyOutputType is record
 263         valid: std_ulogic;
 264         result: std_ulogic_vector(127 downto 0);
 265         overflow : std_ulogic;
 266     end record;
 267     constant MultiplyOutputInit : MultiplyOutputType := (valid => '0', overflow => '0',
 268                                                          others => (others => '0'));
 269
 270     type Execute1ToDividerType is record
 271         valid: std_ulogic;
 272         dividend: std_ulogic_vector(63 downto 0);
 273         divisor: std_ulogic_vector(63 downto 0);
 274         is_signed: std_ulogic;
 275         is_32bit: std_ulogic;
 276         is_extended: std_ulogic;
 277         is_modulus: std_ulogic;
 278         neg_result: std_ulogic;
 279     end record;
 280     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 281                                                               is_extended => '0', is_modulus => '0',
 282                                                               neg_result => '0', others => (others => '0'));
 283
 284     type Decode2ToRegisterFileType is record
 285         read1_enable : std_ulogic;
 286         read1_reg : gspr_index_t;
 287         read2_enable : std_ulogic;
 288         read2_reg : gspr_index_t;
 289         read3_enable : std_ulogic;
 290         read3_reg : gspr_index_t;
 291     end record;
 292
 293     type RegisterFileToDecode2Type is record
 294         read1_data : std_ulogic_vector(63 downto 0);
 295         read2_data : std_ulogic_vector(63 downto 0);
 296         read3_data : std_ulogic_vector(63 downto 0);
 297     end record;
 298
 299     type Decode2ToCrFileType is record
 300         read : std_ulogic;
 301     end record;
 302
 303     type CrFileToDecode2Type is record
 304         read_cr_data   : std_ulogic_vector(31 downto 0);
 305         read_xerc_data : xer_common_t;
 306     end record;
 307
 308     type Execute1ToFetch1Type is record
 309         redirect: std_ulogic;
 310         virt_mode: std_ulogic;
 311         priv_mode: std_ulogic;
 312         big_endian: std_ulogic;
 313         mode_32bit: std_ulogic;
 314         redirect_nia: std_ulogic_vector(63 downto 0);
 315         br_nia : std_ulogic_vector(63 downto 0);
 316         br_last : std_ulogic;
 317         br_taken : std_ulogic;
 318     end record;
 319     constant Execute1ToFetch1Init : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
 320                                                              priv_mode => '0', big_endian => '0',
 321                                                              mode_32bit => '0', br_taken => '0',
 322                                                              br_last => '0', others => (others => '0'));
 323
 324     type Execute1ToLoadstore1Type is record
 325         valid : std_ulogic;
 326         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 327         nia : std_ulogic_vector(63 downto 0);
 328         insn : std_ulogic_vector(31 downto 0);
 329         addr1 : std_ulogic_vector(63 downto 0);
 330         addr2 : std_ulogic_vector(63 downto 0);
 331         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 332         write_reg : gspr_index_t;
 333         length : std_ulogic_vector(3 downto 0);
 334         ci : std_ulogic;                                -- cache-inhibited load/store
 335         byte_reverse : std_ulogic;
 336         sign_extend : std_ulogic;                       -- do we need to sign extend?
 337         update : std_ulogic;                            -- is this an update instruction?
 338         xerc : xer_common_t;
 339         reserve : std_ulogic;                           -- set for larx/stcx.
 340         rc : std_ulogic;                                -- set for stcx.
 341         virt_mode : std_ulogic;                         -- do translation through TLB
 342         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 343         mode_32bit : std_ulogic;                        -- trim addresses to 32 bits
 344         is_32bit : std_ulogic;
 345         repeat : std_ulogic;
 346         second : std_ulogic;
 347     end record;
 348     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 349                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 350                                                                      reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 351                                                                      nia => (others => '0'), insn => (others => '0'),
 352                                                                      addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'),
 353                                                                      write_reg => (others => '0'), length => (others => '0'),
 354                                                                      mode_32bit => '0', is_32bit => '0',
 355                                                                      repeat => '0', second => '0');
 356
 357     type Loadstore1ToExecute1Type is record
 358         busy : std_ulogic;
 359         exception : std_ulogic;
 360         alignment : std_ulogic;
 361         invalid : std_ulogic;
 362         perm_error : std_ulogic;
 363         rc_error : std_ulogic;
 364         badtree : std_ulogic;
 365         segment_fault : std_ulogic;
 366         instr_fault : std_ulogic;
 367     end record;
 368
 369     type Loadstore1ToDcacheType is record
 370         valid : std_ulogic;
 371         load : std_ulogic;                              -- is this a load
 372         dcbz : std_ulogic;
 373         nc : std_ulogic;
 374         reserve : std_ulogic;
 375         atomic : std_ulogic;                            -- part of a multi-transfer atomic op
 376         atomic_last : std_ulogic;
 377         virt_mode : std_ulogic;
 378         priv_mode : std_ulogic;
 379         addr : std_ulogic_vector(63 downto 0);
 380         data : std_ulogic_vector(63 downto 0);          -- valid the cycle after .valid = 1
 381         byte_sel : std_ulogic_vector(7 downto 0);
 382     end record;
 383
 384     type DcacheToLoadstore1Type is record
 385         valid : std_ulogic;
 386         data : std_ulogic_vector(63 downto 0);
 387         store_done : std_ulogic;
 388         error : std_ulogic;
 389         cache_paradox : std_ulogic;
 390     end record;
 391
 392     type Loadstore1ToMmuType is record
 393         valid : std_ulogic;
 394         tlbie : std_ulogic;
 395         slbia : std_ulogic;
 396         mtspr : std_ulogic;
 397         iside : std_ulogic;
 398         load  : std_ulogic;
 399         priv  : std_ulogic;
 400         sprn  : std_ulogic_vector(9 downto 0);
 401         addr  : std_ulogic_vector(63 downto 0);
 402         rs    : std_ulogic_vector(63 downto 0);
 403     end record;
 404
 405     type MmuToLoadstore1Type is record
 406         done       : std_ulogic;
 407         err        : std_ulogic;
 408         invalid    : std_ulogic;
 409         badtree    : std_ulogic;
 410         segerr     : std_ulogic;
 411         perm_error : std_ulogic;
 412         rc_error   : std_ulogic;
 413         sprval     : std_ulogic_vector(63 downto 0);
 414     end record;
 415
 416     type MmuToDcacheType is record
 417         valid : std_ulogic;
 418         tlbie : std_ulogic;
 419         doall : std_ulogic;
 420         tlbld : std_ulogic;
 421         addr  : std_ulogic_vector(63 downto 0);
 422         pte   : std_ulogic_vector(63 downto 0);
 423     end record;
 424
 425     type DcacheToMmuType is record
 426         stall : std_ulogic;
 427         done  : std_ulogic;
 428         err   : std_ulogic;
 429         data  : std_ulogic_vector(63 downto 0);
 430     end record;
 431
 432     type MmuToIcacheType is record
 433         tlbld : std_ulogic;
 434         tlbie : std_ulogic;
 435         doall : std_ulogic;
 436         addr  : std_ulogic_vector(63 downto 0);
 437         pte   : std_ulogic_vector(63 downto 0);
 438     end record;
 439
 440     type Loadstore1ToWritebackType is record
 441         valid : std_ulogic;
 442         write_enable: std_ulogic;
 443         write_reg : gspr_index_t;
 444         write_data : std_ulogic_vector(63 downto 0);
 445         xerc : xer_common_t;
 446         rc : std_ulogic;
 447         store_done : std_ulogic;
 448     end record;
 449     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 450                                                                        rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
 451
 452     type Execute1ToWritebackType is record
 453         valid: std_ulogic;
 454         rc : std_ulogic;
 455         mode_32bit : std_ulogic;
 456         write_enable : std_ulogic;
 457         write_reg: gspr_index_t;
 458         write_data: std_ulogic_vector(63 downto 0);
 459         write_cr_enable : std_ulogic;
 460         write_cr_mask : std_ulogic_vector(7 downto 0);
 461         write_cr_data : std_ulogic_vector(31 downto 0);
 462         write_xerc_enable : std_ulogic;
 463         xerc : xer_common_t;
 464         exc_write_enable : std_ulogic;
 465         exc_write_reg : gspr_index_t;
 466         exc_write_data : std_ulogic_vector(63 downto 0);
 467     end record;
 468     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', mode_32bit => '0', write_enable => '0',
 469                                                                    write_cr_enable => '0', exc_write_enable => '0',
 470                                                                    write_xerc_enable => '0', xerc => xerc_init,
 471                                    write_data => (others => '0'), write_cr_mask => (others => '0'),
 472                                    write_cr_data => (others => '0'), write_reg => (others => '0'),
 473                                    exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
 474
 475     type Execute1ToFPUType is record
 476         valid   : std_ulogic;
 477         op      : insn_type_t;
 478         nia     : std_ulogic_vector(63 downto 0);
 479         insn    : std_ulogic_vector(31 downto 0);
 480         single  : std_ulogic;
 481         fe_mode : std_ulogic_vector(1 downto 0);
 482         fra     : std_ulogic_vector(63 downto 0);
 483         frb     : std_ulogic_vector(63 downto 0);
 484         frc     : std_ulogic_vector(63 downto 0);
 485         frt     : gspr_index_t;
 486         rc      : std_ulogic;
 487         out_cr  : std_ulogic;
 488     end record;
 489     constant Execute1ToFPUInit : Execute1ToFPUType := (valid => '0', op => OP_ILLEGAL, nia => (others => '0'),
 490                                                        insn  => (others => '0'), fe_mode => "00", rc => '0',
 491                                                        fra => (others => '0'), frb => (others => '0'),
 492                                                        frc => (others => '0'), frt => (others => '0'),
 493                                                        single => '0', out_cr => '0');
 494
 495     type FPUToExecute1Type is record
 496         busy      : std_ulogic;
 497         exception : std_ulogic;
 498         interrupt : std_ulogic;
 499         illegal   : std_ulogic;
 500     end record;
 501     constant FPUToExecute1Init : FPUToExecute1Type := (others => '0');
 502
 503     type FPUToWritebackType is record
 504         valid           : std_ulogic;
 505         write_enable    : std_ulogic;
 506         write_reg       : gspr_index_t;
 507         write_data      : std_ulogic_vector(63 downto 0);
 508         write_cr_enable : std_ulogic;
 509         write_cr_mask   : std_ulogic_vector(7 downto 0);
 510         write_cr_data   : std_ulogic_vector(31 downto 0);
 511     end record;
 512     constant FPUToWritebackInit : FPUToWritebackType :=  (valid => '0', write_enable => '0', write_cr_enable => '0', others => (others => '0'));
 513
 514     type DividerToExecute1Type is record
 515         valid: std_ulogic;
 516         write_reg_data: std_ulogic_vector(63 downto 0);
 517         overflow : std_ulogic;
 518     end record;
 519     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 520                                                                others => (others => '0'));
 521
 522     type WritebackToRegisterFileType is record
 523         write_reg : gspr_index_t;
 524         write_data : std_ulogic_vector(63 downto 0);
 525         write_enable : std_ulogic;
 526     end record;
 527     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
 528
 529     type WritebackToCrFileType is record
 530         write_cr_enable : std_ulogic;
 531         write_cr_mask : std_ulogic_vector(7 downto 0);
 532         write_cr_data : std_ulogic_vector(31 downto 0);
 533         write_xerc_enable : std_ulogic;
 534         write_xerc_data : xer_common_t;
 535     end record;
 536     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 537                                                                write_xerc_data => xerc_init,
 538                                                                write_cr_mask => (others => '0'),
 539                                                                write_cr_data => (others => '0'));
 540
 541 end common;
 542
 543 package body common is
 544     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 545     begin
 546         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 547     end;
 548     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 549        variable n : integer range 0 to 31;
 550        -- tmp variable introduced as workaround for VCS compilation
 551        -- simulation was failing with subtype constraint mismatch error
 552        -- see GitHub PR #173
 553        variable tmp : std_ulogic_vector(4 downto 0);
 554     begin
 555        case spr is
 556        when SPR_LR =>
 557            n := 0;              -- N.B. decode2 relies on this specific value
 558        when SPR_CTR =>
 559            n := 1;              -- N.B. decode2 relies on this specific value
 560        when SPR_SRR0 =>
 561            n := 2;
 562        when SPR_SRR1 =>
 563            n := 3;
 564        when SPR_HSRR0 =>
 565            n := 4;
 566        when SPR_HSRR1 =>
 567            n := 5;
 568        when SPR_SPRG0 =>
 569            n := 6;
 570        when SPR_SPRG1 =>
 571            n := 7;
 572        when SPR_SPRG2 =>
 573            n := 8;
 574        when SPR_SPRG3 | SPR_SPRG3U =>
 575            n := 9;
 576        when SPR_HSPRG0 =>
 577            n := 10;
 578        when SPR_HSPRG1 =>
 579            n := 11;
 580        when SPR_XER =>
 581            n := 12;
 582        when SPR_TAR =>
 583            n := 13;
 584        when others =>
 585            n := 0;
 586            return "0000000";
 587        end case;
 588        tmp := std_ulogic_vector(to_unsigned(n, 5));
 589        return "01" & tmp;
 590     end;
 591
 592     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 593     begin
 594         return i(4 downto 0);
 595     end;
 596
 597     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 598     begin
 599         return "00" & i;
 600     end;
 601
 602     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 603     begin
 604         if s(5) = '1' then
 605             return s;
 606         else
 607             return gpr_to_gspr(g);
 608         end if;
 609     end;
 610
 611     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 612     begin
 613         return s(5);
 614     end;
 615
 616     function fpr_to_gspr(f: fpr_index_t) return gspr_index_t is
 617     begin
 618         return "10" & f;
 619     end;
 620 end common;