common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.utils.all;
   7 use work.decode_types.all;
   8
   9 package common is
  10     -- Processor Version Number
  11     constant PVR_MICROWATT  : std_ulogic_vector(31 downto 0) := x"00630000";
  12
  13     -- MSR bit numbers
  14     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  15     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  16     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  17     constant MSR_FP  : integer := (63 - 50);    -- Floating Point available
  18     constant MSR_FE0 : integer := (63 - 52);    -- Floating Exception mode
  19     constant MSR_SE  : integer := (63 - 53);    -- Single-step bit of TE field
  20     constant MSR_BE  : integer := (63 - 54);    -- Branch trace bit of TE field
  21     constant MSR_FE1 : integer := (63 - 55);    -- Floating Exception mode
  22     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  23     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  24     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  25     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  26
  27     -- SPR numbers
  28     subtype spr_num_t is integer range 0 to 1023;
  29
  30     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  31
  32     constant SPR_XER    : spr_num_t := 1;
  33     constant SPR_LR     : spr_num_t := 8;
  34     constant SPR_CTR    : spr_num_t := 9;
  35     constant SPR_TAR    : spr_num_t := 815;
  36     constant SPR_DSISR  : spr_num_t := 18;
  37     constant SPR_DAR    : spr_num_t := 19;
  38     constant SPR_TB     : spr_num_t := 268;
  39     constant SPR_TBU    : spr_num_t := 269;
  40     constant SPR_DEC    : spr_num_t := 22;
  41     constant SPR_SRR0   : spr_num_t := 26;
  42     constant SPR_SRR1   : spr_num_t := 27;
  43     constant SPR_CFAR   : spr_num_t := 28;
  44     constant SPR_HSRR0  : spr_num_t := 314;
  45     constant SPR_HSRR1  : spr_num_t := 315;
  46     constant SPR_SPRG0  : spr_num_t := 272;
  47     constant SPR_SPRG1  : spr_num_t := 273;
  48     constant SPR_SPRG2  : spr_num_t := 274;
  49     constant SPR_SPRG3  : spr_num_t := 275;
  50     constant SPR_SPRG3U : spr_num_t := 259;
  51     constant SPR_HSPRG0 : spr_num_t := 304;
  52     constant SPR_HSPRG1 : spr_num_t := 305;
  53     constant SPR_PID    : spr_num_t := 48;
  54     constant SPR_PRTBL  : spr_num_t := 720;
  55     constant SPR_PVR    : spr_num_t := 287;
  56
  57     -- GPR indices in the register file (GPR only)
  58     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  59
  60     -- Extended GPR index (can hold an SPR or a FPR)
  61     subtype gspr_index_t is std_ulogic_vector(6 downto 0);
  62
  63     -- FPR indices
  64     subtype fpr_index_t is std_ulogic_vector(4 downto 0);
  65
  66     -- Some SPRs are stored in the register file, they use the magic
  67     -- GPR numbers above 31.
  68     --
  69     -- The function fast_spr_num() returns the corresponding fast
  70     -- pseudo-GPR number for a given SPR number. The result MSB
  71     -- indicates if this is indeed a fast SPR. If clear, then
  72     -- the SPR is not stored in the GPR file.
  73     --
  74     -- FPRs are also stored in the register file, using GSPR
  75     -- numbers from 64 to 95.
  76     --
  77     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  78
  79     -- Indices conversion functions
  80     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  81     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  82     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  83     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  84     function fpr_to_gspr(f: fpr_index_t) return gspr_index_t;
  85
  86     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  87     -- in the CR file as a kind of CR extension (with a separate write
  88     -- control). The rest is stored as a fast SPR.
  89     type xer_common_t is record
  90         ca : std_ulogic;
  91         ca32 : std_ulogic;
  92         ov : std_ulogic;
  93         ov32 : std_ulogic;
  94         so : std_ulogic;
  95     end record;
  96     constant xerc_init : xer_common_t := (others => '0');
  97
  98     -- FPSCR bit numbers
  99     constant FPSCR_FX     : integer := 63 - 32;
 100     constant FPSCR_FEX    : integer := 63 - 33;
 101     constant FPSCR_VX     : integer := 63 - 34;
 102     constant FPSCR_OX     : integer := 63 - 35;
 103     constant FPSCR_UX     : integer := 63 - 36;
 104     constant FPSCR_ZX     : integer := 63 - 37;
 105     constant FPSCR_XX     : integer := 63 - 38;
 106     constant FPSCR_VXSNAN : integer := 63 - 39;
 107     constant FPSCR_VXISI  : integer := 63 - 40;
 108     constant FPSCR_VXIDI  : integer := 63 - 41;
 109     constant FPSCR_VXZDZ  : integer := 63 - 42;
 110     constant FPSCR_VXIMZ  : integer := 63 - 43;
 111     constant FPSCR_VXVC   : integer := 63 - 44;
 112     constant FPSCR_FR     : integer := 63 - 45;
 113     constant FPSCR_FI     : integer := 63 - 46;
 114     constant FPSCR_C      : integer := 63 - 47;
 115     constant FPSCR_FL     : integer := 63 - 48;
 116     constant FPSCR_FG     : integer := 63 - 49;
 117     constant FPSCR_FE     : integer := 63 - 50;
 118     constant FPSCR_FU     : integer := 63 - 51;
 119     constant FPSCR_VXSOFT : integer := 63 - 53;
 120     constant FPSCR_VXSQRT : integer := 63 - 54;
 121     constant FPSCR_VXCVI  : integer := 63 - 55;
 122     constant FPSCR_VE     : integer := 63 - 56;
 123     constant FPSCR_OE     : integer := 63 - 57;
 124     constant FPSCR_UE     : integer := 63 - 58;
 125     constant FPSCR_ZE     : integer := 63 - 59;
 126     constant FPSCR_XE     : integer := 63 - 60;
 127     constant FPSCR_NI     : integer := 63 - 61;
 128     constant FPSCR_RN     : integer := 63 - 63;
 129
 130     -- Used for tracking instruction completion and pending register writes
 131     constant TAG_COUNT : positive := 4;
 132     constant TAG_NUMBER_BITS : natural := log2(TAG_COUNT);
 133     subtype tag_number_t is integer range 0 to TAG_COUNT - 1;
 134     subtype tag_index_t is unsigned(TAG_NUMBER_BITS - 1 downto 0);
 135     type instr_tag_t is record
 136         tag   : tag_number_t;
 137         valid : std_ulogic;
 138     end record;
 139     constant instr_tag_init : instr_tag_t := (tag => 0, valid => '0');
 140
 141     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
 142
 143     -- For now, fixed 16 sources, make this either a parametric
 144     -- package of some sort or an unconstrainted array.
 145     type ics_to_icp_t is record
 146         -- Level interrupts only, ICS just keeps prsenting the
 147         -- highest priority interrupt. Once handling edge, something
 148         -- smarter involving handshake & reject support will be needed
 149         src : std_ulogic_vector(3 downto 0);
 150         pri : std_ulogic_vector(7 downto 0);
 151     end record;
 152
 153     -- This needs to die...
 154     type ctrl_t is record
 155         tb: std_ulogic_vector(63 downto 0);
 156         dec: std_ulogic_vector(63 downto 0);
 157         msr: std_ulogic_vector(63 downto 0);
 158         cfar: std_ulogic_vector(63 downto 0);
 159         irq_state : irq_state_t;
 160         srr1: std_ulogic_vector(63 downto 0);
 161     end record;
 162
 163     type Fetch1ToIcacheType is record
 164         req: std_ulogic;
 165         virt_mode : std_ulogic;
 166         priv_mode : std_ulogic;
 167         big_endian : std_ulogic;
 168         stop_mark: std_ulogic;
 169         sequential: std_ulogic;
 170         predicted : std_ulogic;
 171         nia: std_ulogic_vector(63 downto 0);
 172     end record;
 173
 174     type IcacheToDecode1Type is record
 175         valid: std_ulogic;
 176         stop_mark: std_ulogic;
 177         fetch_failed: std_ulogic;
 178         nia: std_ulogic_vector(63 downto 0);
 179         insn: std_ulogic_vector(31 downto 0);
 180         big_endian: std_ulogic;
 181         next_predicted: std_ulogic;
 182     end record;
 183
 184     type Decode1ToDecode2Type is record
 185         valid: std_ulogic;
 186         stop_mark : std_ulogic;
 187         nia: std_ulogic_vector(63 downto 0);
 188         insn: std_ulogic_vector(31 downto 0);
 189         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 190         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 191         ispro: gspr_index_t; -- (G)SPR written with LR or CTR
 192         decode: decode_rom_t;
 193         br_pred: std_ulogic; -- Branch was predicted to be taken
 194         big_endian: std_ulogic;
 195     end record;
 196     constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
 197         (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
 198          ispr1 => (others => '0'), ispr2 => (others => '0'), ispro => (others => '0'),
 199          decode => decode_rom_init, br_pred => '0', big_endian => '0');
 200
 201     type Decode1ToFetch1Type is record
 202         redirect     : std_ulogic;
 203         redirect_nia : std_ulogic_vector(63 downto 0);
 204     end record;
 205
 206     type Decode2ToExecute1Type is record
 207         valid: std_ulogic;
 208         unit : unit_t;
 209         fac : facility_t;
 210         insn_type: insn_type_t;
 211         nia: std_ulogic_vector(63 downto 0);
 212         instr_tag : instr_tag_t;
 213         write_reg: gspr_index_t;
 214         write_reg_enable: std_ulogic;
 215         read_reg1: gspr_index_t;
 216         read_reg2: gspr_index_t;
 217         read_data1: std_ulogic_vector(63 downto 0);
 218         read_data2: std_ulogic_vector(63 downto 0);
 219         read_data3: std_ulogic_vector(63 downto 0);
 220         bypass_data1: std_ulogic;
 221         bypass_data2: std_ulogic;
 222         bypass_data3: std_ulogic;
 223         cr: std_ulogic_vector(31 downto 0);
 224         bypass_cr : std_ulogic;
 225         xerc: xer_common_t;
 226         lr: std_ulogic;
 227         br_abs: std_ulogic;
 228         rc: std_ulogic;
 229         oe: std_ulogic;
 230         invert_a: std_ulogic;
 231         addm1 : std_ulogic;
 232         invert_out: std_ulogic;
 233         input_carry: carry_in_t;
 234         output_carry: std_ulogic;
 235         input_cr: std_ulogic;
 236         output_cr: std_ulogic;
 237         is_32bit: std_ulogic;
 238         is_signed: std_ulogic;
 239         insn: std_ulogic_vector(31 downto 0);
 240         data_len: std_ulogic_vector(3 downto 0);
 241         byte_reverse : std_ulogic;
 242         sign_extend : std_ulogic;                       -- do we need to sign extend?
 243         update : std_ulogic;                            -- is this an update instruction?
 244         reserve : std_ulogic;                           -- set for larx/stcx
 245         br_pred : std_ulogic;
 246         result_sel : std_ulogic_vector(2 downto 0);     -- select source of result
 247         sub_select : std_ulogic_vector(2 downto 0);     -- sub-result selection
 248         repeat : std_ulogic;                            -- set if instruction is cracked into two ops
 249         second : std_ulogic;                            -- set if this is the second op
 250     end record;
 251     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 252         (valid => '0', unit => NONE, fac => NONE, insn_type => OP_ILLEGAL, instr_tag => instr_tag_init,
 253          write_reg_enable => '0', bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 254          bypass_cr => '0', lr => '0', br_abs => '0', rc => '0', oe => '0', invert_a => '0', addm1 => '0',
 255          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 256          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
 257          byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'),
 258          read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'),
 259          cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'),
 260          result_sel => "000", sub_select => "000",
 261          repeat => '0', second => '0', others => (others => '0'));
 262
 263     type MultiplyInputType is record
 264         valid: std_ulogic;
 265         data1: std_ulogic_vector(63 downto 0);
 266         data2: std_ulogic_vector(63 downto 0);
 267         addend: std_ulogic_vector(127 downto 0);
 268         is_32bit: std_ulogic;
 269         not_result: std_ulogic;
 270     end record;
 271     constant MultiplyInputInit : MultiplyInputType := (valid => '0',
 272                                                        is_32bit => '0', not_result => '0',
 273                                                        others => (others => '0'));
 274
 275     type MultiplyOutputType is record
 276         valid: std_ulogic;
 277         result: std_ulogic_vector(127 downto 0);
 278         overflow : std_ulogic;
 279     end record;
 280     constant MultiplyOutputInit : MultiplyOutputType := (valid => '0', overflow => '0',
 281                                                          others => (others => '0'));
 282
 283     type Execute1ToDividerType is record
 284         valid: std_ulogic;
 285         dividend: std_ulogic_vector(63 downto 0);
 286         divisor: std_ulogic_vector(63 downto 0);
 287         is_signed: std_ulogic;
 288         is_32bit: std_ulogic;
 289         is_extended: std_ulogic;
 290         is_modulus: std_ulogic;
 291         neg_result: std_ulogic;
 292     end record;
 293     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 294                                                               is_extended => '0', is_modulus => '0',
 295                                                               neg_result => '0', others => (others => '0'));
 296
 297     type Decode2ToRegisterFileType is record
 298         read1_enable : std_ulogic;
 299         read1_reg : gspr_index_t;
 300         read2_enable : std_ulogic;
 301         read2_reg : gspr_index_t;
 302         read3_enable : std_ulogic;
 303         read3_reg : gspr_index_t;
 304     end record;
 305
 306     type RegisterFileToDecode2Type is record
 307         read1_data : std_ulogic_vector(63 downto 0);
 308         read2_data : std_ulogic_vector(63 downto 0);
 309         read3_data : std_ulogic_vector(63 downto 0);
 310     end record;
 311
 312     type Decode2ToCrFileType is record
 313         read : std_ulogic;
 314     end record;
 315
 316     type CrFileToDecode2Type is record
 317         read_cr_data   : std_ulogic_vector(31 downto 0);
 318         read_xerc_data : xer_common_t;
 319     end record;
 320
 321     type Execute1ToFetch1Type is record
 322         redirect: std_ulogic;
 323         virt_mode: std_ulogic;
 324         priv_mode: std_ulogic;
 325         big_endian: std_ulogic;
 326         mode_32bit: std_ulogic;
 327         redirect_nia: std_ulogic_vector(63 downto 0);
 328         br_nia : std_ulogic_vector(63 downto 0);
 329         br_last : std_ulogic;
 330         br_taken : std_ulogic;
 331     end record;
 332     constant Execute1ToFetch1Init : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
 333                                                              priv_mode => '0', big_endian => '0',
 334                                                              mode_32bit => '0', br_taken => '0',
 335                                                              br_last => '0', others => (others => '0'));
 336
 337     type Execute1ToLoadstore1Type is record
 338         valid : std_ulogic;
 339         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 340         nia : std_ulogic_vector(63 downto 0);
 341         insn : std_ulogic_vector(31 downto 0);
 342         instr_tag : instr_tag_t;
 343         addr1 : std_ulogic_vector(63 downto 0);
 344         addr2 : std_ulogic_vector(63 downto 0);
 345         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 346         write_reg : gspr_index_t;
 347         length : std_ulogic_vector(3 downto 0);
 348         ci : std_ulogic;                                -- cache-inhibited load/store
 349         byte_reverse : std_ulogic;
 350         sign_extend : std_ulogic;                       -- do we need to sign extend?
 351         update : std_ulogic;                            -- is this an update instruction?
 352         xerc : xer_common_t;
 353         reserve : std_ulogic;                           -- set for larx/stcx.
 354         rc : std_ulogic;                                -- set for stcx.
 355         virt_mode : std_ulogic;                         -- do translation through TLB
 356         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 357         mode_32bit : std_ulogic;                        -- trim addresses to 32 bits
 358         is_32bit : std_ulogic;
 359         repeat : std_ulogic;
 360         second : std_ulogic;
 361     end record;
 362     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type :=
 363         (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 364          sign_extend => '0', update => '0', xerc => xerc_init,
 365          reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 366          nia => (others => '0'), insn => (others => '0'),
 367          instr_tag => instr_tag_init,
 368          addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'),
 369          write_reg => (others => '0'),
 370          length => (others => '0'),
 371          mode_32bit => '0', is_32bit => '0',
 372          repeat => '0', second => '0');
 373
 374     type Loadstore1ToExecute1Type is record
 375         busy : std_ulogic;
 376         exception : std_ulogic;
 377         alignment : std_ulogic;
 378         invalid : std_ulogic;
 379         perm_error : std_ulogic;
 380         rc_error : std_ulogic;
 381         badtree : std_ulogic;
 382         segment_fault : std_ulogic;
 383         instr_fault : std_ulogic;
 384     end record;
 385
 386     type Loadstore1ToDcacheType is record
 387         valid : std_ulogic;
 388         load : std_ulogic;                              -- is this a load
 389         dcbz : std_ulogic;
 390         nc : std_ulogic;
 391         reserve : std_ulogic;
 392         atomic : std_ulogic;                            -- part of a multi-transfer atomic op
 393         atomic_last : std_ulogic;
 394         virt_mode : std_ulogic;
 395         priv_mode : std_ulogic;
 396         addr : std_ulogic_vector(63 downto 0);
 397         data : std_ulogic_vector(63 downto 0);          -- valid the cycle after .valid = 1
 398         byte_sel : std_ulogic_vector(7 downto 0);
 399     end record;
 400
 401     type DcacheToLoadstore1Type is record
 402         valid : std_ulogic;
 403         data : std_ulogic_vector(63 downto 0);
 404         store_done : std_ulogic;
 405         error : std_ulogic;
 406         cache_paradox : std_ulogic;
 407     end record;
 408
 409     type Loadstore1ToMmuType is record
 410         valid : std_ulogic;
 411         tlbie : std_ulogic;
 412         slbia : std_ulogic;
 413         mtspr : std_ulogic;
 414         iside : std_ulogic;
 415         load  : std_ulogic;
 416         priv  : std_ulogic;
 417         sprn  : std_ulogic_vector(9 downto 0);
 418         addr  : std_ulogic_vector(63 downto 0);
 419         rs    : std_ulogic_vector(63 downto 0);
 420     end record;
 421
 422     type MmuToLoadstore1Type is record
 423         done       : std_ulogic;
 424         err        : std_ulogic;
 425         invalid    : std_ulogic;
 426         badtree    : std_ulogic;
 427         segerr     : std_ulogic;
 428         perm_error : std_ulogic;
 429         rc_error   : std_ulogic;
 430         sprval     : std_ulogic_vector(63 downto 0);
 431     end record;
 432
 433     type MmuToDcacheType is record
 434         valid : std_ulogic;
 435         tlbie : std_ulogic;
 436         doall : std_ulogic;
 437         tlbld : std_ulogic;
 438         addr  : std_ulogic_vector(63 downto 0);
 439         pte   : std_ulogic_vector(63 downto 0);
 440     end record;
 441
 442     type DcacheToMmuType is record
 443         stall : std_ulogic;
 444         done  : std_ulogic;
 445         err   : std_ulogic;
 446         data  : std_ulogic_vector(63 downto 0);
 447     end record;
 448
 449     type MmuToIcacheType is record
 450         tlbld : std_ulogic;
 451         tlbie : std_ulogic;
 452         doall : std_ulogic;
 453         addr  : std_ulogic_vector(63 downto 0);
 454         pte   : std_ulogic_vector(63 downto 0);
 455     end record;
 456
 457     type Loadstore1ToWritebackType is record
 458         valid : std_ulogic;
 459         instr_tag : instr_tag_t;
 460         write_enable: std_ulogic;
 461         write_reg : gspr_index_t;
 462         write_data : std_ulogic_vector(63 downto 0);
 463         xerc : xer_common_t;
 464         rc : std_ulogic;
 465         store_done : std_ulogic;
 466     end record;
 467     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType :=
 468         (valid => '0', instr_tag => instr_tag_init, write_enable => '0', xerc => xerc_init,
 469          rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
 470
 471     type Execute1ToWritebackType is record
 472         valid: std_ulogic;
 473         instr_tag : instr_tag_t;
 474         rc : std_ulogic;
 475         mode_32bit : std_ulogic;
 476         write_enable : std_ulogic;
 477         write_reg: gspr_index_t;
 478         write_data: std_ulogic_vector(63 downto 0);
 479         write_cr_enable : std_ulogic;
 480         write_cr_mask : std_ulogic_vector(7 downto 0);
 481         write_cr_data : std_ulogic_vector(31 downto 0);
 482         write_xerc_enable : std_ulogic;
 483         xerc : xer_common_t;
 484         exc_write_enable : std_ulogic;
 485         exc_write_reg : gspr_index_t;
 486         exc_write_data : std_ulogic_vector(63 downto 0);
 487     end record;
 488     constant Execute1ToWritebackInit : Execute1ToWritebackType :=
 489         (valid => '0', instr_tag => instr_tag_init, rc => '0', mode_32bit => '0',
 490          write_enable => '0', write_cr_enable => '0', exc_write_enable => '0',
 491          write_xerc_enable => '0', xerc => xerc_init,
 492          write_data => (others => '0'), write_cr_mask => (others => '0'),
 493          write_cr_data => (others => '0'), write_reg => (others => '0'),
 494          exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
 495
 496     type Execute1ToFPUType is record
 497         valid   : std_ulogic;
 498         op      : insn_type_t;
 499         nia     : std_ulogic_vector(63 downto 0);
 500         itag    : instr_tag_t;
 501         insn    : std_ulogic_vector(31 downto 0);
 502         single  : std_ulogic;
 503         fe_mode : std_ulogic_vector(1 downto 0);
 504         fra     : std_ulogic_vector(63 downto 0);
 505         frb     : std_ulogic_vector(63 downto 0);
 506         frc     : std_ulogic_vector(63 downto 0);
 507         frt     : gspr_index_t;
 508         rc      : std_ulogic;
 509         out_cr  : std_ulogic;
 510     end record;
 511     constant Execute1ToFPUInit : Execute1ToFPUType := (valid => '0', op => OP_ILLEGAL, nia => (others => '0'),
 512                                                        itag => instr_tag_init,
 513                                                        insn  => (others => '0'), fe_mode => "00", rc => '0',
 514                                                        fra => (others => '0'), frb => (others => '0'),
 515                                                        frc => (others => '0'), frt => (others => '0'),
 516                                                        single => '0', out_cr => '0');
 517
 518     type FPUToExecute1Type is record
 519         busy      : std_ulogic;
 520         exception : std_ulogic;
 521         interrupt : std_ulogic;
 522         illegal   : std_ulogic;
 523     end record;
 524     constant FPUToExecute1Init : FPUToExecute1Type := (others => '0');
 525
 526     type FPUToWritebackType is record
 527         valid           : std_ulogic;
 528         instr_tag       : instr_tag_t;
 529         write_enable    : std_ulogic;
 530         write_reg       : gspr_index_t;
 531         write_data      : std_ulogic_vector(63 downto 0);
 532         write_cr_enable : std_ulogic;
 533         write_cr_mask   : std_ulogic_vector(7 downto 0);
 534         write_cr_data   : std_ulogic_vector(31 downto 0);
 535     end record;
 536     constant FPUToWritebackInit : FPUToWritebackType :=  (valid => '0', instr_tag => instr_tag_init,
 537                                                           write_enable => '0', write_cr_enable => '0',
 538                                                           others => (others => '0'));
 539
 540     type DividerToExecute1Type is record
 541         valid: std_ulogic;
 542         write_reg_data: std_ulogic_vector(63 downto 0);
 543         overflow : std_ulogic;
 544     end record;
 545     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 546                                                                others => (others => '0'));
 547
 548     type WritebackToRegisterFileType is record
 549         write_reg : gspr_index_t;
 550         write_data : std_ulogic_vector(63 downto 0);
 551         write_enable : std_ulogic;
 552     end record;
 553     constant WritebackToRegisterFileInit : WritebackToRegisterFileType :=
 554         (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
 555
 556     type WritebackToCrFileType is record
 557         write_cr_enable : std_ulogic;
 558         write_cr_mask : std_ulogic_vector(7 downto 0);
 559         write_cr_data : std_ulogic_vector(31 downto 0);
 560         write_xerc_enable : std_ulogic;
 561         write_xerc_data : xer_common_t;
 562     end record;
 563     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 564                                                                write_xerc_data => xerc_init,
 565                                                                write_cr_mask => (others => '0'),
 566                                                                write_cr_data => (others => '0'));
 567
 568 end common;
 569
 570 package body common is
 571     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 572     begin
 573         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 574     end;
 575     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 576        variable n : integer range 0 to 31;
 577        -- tmp variable introduced as workaround for VCS compilation
 578        -- simulation was failing with subtype constraint mismatch error
 579        -- see GitHub PR #173
 580        variable tmp : std_ulogic_vector(4 downto 0);
 581     begin
 582        case spr is
 583        when SPR_LR =>
 584            n := 0;              -- N.B. decode2 relies on this specific value
 585        when SPR_CTR =>
 586            n := 1;              -- N.B. decode2 relies on this specific value
 587        when SPR_SRR0 =>
 588            n := 2;
 589        when SPR_SRR1 =>
 590            n := 3;
 591        when SPR_HSRR0 =>
 592            n := 4;
 593        when SPR_HSRR1 =>
 594            n := 5;
 595        when SPR_SPRG0 =>
 596            n := 6;
 597        when SPR_SPRG1 =>
 598            n := 7;
 599        when SPR_SPRG2 =>
 600            n := 8;
 601        when SPR_SPRG3 | SPR_SPRG3U =>
 602            n := 9;
 603        when SPR_HSPRG0 =>
 604            n := 10;
 605        when SPR_HSPRG1 =>
 606            n := 11;
 607        when SPR_XER =>
 608            n := 12;
 609        when SPR_TAR =>
 610            n := 13;
 611        when others =>
 612            n := 0;
 613            return "0000000";
 614        end case;
 615        tmp := std_ulogic_vector(to_unsigned(n, 5));
 616        return "01" & tmp;
 617     end;
 618
 619     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 620     begin
 621         return i(4 downto 0);
 622     end;
 623
 624     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 625     begin
 626         return "00" & i;
 627     end;
 628
 629     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 630     begin
 631         if s(5) = '1' then
 632             return s;
 633         else
 634             return gpr_to_gspr(g);
 635         end if;
 636     end;
 637
 638     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 639     begin
 640         return s(5);
 641     end;
 642
 643     function fpr_to_gspr(f: fpr_index_t) return gspr_index_t is
 644     begin
 645         return "10" & f;
 646     end;
 647 end common;