common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9     -- Processor Version Number
  10     constant PVR_MICROWATT  : std_ulogic_vector(31 downto 0) := x"00630000";
  11
  12     -- MSR bit numbers
  13     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  14     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  15     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  16     constant MSR_FP  : integer := (63 - 50);    -- Floating Point available
  17     constant MSR_FE0 : integer := (63 - 52);    -- Floating Exception mode
  18     constant MSR_SE  : integer := (63 - 53);    -- Single-step bit of TE field
  19     constant MSR_BE  : integer := (63 - 54);    -- Branch trace bit of TE field
  20     constant MSR_FE1 : integer := (63 - 55);    -- Floating Exception mode
  21     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  22     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  23     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  24     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  25
  26     -- SPR numbers
  27     subtype spr_num_t is integer range 0 to 1023;
  28
  29     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  30
  31     constant SPR_XER    : spr_num_t := 1;
  32     constant SPR_LR     : spr_num_t := 8;
  33     constant SPR_CTR    : spr_num_t := 9;
  34     constant SPR_TAR    : spr_num_t := 815;
  35     constant SPR_DSISR  : spr_num_t := 18;
  36     constant SPR_DAR    : spr_num_t := 19;
  37     constant SPR_TB     : spr_num_t := 268;
  38     constant SPR_TBU    : spr_num_t := 269;
  39     constant SPR_DEC    : spr_num_t := 22;
  40     constant SPR_SRR0   : spr_num_t := 26;
  41     constant SPR_SRR1   : spr_num_t := 27;
  42     constant SPR_CFAR   : spr_num_t := 28;
  43     constant SPR_HSRR0  : spr_num_t := 314;
  44     constant SPR_HSRR1  : spr_num_t := 315;
  45     constant SPR_SPRG0  : spr_num_t := 272;
  46     constant SPR_SPRG1  : spr_num_t := 273;
  47     constant SPR_SPRG2  : spr_num_t := 274;
  48     constant SPR_SPRG3  : spr_num_t := 275;
  49     constant SPR_SPRG3U : spr_num_t := 259;
  50     constant SPR_HSPRG0 : spr_num_t := 304;
  51     constant SPR_HSPRG1 : spr_num_t := 305;
  52     constant SPR_PID    : spr_num_t := 48;
  53     constant SPR_PRTBL  : spr_num_t := 720;
  54     constant SPR_PVR    : spr_num_t := 287;
  55
  56     -- GPR indices in the register file (GPR only)
  57     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  58
  59     -- Extended GPR index (can hold an SPR or a FPR)
  60     subtype gspr_index_t is std_ulogic_vector(6 downto 0);
  61
  62     -- FPR indices
  63     subtype fpr_index_t is std_ulogic_vector(4 downto 0);
  64
  65     -- Some SPRs are stored in the register file, they use the magic
  66     -- GPR numbers above 31.
  67     --
  68     -- The function fast_spr_num() returns the corresponding fast
  69     -- pseudo-GPR number for a given SPR number. The result MSB
  70     -- indicates if this is indeed a fast SPR. If clear, then
  71     -- the SPR is not stored in the GPR file.
  72     --
  73     -- FPRs are also stored in the register file, using GSPR
  74     -- numbers from 64 to 95.
  75     --
  76     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  77
  78     -- Indices conversion functions
  79     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  80     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  81     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  82     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  83     function fpr_to_gspr(f: fpr_index_t) return gspr_index_t;
  84
  85     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  86     -- in the CR file as a kind of CR extension (with a separate write
  87     -- control). The rest is stored as a fast SPR.
  88     type xer_common_t is record
  89         ca : std_ulogic;
  90         ca32 : std_ulogic;
  91         ov : std_ulogic;
  92         ov32 : std_ulogic;
  93         so : std_ulogic;
  94     end record;
  95     constant xerc_init : xer_common_t := (others => '0');
  96
  97     -- FPSCR bit numbers
  98     constant FPSCR_FX     : integer := 63 - 32;
  99     constant FPSCR_FEX    : integer := 63 - 33;
 100     constant FPSCR_VX     : integer := 63 - 34;
 101     constant FPSCR_OX     : integer := 63 - 35;
 102     constant FPSCR_UX     : integer := 63 - 36;
 103     constant FPSCR_ZX     : integer := 63 - 37;
 104     constant FPSCR_XX     : integer := 63 - 38;
 105     constant FPSCR_VXSNAN : integer := 63 - 39;
 106     constant FPSCR_VXISI  : integer := 63 - 40;
 107     constant FPSCR_VXIDI  : integer := 63 - 41;
 108     constant FPSCR_VXZDZ  : integer := 63 - 42;
 109     constant FPSCR_VXIMZ  : integer := 63 - 43;
 110     constant FPSCR_VXVC   : integer := 63 - 44;
 111     constant FPSCR_FR     : integer := 63 - 45;
 112     constant FPSCR_FI     : integer := 63 - 46;
 113     constant FPSCR_C      : integer := 63 - 47;
 114     constant FPSCR_FL     : integer := 63 - 48;
 115     constant FPSCR_FG     : integer := 63 - 49;
 116     constant FPSCR_FE     : integer := 63 - 50;
 117     constant FPSCR_FU     : integer := 63 - 51;
 118     constant FPSCR_VXSOFT : integer := 63 - 53;
 119     constant FPSCR_VXSQRT : integer := 63 - 54;
 120     constant FPSCR_VXCVI  : integer := 63 - 55;
 121     constant FPSCR_VE     : integer := 63 - 56;
 122     constant FPSCR_OE     : integer := 63 - 57;
 123     constant FPSCR_UE     : integer := 63 - 58;
 124     constant FPSCR_ZE     : integer := 63 - 59;
 125     constant FPSCR_XE     : integer := 63 - 60;
 126     constant FPSCR_NI     : integer := 63 - 61;
 127     constant FPSCR_RN     : integer := 63 - 63;
 128
 129     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
 130
 131     -- For now, fixed 16 sources, make this either a parametric
 132     -- package of some sort or an unconstrainted array.
 133     type ics_to_icp_t is record
 134         -- Level interrupts only, ICS just keeps prsenting the
 135         -- highest priority interrupt. Once handling edge, something
 136         -- smarter involving handshake & reject support will be needed
 137         src : std_ulogic_vector(3 downto 0);
 138         pri : std_ulogic_vector(7 downto 0);
 139     end record;
 140
 141     -- This needs to die...
 142     type ctrl_t is record
 143         tb: std_ulogic_vector(63 downto 0);
 144         dec: std_ulogic_vector(63 downto 0);
 145         msr: std_ulogic_vector(63 downto 0);
 146         cfar: std_ulogic_vector(63 downto 0);
 147         irq_state : irq_state_t;
 148         srr1: std_ulogic_vector(63 downto 0);
 149     end record;
 150
 151     type Fetch1ToIcacheType is record
 152         req: std_ulogic;
 153         virt_mode : std_ulogic;
 154         priv_mode : std_ulogic;
 155         big_endian : std_ulogic;
 156         stop_mark: std_ulogic;
 157         sequential: std_ulogic;
 158         predicted : std_ulogic;
 159         nia: std_ulogic_vector(63 downto 0);
 160     end record;
 161
 162     type IcacheToDecode1Type is record
 163         valid: std_ulogic;
 164         stop_mark: std_ulogic;
 165         fetch_failed: std_ulogic;
 166         nia: std_ulogic_vector(63 downto 0);
 167         insn: std_ulogic_vector(31 downto 0);
 168         big_endian: std_ulogic;
 169         next_predicted: std_ulogic;
 170     end record;
 171
 172     type Decode1ToDecode2Type is record
 173         valid: std_ulogic;
 174         stop_mark : std_ulogic;
 175         nia: std_ulogic_vector(63 downto 0);
 176         insn: std_ulogic_vector(31 downto 0);
 177         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 178         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 179         decode: decode_rom_t;
 180         br_pred: std_ulogic; -- Branch was predicted to be taken
 181         big_endian: std_ulogic;
 182     end record;
 183     constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
 184         (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
 185          ispr1 => (others => '0'), ispr2 => (others => '0'), decode => decode_rom_init,
 186          br_pred => '0', big_endian => '0');
 187
 188     type Decode1ToFetch1Type is record
 189         redirect     : std_ulogic;
 190         redirect_nia : std_ulogic_vector(63 downto 0);
 191     end record;
 192
 193     type Decode2ToExecute1Type is record
 194         valid: std_ulogic;
 195         unit : unit_t;
 196         fac : facility_t;
 197         insn_type: insn_type_t;
 198         nia: std_ulogic_vector(63 downto 0);
 199         write_reg: gspr_index_t;
 200         write_reg_enable: std_ulogic;
 201         read_reg1: gspr_index_t;
 202         read_reg2: gspr_index_t;
 203         read_data1: std_ulogic_vector(63 downto 0);
 204         read_data2: std_ulogic_vector(63 downto 0);
 205         read_data3: std_ulogic_vector(63 downto 0);
 206         bypass_data1: std_ulogic;
 207         bypass_data2: std_ulogic;
 208         bypass_data3: std_ulogic;
 209         cr: std_ulogic_vector(31 downto 0);
 210         bypass_cr : std_ulogic;
 211         xerc: xer_common_t;
 212         lr: std_ulogic;
 213         rc: std_ulogic;
 214         oe: std_ulogic;
 215         invert_a: std_ulogic;
 216         addm1 : std_ulogic;
 217         invert_out: std_ulogic;
 218         input_carry: carry_in_t;
 219         output_carry: std_ulogic;
 220         input_cr: std_ulogic;
 221         output_cr: std_ulogic;
 222         is_32bit: std_ulogic;
 223         is_signed: std_ulogic;
 224         insn: std_ulogic_vector(31 downto 0);
 225         data_len: std_ulogic_vector(3 downto 0);
 226         byte_reverse : std_ulogic;
 227         sign_extend : std_ulogic;                       -- do we need to sign extend?
 228         update : std_ulogic;                            -- is this an update instruction?
 229         reserve : std_ulogic;                           -- set for larx/stcx
 230         br_pred : std_ulogic;
 231         result_sel : std_ulogic_vector(2 downto 0);     -- select source of result
 232         sub_select : std_ulogic_vector(2 downto 0);     -- sub-result selection
 233         repeat : std_ulogic;                            -- set if instruction is cracked into two ops
 234         second : std_ulogic;                            -- set if this is the second op
 235     end record;
 236     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 237         (valid => '0', unit => NONE, fac => NONE, insn_type => OP_ILLEGAL,
 238          write_reg_enable => '0', bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 239          bypass_cr => '0', lr => '0', rc => '0', oe => '0', invert_a => '0', addm1 => '0',
 240          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 241          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
 242          byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'),
 243          read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'),
 244          cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'),
 245          result_sel => "000", sub_select => "000",
 246          repeat => '0', second => '0', others => (others => '0'));
 247
 248     type MultiplyInputType is record
 249         valid: std_ulogic;
 250         data1: std_ulogic_vector(63 downto 0);
 251         data2: std_ulogic_vector(63 downto 0);
 252         addend: std_ulogic_vector(127 downto 0);
 253         is_32bit: std_ulogic;
 254         not_result: std_ulogic;
 255     end record;
 256     constant MultiplyInputInit : MultiplyInputType := (valid => '0',
 257                                                        is_32bit => '0', not_result => '0',
 258                                                        others => (others => '0'));
 259
 260     type MultiplyOutputType is record
 261         valid: std_ulogic;
 262         result: std_ulogic_vector(127 downto 0);
 263         overflow : std_ulogic;
 264     end record;
 265     constant MultiplyOutputInit : MultiplyOutputType := (valid => '0', overflow => '0',
 266                                                          others => (others => '0'));
 267
 268     type Execute1ToDividerType is record
 269         valid: std_ulogic;
 270         dividend: std_ulogic_vector(63 downto 0);
 271         divisor: std_ulogic_vector(63 downto 0);
 272         is_signed: std_ulogic;
 273         is_32bit: std_ulogic;
 274         is_extended: std_ulogic;
 275         is_modulus: std_ulogic;
 276         neg_result: std_ulogic;
 277     end record;
 278     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 279                                                               is_extended => '0', is_modulus => '0',
 280                                                               neg_result => '0', others => (others => '0'));
 281
 282     type Decode2ToRegisterFileType is record
 283         read1_enable : std_ulogic;
 284         read1_reg : gspr_index_t;
 285         read2_enable : std_ulogic;
 286         read2_reg : gspr_index_t;
 287         read3_enable : std_ulogic;
 288         read3_reg : gspr_index_t;
 289     end record;
 290
 291     type RegisterFileToDecode2Type is record
 292         read1_data : std_ulogic_vector(63 downto 0);
 293         read2_data : std_ulogic_vector(63 downto 0);
 294         read3_data : std_ulogic_vector(63 downto 0);
 295     end record;
 296
 297     type Decode2ToCrFileType is record
 298         read : std_ulogic;
 299     end record;
 300
 301     type CrFileToDecode2Type is record
 302         read_cr_data   : std_ulogic_vector(31 downto 0);
 303         read_xerc_data : xer_common_t;
 304     end record;
 305
 306     type Execute1ToFetch1Type is record
 307         redirect: std_ulogic;
 308         virt_mode: std_ulogic;
 309         priv_mode: std_ulogic;
 310         big_endian: std_ulogic;
 311         mode_32bit: std_ulogic;
 312         redirect_nia: std_ulogic_vector(63 downto 0);
 313         br_nia : std_ulogic_vector(63 downto 0);
 314         br_last : std_ulogic;
 315         br_taken : std_ulogic;
 316     end record;
 317     constant Execute1ToFetch1Init : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
 318                                                              priv_mode => '0', big_endian => '0',
 319                                                              mode_32bit => '0', br_taken => '0',
 320                                                              br_last => '0', others => (others => '0'));
 321
 322     type Execute1ToLoadstore1Type is record
 323         valid : std_ulogic;
 324         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 325         nia : std_ulogic_vector(63 downto 0);
 326         insn : std_ulogic_vector(31 downto 0);
 327         addr1 : std_ulogic_vector(63 downto 0);
 328         addr2 : std_ulogic_vector(63 downto 0);
 329         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 330         write_reg : gspr_index_t;
 331         length : std_ulogic_vector(3 downto 0);
 332         ci : std_ulogic;                                -- cache-inhibited load/store
 333         byte_reverse : std_ulogic;
 334         sign_extend : std_ulogic;                       -- do we need to sign extend?
 335         update : std_ulogic;                            -- is this an update instruction?
 336         xerc : xer_common_t;
 337         reserve : std_ulogic;                           -- set for larx/stcx.
 338         rc : std_ulogic;                                -- set for stcx.
 339         virt_mode : std_ulogic;                         -- do translation through TLB
 340         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 341         mode_32bit : std_ulogic;                        -- trim addresses to 32 bits
 342         is_32bit : std_ulogic;
 343         repeat : std_ulogic;
 344         second : std_ulogic;
 345     end record;
 346     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 347                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 348                                                                      reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 349                                                                      nia => (others => '0'), insn => (others => '0'),
 350                                                                      addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'),
 351                                                                      write_reg => (others => '0'), length => (others => '0'),
 352                                                                      mode_32bit => '0', is_32bit => '0',
 353                                                                      repeat => '0', second => '0');
 354
 355     type Loadstore1ToExecute1Type is record
 356         busy : std_ulogic;
 357         exception : std_ulogic;
 358         alignment : std_ulogic;
 359         invalid : std_ulogic;
 360         perm_error : std_ulogic;
 361         rc_error : std_ulogic;
 362         badtree : std_ulogic;
 363         segment_fault : std_ulogic;
 364         instr_fault : std_ulogic;
 365     end record;
 366
 367     type Loadstore1ToDcacheType is record
 368         valid : std_ulogic;
 369         load : std_ulogic;                              -- is this a load
 370         dcbz : std_ulogic;
 371         nc : std_ulogic;
 372         reserve : std_ulogic;
 373         atomic : std_ulogic;                            -- part of a multi-transfer atomic op
 374         atomic_last : std_ulogic;
 375         virt_mode : std_ulogic;
 376         priv_mode : std_ulogic;
 377         addr : std_ulogic_vector(63 downto 0);
 378         data : std_ulogic_vector(63 downto 0);          -- valid the cycle after .valid = 1
 379         byte_sel : std_ulogic_vector(7 downto 0);
 380     end record;
 381
 382     type DcacheToLoadstore1Type is record
 383         valid : std_ulogic;
 384         data : std_ulogic_vector(63 downto 0);
 385         store_done : std_ulogic;
 386         error : std_ulogic;
 387         cache_paradox : std_ulogic;
 388     end record;
 389
 390     type Loadstore1ToMmuType is record
 391         valid : std_ulogic;
 392         tlbie : std_ulogic;
 393         slbia : std_ulogic;
 394         mtspr : std_ulogic;
 395         iside : std_ulogic;
 396         load  : std_ulogic;
 397         priv  : std_ulogic;
 398         sprn  : std_ulogic_vector(9 downto 0);
 399         addr  : std_ulogic_vector(63 downto 0);
 400         rs    : std_ulogic_vector(63 downto 0);
 401     end record;
 402
 403     type MmuToLoadstore1Type is record
 404         done       : std_ulogic;
 405         err        : std_ulogic;
 406         invalid    : std_ulogic;
 407         badtree    : std_ulogic;
 408         segerr     : std_ulogic;
 409         perm_error : std_ulogic;
 410         rc_error   : std_ulogic;
 411         sprval     : std_ulogic_vector(63 downto 0);
 412     end record;
 413
 414     type MmuToDcacheType is record
 415         valid : std_ulogic;
 416         tlbie : std_ulogic;
 417         doall : std_ulogic;
 418         tlbld : std_ulogic;
 419         addr  : std_ulogic_vector(63 downto 0);
 420         pte   : std_ulogic_vector(63 downto 0);
 421     end record;
 422
 423     type DcacheToMmuType is record
 424         stall : std_ulogic;
 425         done  : std_ulogic;
 426         err   : std_ulogic;
 427         data  : std_ulogic_vector(63 downto 0);
 428     end record;
 429
 430     type MmuToIcacheType is record
 431         tlbld : std_ulogic;
 432         tlbie : std_ulogic;
 433         doall : std_ulogic;
 434         addr  : std_ulogic_vector(63 downto 0);
 435         pte   : std_ulogic_vector(63 downto 0);
 436     end record;
 437
 438     type Loadstore1ToWritebackType is record
 439         valid : std_ulogic;
 440         write_enable: std_ulogic;
 441         write_reg : gspr_index_t;
 442         write_data : std_ulogic_vector(63 downto 0);
 443         xerc : xer_common_t;
 444         rc : std_ulogic;
 445         store_done : std_ulogic;
 446     end record;
 447     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 448                                                                        rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
 449
 450     type Execute1ToWritebackType is record
 451         valid: std_ulogic;
 452         rc : std_ulogic;
 453         mode_32bit : std_ulogic;
 454         write_enable : std_ulogic;
 455         write_reg: gspr_index_t;
 456         write_data: std_ulogic_vector(63 downto 0);
 457         write_cr_enable : std_ulogic;
 458         write_cr_mask : std_ulogic_vector(7 downto 0);
 459         write_cr_data : std_ulogic_vector(31 downto 0);
 460         write_xerc_enable : std_ulogic;
 461         xerc : xer_common_t;
 462         exc_write_enable : std_ulogic;
 463         exc_write_reg : gspr_index_t;
 464         exc_write_data : std_ulogic_vector(63 downto 0);
 465     end record;
 466     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', mode_32bit => '0', write_enable => '0',
 467                                                                    write_cr_enable => '0', exc_write_enable => '0',
 468                                                                    write_xerc_enable => '0', xerc => xerc_init,
 469                                    write_data => (others => '0'), write_cr_mask => (others => '0'),
 470                                    write_cr_data => (others => '0'), write_reg => (others => '0'),
 471                                    exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
 472
 473     type Execute1ToFPUType is record
 474         valid   : std_ulogic;
 475         op      : insn_type_t;
 476         nia     : std_ulogic_vector(63 downto 0);
 477         insn    : std_ulogic_vector(31 downto 0);
 478         single  : std_ulogic;
 479         fe_mode : std_ulogic_vector(1 downto 0);
 480         fra     : std_ulogic_vector(63 downto 0);
 481         frb     : std_ulogic_vector(63 downto 0);
 482         frc     : std_ulogic_vector(63 downto 0);
 483         frt     : gspr_index_t;
 484         rc      : std_ulogic;
 485         out_cr  : std_ulogic;
 486     end record;
 487     constant Execute1ToFPUInit : Execute1ToFPUType := (valid => '0', op => OP_ILLEGAL, nia => (others => '0'),
 488                                                        insn  => (others => '0'), fe_mode => "00", rc => '0',
 489                                                        fra => (others => '0'), frb => (others => '0'),
 490                                                        frc => (others => '0'), frt => (others => '0'),
 491                                                        single => '0', out_cr => '0');
 492
 493     type FPUToExecute1Type is record
 494         busy      : std_ulogic;
 495         exception : std_ulogic;
 496         interrupt : std_ulogic;
 497         illegal   : std_ulogic;
 498     end record;
 499     constant FPUToExecute1Init : FPUToExecute1Type := (others => '0');
 500
 501     type FPUToWritebackType is record
 502         valid           : std_ulogic;
 503         write_enable    : std_ulogic;
 504         write_reg       : gspr_index_t;
 505         write_data      : std_ulogic_vector(63 downto 0);
 506         write_cr_enable : std_ulogic;
 507         write_cr_mask   : std_ulogic_vector(7 downto 0);
 508         write_cr_data   : std_ulogic_vector(31 downto 0);
 509     end record;
 510     constant FPUToWritebackInit : FPUToWritebackType :=  (valid => '0', write_enable => '0', write_cr_enable => '0', others => (others => '0'));
 511
 512     type DividerToExecute1Type is record
 513         valid: std_ulogic;
 514         write_reg_data: std_ulogic_vector(63 downto 0);
 515         overflow : std_ulogic;
 516     end record;
 517     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 518                                                                others => (others => '0'));
 519
 520     type WritebackToRegisterFileType is record
 521         write_reg : gspr_index_t;
 522         write_data : std_ulogic_vector(63 downto 0);
 523         write_enable : std_ulogic;
 524     end record;
 525     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
 526
 527     type WritebackToCrFileType is record
 528         write_cr_enable : std_ulogic;
 529         write_cr_mask : std_ulogic_vector(7 downto 0);
 530         write_cr_data : std_ulogic_vector(31 downto 0);
 531         write_xerc_enable : std_ulogic;
 532         write_xerc_data : xer_common_t;
 533     end record;
 534     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 535                                                                write_xerc_data => xerc_init,
 536                                                                write_cr_mask => (others => '0'),
 537                                                                write_cr_data => (others => '0'));
 538
 539 end common;
 540
 541 package body common is
 542     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 543     begin
 544         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 545     end;
 546     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 547        variable n : integer range 0 to 31;
 548        -- tmp variable introduced as workaround for VCS compilation
 549        -- simulation was failing with subtype constraint mismatch error
 550        -- see GitHub PR #173
 551        variable tmp : std_ulogic_vector(4 downto 0);
 552     begin
 553        case spr is
 554        when SPR_LR =>
 555            n := 0;
 556        when SPR_CTR =>
 557            n:= 1;
 558        when SPR_SRR0 =>
 559            n := 2;
 560        when SPR_SRR1 =>
 561            n := 3;
 562        when SPR_HSRR0 =>
 563            n := 4;
 564        when SPR_HSRR1 =>
 565            n := 5;
 566        when SPR_SPRG0 =>
 567            n := 6;
 568        when SPR_SPRG1 =>
 569            n := 7;
 570        when SPR_SPRG2 =>
 571            n := 8;
 572        when SPR_SPRG3 | SPR_SPRG3U =>
 573            n := 9;
 574        when SPR_HSPRG0 =>
 575            n := 10;
 576        when SPR_HSPRG1 =>
 577            n := 11;
 578        when SPR_XER =>
 579            n := 12;
 580        when SPR_TAR =>
 581            n := 13;
 582        when others =>
 583            n := 0;
 584            return "0000000";
 585        end case;
 586        tmp := std_ulogic_vector(to_unsigned(n, 5));
 587        return "01" & tmp;
 588     end;
 589
 590     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 591     begin
 592         return i(4 downto 0);
 593     end;
 594
 595     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 596     begin
 597         return "00" & i;
 598     end;
 599
 600     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 601     begin
 602         if s(5) = '1' then
 603             return s;
 604         else
 605             return gpr_to_gspr(g);
 606         end if;
 607     end;
 608
 609     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 610     begin
 611         return s(5);
 612     end;
 613
 614     function fpr_to_gspr(f: fpr_index_t) return gspr_index_t is
 615     begin
 616         return "10" & f;
 617     end;
 618 end common;