common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.utils.all;
   7 use work.decode_types.all;
   8
   9 package common is
  10     -- Processor Version Number
  11     constant PVR_MICROWATT  : std_ulogic_vector(31 downto 0) := x"00630000";
  12
  13     -- MSR bit numbers
  14     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  15     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  16     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  17     constant MSR_FP  : integer := (63 - 50);    -- Floating Point available
  18     constant MSR_FE0 : integer := (63 - 52);    -- Floating Exception mode
  19     constant MSR_SE  : integer := (63 - 53);    -- Single-step bit of TE field
  20     constant MSR_BE  : integer := (63 - 54);    -- Branch trace bit of TE field
  21     constant MSR_FE1 : integer := (63 - 55);    -- Floating Exception mode
  22     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  23     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  24     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  25     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  26
  27     -- SPR numbers
  28     subtype spr_num_t is integer range 0 to 1023;
  29
  30     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  31
  32     constant SPR_XER    : spr_num_t := 1;
  33     constant SPR_LR     : spr_num_t := 8;
  34     constant SPR_CTR    : spr_num_t := 9;
  35     constant SPR_TAR    : spr_num_t := 815;
  36     constant SPR_DSISR  : spr_num_t := 18;
  37     constant SPR_DAR    : spr_num_t := 19;
  38     constant SPR_TB     : spr_num_t := 268;
  39     constant SPR_TBU    : spr_num_t := 269;
  40     constant SPR_DEC    : spr_num_t := 22;
  41     constant SPR_SRR0   : spr_num_t := 26;
  42     constant SPR_SRR1   : spr_num_t := 27;
  43     constant SPR_CFAR   : spr_num_t := 28;
  44     constant SPR_HSRR0  : spr_num_t := 314;
  45     constant SPR_HSRR1  : spr_num_t := 315;
  46     constant SPR_SPRG0  : spr_num_t := 272;
  47     constant SPR_SPRG1  : spr_num_t := 273;
  48     constant SPR_SPRG2  : spr_num_t := 274;
  49     constant SPR_SPRG3  : spr_num_t := 275;
  50     constant SPR_SPRG3U : spr_num_t := 259;
  51     constant SPR_HSPRG0 : spr_num_t := 304;
  52     constant SPR_HSPRG1 : spr_num_t := 305;
  53     constant SPR_PID    : spr_num_t := 48;
  54     constant SPR_PRTBL  : spr_num_t := 720;
  55     constant SPR_PVR    : spr_num_t := 287;
  56
  57     -- GPR indices in the register file (GPR only)
  58     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  59
  60     -- Extended GPR index (can hold an SPR or a FPR)
  61     subtype gspr_index_t is std_ulogic_vector(6 downto 0);
  62
  63     -- FPR indices
  64     subtype fpr_index_t is std_ulogic_vector(4 downto 0);
  65
  66     -- Some SPRs are stored in the register file, they use the magic
  67     -- GPR numbers above 31.
  68     --
  69     -- The function fast_spr_num() returns the corresponding fast
  70     -- pseudo-GPR number for a given SPR number. The result MSB
  71     -- indicates if this is indeed a fast SPR. If clear, then
  72     -- the SPR is not stored in the GPR file.
  73     --
  74     -- FPRs are also stored in the register file, using GSPR
  75     -- numbers from 64 to 95.
  76     --
  77     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  78
  79     -- Indices conversion functions
  80     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  81     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  82     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  83     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  84     function fpr_to_gspr(f: fpr_index_t) return gspr_index_t;
  85
  86     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  87     -- in the CR file as a kind of CR extension (with a separate write
  88     -- control). The rest is stored as a fast SPR.
  89     type xer_common_t is record
  90         ca : std_ulogic;
  91         ca32 : std_ulogic;
  92         ov : std_ulogic;
  93         ov32 : std_ulogic;
  94         so : std_ulogic;
  95     end record;
  96     constant xerc_init : xer_common_t := (others => '0');
  97
  98     -- FPSCR bit numbers
  99     constant FPSCR_FX     : integer := 63 - 32;
 100     constant FPSCR_FEX    : integer := 63 - 33;
 101     constant FPSCR_VX     : integer := 63 - 34;
 102     constant FPSCR_OX     : integer := 63 - 35;
 103     constant FPSCR_UX     : integer := 63 - 36;
 104     constant FPSCR_ZX     : integer := 63 - 37;
 105     constant FPSCR_XX     : integer := 63 - 38;
 106     constant FPSCR_VXSNAN : integer := 63 - 39;
 107     constant FPSCR_VXISI  : integer := 63 - 40;
 108     constant FPSCR_VXIDI  : integer := 63 - 41;
 109     constant FPSCR_VXZDZ  : integer := 63 - 42;
 110     constant FPSCR_VXIMZ  : integer := 63 - 43;
 111     constant FPSCR_VXVC   : integer := 63 - 44;
 112     constant FPSCR_FR     : integer := 63 - 45;
 113     constant FPSCR_FI     : integer := 63 - 46;
 114     constant FPSCR_C      : integer := 63 - 47;
 115     constant FPSCR_FL     : integer := 63 - 48;
 116     constant FPSCR_FG     : integer := 63 - 49;
 117     constant FPSCR_FE     : integer := 63 - 50;
 118     constant FPSCR_FU     : integer := 63 - 51;
 119     constant FPSCR_VXSOFT : integer := 63 - 53;
 120     constant FPSCR_VXSQRT : integer := 63 - 54;
 121     constant FPSCR_VXCVI  : integer := 63 - 55;
 122     constant FPSCR_VE     : integer := 63 - 56;
 123     constant FPSCR_OE     : integer := 63 - 57;
 124     constant FPSCR_UE     : integer := 63 - 58;
 125     constant FPSCR_ZE     : integer := 63 - 59;
 126     constant FPSCR_XE     : integer := 63 - 60;
 127     constant FPSCR_NI     : integer := 63 - 61;
 128     constant FPSCR_RN     : integer := 63 - 63;
 129
 130     -- Used for tracking instruction completion and pending register writes
 131     constant TAG_COUNT : positive := 4;
 132     constant TAG_NUMBER_BITS : natural := log2(TAG_COUNT);
 133     subtype tag_number_t is integer range 0 to TAG_COUNT - 1;
 134     subtype tag_index_t is unsigned(TAG_NUMBER_BITS - 1 downto 0);
 135     type instr_tag_t is record
 136         tag   : tag_number_t;
 137         valid : std_ulogic;
 138     end record;
 139     constant instr_tag_init : instr_tag_t := (tag => 0, valid => '0');
 140     function tag_match(tag1 : instr_tag_t; tag2 : instr_tag_t) return boolean;
 141
 142     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
 143
 144     -- For now, fixed 16 sources, make this either a parametric
 145     -- package of some sort or an unconstrainted array.
 146     type ics_to_icp_t is record
 147         -- Level interrupts only, ICS just keeps prsenting the
 148         -- highest priority interrupt. Once handling edge, something
 149         -- smarter involving handshake & reject support will be needed
 150         src : std_ulogic_vector(3 downto 0);
 151         pri : std_ulogic_vector(7 downto 0);
 152     end record;
 153
 154     -- This needs to die...
 155     type ctrl_t is record
 156         tb: std_ulogic_vector(63 downto 0);
 157         dec: std_ulogic_vector(63 downto 0);
 158         msr: std_ulogic_vector(63 downto 0);
 159         cfar: std_ulogic_vector(63 downto 0);
 160         irq_state : irq_state_t;
 161         srr1: std_ulogic_vector(63 downto 0);
 162     end record;
 163
 164     type Fetch1ToIcacheType is record
 165         req: std_ulogic;
 166         virt_mode : std_ulogic;
 167         priv_mode : std_ulogic;
 168         big_endian : std_ulogic;
 169         stop_mark: std_ulogic;
 170         sequential: std_ulogic;
 171         predicted : std_ulogic;
 172         nia: std_ulogic_vector(63 downto 0);
 173     end record;
 174
 175     type IcacheToDecode1Type is record
 176         valid: std_ulogic;
 177         stop_mark: std_ulogic;
 178         fetch_failed: std_ulogic;
 179         nia: std_ulogic_vector(63 downto 0);
 180         insn: std_ulogic_vector(31 downto 0);
 181         big_endian: std_ulogic;
 182         next_predicted: std_ulogic;
 183     end record;
 184
 185     type Decode1ToDecode2Type is record
 186         valid: std_ulogic;
 187         stop_mark : std_ulogic;
 188         nia: std_ulogic_vector(63 downto 0);
 189         insn: std_ulogic_vector(31 downto 0);
 190         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 191         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 192         ispro: gspr_index_t; -- (G)SPR written with LR or CTR
 193         decode: decode_rom_t;
 194         br_pred: std_ulogic; -- Branch was predicted to be taken
 195         big_endian: std_ulogic;
 196     end record;
 197     constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
 198         (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
 199          ispr1 => (others => '0'), ispr2 => (others => '0'), ispro => (others => '0'),
 200          decode => decode_rom_init, br_pred => '0', big_endian => '0');
 201
 202     type Decode1ToFetch1Type is record
 203         redirect     : std_ulogic;
 204         redirect_nia : std_ulogic_vector(63 downto 0);
 205     end record;
 206
 207     type bypass_data_t is record
 208         tag  : instr_tag_t;
 209         data : std_ulogic_vector(63 downto 0);
 210     end record;
 211     constant bypass_data_init : bypass_data_t := (tag => instr_tag_init, data => (others => '0'));
 212
 213     type Decode2ToExecute1Type is record
 214         valid: std_ulogic;
 215         unit : unit_t;
 216         fac : facility_t;
 217         insn_type: insn_type_t;
 218         nia: std_ulogic_vector(63 downto 0);
 219         instr_tag : instr_tag_t;
 220         write_reg: gspr_index_t;
 221         write_reg_enable: std_ulogic;
 222         read_reg1: gspr_index_t;
 223         read_reg2: gspr_index_t;
 224         read_data1: std_ulogic_vector(63 downto 0);
 225         read_data2: std_ulogic_vector(63 downto 0);
 226         read_data3: std_ulogic_vector(63 downto 0);
 227         cr: std_ulogic_vector(31 downto 0);
 228         bypass_cr : std_ulogic;
 229         xerc: xer_common_t;
 230         lr: std_ulogic;
 231         br_abs: std_ulogic;
 232         rc: std_ulogic;
 233         oe: std_ulogic;
 234         invert_a: std_ulogic;
 235         addm1 : std_ulogic;
 236         invert_out: std_ulogic;
 237         input_carry: carry_in_t;
 238         output_carry: std_ulogic;
 239         input_cr: std_ulogic;
 240         output_cr: std_ulogic;
 241         is_32bit: std_ulogic;
 242         is_signed: std_ulogic;
 243         insn: std_ulogic_vector(31 downto 0);
 244         data_len: std_ulogic_vector(3 downto 0);
 245         byte_reverse : std_ulogic;
 246         sign_extend : std_ulogic;                       -- do we need to sign extend?
 247         update : std_ulogic;                            -- is this an update instruction?
 248         reserve : std_ulogic;                           -- set for larx/stcx
 249         br_pred : std_ulogic;
 250         result_sel : std_ulogic_vector(2 downto 0);     -- select source of result
 251         sub_select : std_ulogic_vector(2 downto 0);     -- sub-result selection
 252         repeat : std_ulogic;                            -- set if instruction is cracked into two ops
 253         second : std_ulogic;                            -- set if this is the second op
 254     end record;
 255     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 256         (valid => '0', unit => NONE, fac => NONE, insn_type => OP_ILLEGAL, instr_tag => instr_tag_init,
 257          write_reg_enable => '0',
 258          bypass_cr => '0', lr => '0', br_abs => '0', rc => '0', oe => '0', invert_a => '0', addm1 => '0',
 259          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 260          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
 261          byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'),
 262          read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'),
 263          cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'),
 264          result_sel => "000", sub_select => "000",
 265          repeat => '0', second => '0', others => (others => '0'));
 266
 267     type MultiplyInputType is record
 268         valid: std_ulogic;
 269         data1: std_ulogic_vector(63 downto 0);
 270         data2: std_ulogic_vector(63 downto 0);
 271         addend: std_ulogic_vector(127 downto 0);
 272         is_32bit: std_ulogic;
 273         not_result: std_ulogic;
 274     end record;
 275     constant MultiplyInputInit : MultiplyInputType := (valid => '0',
 276                                                        is_32bit => '0', not_result => '0',
 277                                                        others => (others => '0'));
 278
 279     type MultiplyOutputType is record
 280         valid: std_ulogic;
 281         result: std_ulogic_vector(127 downto 0);
 282         overflow : std_ulogic;
 283     end record;
 284     constant MultiplyOutputInit : MultiplyOutputType := (valid => '0', overflow => '0',
 285                                                          others => (others => '0'));
 286
 287     type Execute1ToDividerType is record
 288         valid: std_ulogic;
 289         dividend: std_ulogic_vector(63 downto 0);
 290         divisor: std_ulogic_vector(63 downto 0);
 291         is_signed: std_ulogic;
 292         is_32bit: std_ulogic;
 293         is_extended: std_ulogic;
 294         is_modulus: std_ulogic;
 295         neg_result: std_ulogic;
 296     end record;
 297     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 298                                                               is_extended => '0', is_modulus => '0',
 299                                                               neg_result => '0', others => (others => '0'));
 300
 301     type Decode2ToRegisterFileType is record
 302         read1_enable : std_ulogic;
 303         read1_reg : gspr_index_t;
 304         read2_enable : std_ulogic;
 305         read2_reg : gspr_index_t;
 306         read3_enable : std_ulogic;
 307         read3_reg : gspr_index_t;
 308     end record;
 309
 310     type RegisterFileToDecode2Type is record
 311         read1_data : std_ulogic_vector(63 downto 0);
 312         read2_data : std_ulogic_vector(63 downto 0);
 313         read3_data : std_ulogic_vector(63 downto 0);
 314     end record;
 315
 316     type Decode2ToCrFileType is record
 317         read : std_ulogic;
 318     end record;
 319
 320     type CrFileToDecode2Type is record
 321         read_cr_data   : std_ulogic_vector(31 downto 0);
 322         read_xerc_data : xer_common_t;
 323     end record;
 324
 325     type Execute1ToFetch1Type is record
 326         redirect: std_ulogic;
 327         virt_mode: std_ulogic;
 328         priv_mode: std_ulogic;
 329         big_endian: std_ulogic;
 330         mode_32bit: std_ulogic;
 331         redirect_nia: std_ulogic_vector(63 downto 0);
 332         br_nia : std_ulogic_vector(63 downto 0);
 333         br_last : std_ulogic;
 334         br_taken : std_ulogic;
 335     end record;
 336     constant Execute1ToFetch1Init : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
 337                                                              priv_mode => '0', big_endian => '0',
 338                                                              mode_32bit => '0', br_taken => '0',
 339                                                              br_last => '0', others => (others => '0'));
 340
 341     type Execute1ToLoadstore1Type is record
 342         valid : std_ulogic;
 343         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 344         nia : std_ulogic_vector(63 downto 0);
 345         insn : std_ulogic_vector(31 downto 0);
 346         instr_tag : instr_tag_t;
 347         addr1 : std_ulogic_vector(63 downto 0);
 348         addr2 : std_ulogic_vector(63 downto 0);
 349         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 350         write_reg : gspr_index_t;
 351         length : std_ulogic_vector(3 downto 0);
 352         ci : std_ulogic;                                -- cache-inhibited load/store
 353         byte_reverse : std_ulogic;
 354         sign_extend : std_ulogic;                       -- do we need to sign extend?
 355         update : std_ulogic;                            -- is this an update instruction?
 356         xerc : xer_common_t;
 357         reserve : std_ulogic;                           -- set for larx/stcx.
 358         rc : std_ulogic;                                -- set for stcx.
 359         virt_mode : std_ulogic;                         -- do translation through TLB
 360         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 361         mode_32bit : std_ulogic;                        -- trim addresses to 32 bits
 362         is_32bit : std_ulogic;
 363         repeat : std_ulogic;
 364         second : std_ulogic;
 365     end record;
 366     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type :=
 367         (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 368          sign_extend => '0', update => '0', xerc => xerc_init,
 369          reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 370          nia => (others => '0'), insn => (others => '0'),
 371          instr_tag => instr_tag_init,
 372          addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'),
 373          write_reg => (others => '0'),
 374          length => (others => '0'),
 375          mode_32bit => '0', is_32bit => '0',
 376          repeat => '0', second => '0');
 377
 378     type Loadstore1ToExecute1Type is record
 379         busy : std_ulogic;
 380         exception : std_ulogic;
 381         alignment : std_ulogic;
 382         invalid : std_ulogic;
 383         perm_error : std_ulogic;
 384         rc_error : std_ulogic;
 385         badtree : std_ulogic;
 386         segment_fault : std_ulogic;
 387         instr_fault : std_ulogic;
 388     end record;
 389
 390     type Loadstore1ToDcacheType is record
 391         valid : std_ulogic;
 392         load : std_ulogic;                              -- is this a load
 393         dcbz : std_ulogic;
 394         nc : std_ulogic;
 395         reserve : std_ulogic;
 396         atomic : std_ulogic;                            -- part of a multi-transfer atomic op
 397         atomic_last : std_ulogic;
 398         virt_mode : std_ulogic;
 399         priv_mode : std_ulogic;
 400         addr : std_ulogic_vector(63 downto 0);
 401         data : std_ulogic_vector(63 downto 0);          -- valid the cycle after .valid = 1
 402         byte_sel : std_ulogic_vector(7 downto 0);
 403     end record;
 404
 405     type DcacheToLoadstore1Type is record
 406         valid : std_ulogic;
 407         data : std_ulogic_vector(63 downto 0);
 408         store_done : std_ulogic;
 409         error : std_ulogic;
 410         cache_paradox : std_ulogic;
 411     end record;
 412
 413     type Loadstore1ToMmuType is record
 414         valid : std_ulogic;
 415         tlbie : std_ulogic;
 416         slbia : std_ulogic;
 417         mtspr : std_ulogic;
 418         iside : std_ulogic;
 419         load  : std_ulogic;
 420         priv  : std_ulogic;
 421         sprn  : std_ulogic_vector(9 downto 0);
 422         addr  : std_ulogic_vector(63 downto 0);
 423         rs    : std_ulogic_vector(63 downto 0);
 424     end record;
 425
 426     type MmuToLoadstore1Type is record
 427         done       : std_ulogic;
 428         err        : std_ulogic;
 429         invalid    : std_ulogic;
 430         badtree    : std_ulogic;
 431         segerr     : std_ulogic;
 432         perm_error : std_ulogic;
 433         rc_error   : std_ulogic;
 434         sprval     : std_ulogic_vector(63 downto 0);
 435     end record;
 436
 437     type MmuToDcacheType is record
 438         valid : std_ulogic;
 439         tlbie : std_ulogic;
 440         doall : std_ulogic;
 441         tlbld : std_ulogic;
 442         addr  : std_ulogic_vector(63 downto 0);
 443         pte   : std_ulogic_vector(63 downto 0);
 444     end record;
 445
 446     type DcacheToMmuType is record
 447         stall : std_ulogic;
 448         done  : std_ulogic;
 449         err   : std_ulogic;
 450         data  : std_ulogic_vector(63 downto 0);
 451     end record;
 452
 453     type MmuToIcacheType is record
 454         tlbld : std_ulogic;
 455         tlbie : std_ulogic;
 456         doall : std_ulogic;
 457         addr  : std_ulogic_vector(63 downto 0);
 458         pte   : std_ulogic_vector(63 downto 0);
 459     end record;
 460
 461     type Loadstore1ToWritebackType is record
 462         valid : std_ulogic;
 463         instr_tag : instr_tag_t;
 464         write_enable: std_ulogic;
 465         write_reg : gspr_index_t;
 466         write_data : std_ulogic_vector(63 downto 0);
 467         xerc : xer_common_t;
 468         rc : std_ulogic;
 469         store_done : std_ulogic;
 470     end record;
 471     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType :=
 472         (valid => '0', instr_tag => instr_tag_init, write_enable => '0', xerc => xerc_init,
 473          rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
 474
 475     type Execute1ToWritebackType is record
 476         valid: std_ulogic;
 477         instr_tag : instr_tag_t;
 478         rc : std_ulogic;
 479         mode_32bit : std_ulogic;
 480         write_enable : std_ulogic;
 481         write_reg: gspr_index_t;
 482         write_data: std_ulogic_vector(63 downto 0);
 483         write_cr_enable : std_ulogic;
 484         write_cr_mask : std_ulogic_vector(7 downto 0);
 485         write_cr_data : std_ulogic_vector(31 downto 0);
 486         write_xerc_enable : std_ulogic;
 487         xerc : xer_common_t;
 488         exc_write_enable : std_ulogic;
 489         exc_write_reg : gspr_index_t;
 490         exc_write_data : std_ulogic_vector(63 downto 0);
 491     end record;
 492     constant Execute1ToWritebackInit : Execute1ToWritebackType :=
 493         (valid => '0', instr_tag => instr_tag_init, rc => '0', mode_32bit => '0',
 494          write_enable => '0', write_cr_enable => '0', exc_write_enable => '0',
 495          write_xerc_enable => '0', xerc => xerc_init,
 496          write_data => (others => '0'), write_cr_mask => (others => '0'),
 497          write_cr_data => (others => '0'), write_reg => (others => '0'),
 498          exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
 499
 500     type Execute1ToFPUType is record
 501         valid   : std_ulogic;
 502         op      : insn_type_t;
 503         nia     : std_ulogic_vector(63 downto 0);
 504         itag    : instr_tag_t;
 505         insn    : std_ulogic_vector(31 downto 0);
 506         single  : std_ulogic;
 507         fe_mode : std_ulogic_vector(1 downto 0);
 508         fra     : std_ulogic_vector(63 downto 0);
 509         frb     : std_ulogic_vector(63 downto 0);
 510         frc     : std_ulogic_vector(63 downto 0);
 511         frt     : gspr_index_t;
 512         rc      : std_ulogic;
 513         out_cr  : std_ulogic;
 514     end record;
 515     constant Execute1ToFPUInit : Execute1ToFPUType := (valid => '0', op => OP_ILLEGAL, nia => (others => '0'),
 516                                                        itag => instr_tag_init,
 517                                                        insn  => (others => '0'), fe_mode => "00", rc => '0',
 518                                                        fra => (others => '0'), frb => (others => '0'),
 519                                                        frc => (others => '0'), frt => (others => '0'),
 520                                                        single => '0', out_cr => '0');
 521
 522     type FPUToExecute1Type is record
 523         busy      : std_ulogic;
 524         exception : std_ulogic;
 525         interrupt : std_ulogic;
 526         illegal   : std_ulogic;
 527     end record;
 528     constant FPUToExecute1Init : FPUToExecute1Type := (others => '0');
 529
 530     type FPUToWritebackType is record
 531         valid           : std_ulogic;
 532         instr_tag       : instr_tag_t;
 533         write_enable    : std_ulogic;
 534         write_reg       : gspr_index_t;
 535         write_data      : std_ulogic_vector(63 downto 0);
 536         write_cr_enable : std_ulogic;
 537         write_cr_mask   : std_ulogic_vector(7 downto 0);
 538         write_cr_data   : std_ulogic_vector(31 downto 0);
 539     end record;
 540     constant FPUToWritebackInit : FPUToWritebackType :=  (valid => '0', instr_tag => instr_tag_init,
 541                                                           write_enable => '0', write_cr_enable => '0',
 542                                                           others => (others => '0'));
 543
 544     type DividerToExecute1Type is record
 545         valid: std_ulogic;
 546         write_reg_data: std_ulogic_vector(63 downto 0);
 547         overflow : std_ulogic;
 548     end record;
 549     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 550                                                                others => (others => '0'));
 551
 552     type WritebackToRegisterFileType is record
 553         write_reg : gspr_index_t;
 554         write_data : std_ulogic_vector(63 downto 0);
 555         write_enable : std_ulogic;
 556     end record;
 557     constant WritebackToRegisterFileInit : WritebackToRegisterFileType :=
 558         (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
 559
 560     type WritebackToCrFileType is record
 561         write_cr_enable : std_ulogic;
 562         write_cr_mask : std_ulogic_vector(7 downto 0);
 563         write_cr_data : std_ulogic_vector(31 downto 0);
 564         write_xerc_enable : std_ulogic;
 565         write_xerc_data : xer_common_t;
 566     end record;
 567     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 568                                                                write_xerc_data => xerc_init,
 569                                                                write_cr_mask => (others => '0'),
 570                                                                write_cr_data => (others => '0'));
 571
 572 end common;
 573
 574 package body common is
 575     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 576     begin
 577         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 578     end;
 579     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 580        variable n : integer range 0 to 31;
 581        -- tmp variable introduced as workaround for VCS compilation
 582        -- simulation was failing with subtype constraint mismatch error
 583        -- see GitHub PR #173
 584        variable tmp : std_ulogic_vector(4 downto 0);
 585     begin
 586        case spr is
 587        when SPR_LR =>
 588            n := 0;              -- N.B. decode2 relies on this specific value
 589        when SPR_CTR =>
 590            n := 1;              -- N.B. decode2 relies on this specific value
 591        when SPR_SRR0 =>
 592            n := 2;
 593        when SPR_SRR1 =>
 594            n := 3;
 595        when SPR_HSRR0 =>
 596            n := 4;
 597        when SPR_HSRR1 =>
 598            n := 5;
 599        when SPR_SPRG0 =>
 600            n := 6;
 601        when SPR_SPRG1 =>
 602            n := 7;
 603        when SPR_SPRG2 =>
 604            n := 8;
 605        when SPR_SPRG3 | SPR_SPRG3U =>
 606            n := 9;
 607        when SPR_HSPRG0 =>
 608            n := 10;
 609        when SPR_HSPRG1 =>
 610            n := 11;
 611        when SPR_XER =>
 612            n := 12;
 613        when SPR_TAR =>
 614            n := 13;
 615        when others =>
 616            n := 0;
 617            return "0000000";
 618        end case;
 619        tmp := std_ulogic_vector(to_unsigned(n, 5));
 620        return "01" & tmp;
 621     end;
 622
 623     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 624     begin
 625         return i(4 downto 0);
 626     end;
 627
 628     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 629     begin
 630         return "00" & i;
 631     end;
 632
 633     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 634     begin
 635         if s(5) = '1' then
 636             return s;
 637         else
 638             return gpr_to_gspr(g);
 639         end if;
 640     end;
 641
 642     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 643     begin
 644         return s(5);
 645     end;
 646
 647     function fpr_to_gspr(f: fpr_index_t) return gspr_index_t is
 648     begin
 649         return "10" & f;
 650     end;
 651
 652     function tag_match(tag1 : instr_tag_t; tag2 : instr_tag_t) return boolean is
 653     begin
 654         return tag1.valid = '1' and tag2.valid = '1' and tag1.tag = tag2.tag;
 655     end;
 656 end common;