2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 use work.decode_types.all;
10 -- Processor Version Number
11 constant PVR_MICROWATT : std_ulogic_vector(31 downto 0) := x"00630000";
14 constant MSR_SF : integer := (63 - 0); -- Sixty-Four bit mode
15 constant MSR_EE : integer := (63 - 48); -- External interrupt Enable
16 constant MSR_PR : integer := (63 - 49); -- PRoblem state
17 constant MSR_FP : integer := (63 - 50); -- Floating Point available
18 constant MSR_FE0 : integer := (63 - 52); -- Floating Exception mode
19 constant MSR_SE : integer := (63 - 53); -- Single-step bit of TE field
20 constant MSR_BE : integer := (63 - 54); -- Branch trace bit of TE field
21 constant MSR_FE1 : integer := (63 - 55); -- Floating Exception mode
22 constant MSR_IR : integer := (63 - 58); -- Instruction Relocation
23 constant MSR_DR : integer := (63 - 59); -- Data Relocation
24 constant MSR_RI : integer := (63 - 62); -- Recoverable Interrupt
25 constant MSR_LE : integer := (63 - 63); -- Little Endian
28 subtype spr_num_t is integer range 0 to 1023;
30 function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
32 constant SPR_XER : spr_num_t := 1;
33 constant SPR_LR : spr_num_t := 8;
34 constant SPR_CTR : spr_num_t := 9;
35 constant SPR_TAR : spr_num_t := 815;
36 constant SPR_DSISR : spr_num_t := 18;
37 constant SPR_DAR : spr_num_t := 19;
38 constant SPR_TB : spr_num_t := 268;
39 constant SPR_TBU : spr_num_t := 269;
40 constant SPR_DEC : spr_num_t := 22;
41 constant SPR_SRR0 : spr_num_t := 26;
42 constant SPR_SRR1 : spr_num_t := 27;
43 constant SPR_CFAR : spr_num_t := 28;
44 constant SPR_HSRR0 : spr_num_t := 314;
45 constant SPR_HSRR1 : spr_num_t := 315;
46 constant SPR_SPRG0 : spr_num_t := 272;
47 constant SPR_SPRG1 : spr_num_t := 273;
48 constant SPR_SPRG2 : spr_num_t := 274;
49 constant SPR_SPRG3 : spr_num_t := 275;
50 constant SPR_SPRG3U : spr_num_t := 259;
51 constant SPR_HSPRG0 : spr_num_t := 304;
52 constant SPR_HSPRG1 : spr_num_t := 305;
53 constant SPR_PID : spr_num_t := 48;
54 constant SPR_PRTBL : spr_num_t := 720;
55 constant SPR_PVR : spr_num_t := 287;
57 -- GPR indices in the register file (GPR only)
58 subtype gpr_index_t is std_ulogic_vector(4 downto 0);
60 -- Extended GPR index (can hold an SPR or a FPR)
61 subtype gspr_index_t is std_ulogic_vector(6 downto 0);
64 subtype fpr_index_t is std_ulogic_vector(4 downto 0);
66 -- Some SPRs are stored in the register file, they use the magic
67 -- GPR numbers above 31.
69 -- The function fast_spr_num() returns the corresponding fast
70 -- pseudo-GPR number for a given SPR number. The result MSB
71 -- indicates if this is indeed a fast SPR. If clear, then
72 -- the SPR is not stored in the GPR file.
74 -- FPRs are also stored in the register file, using GSPR
75 -- numbers from 64 to 95.
77 function fast_spr_num(spr: spr_num_t) return gspr_index_t;
79 -- Indices conversion functions
80 function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
81 function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
82 function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
83 function is_fast_spr(s: gspr_index_t) return std_ulogic;
84 function fpr_to_gspr(f: fpr_index_t) return gspr_index_t;
86 -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
87 -- in the CR file as a kind of CR extension (with a separate write
88 -- control). The rest is stored as a fast SPR.
89 type xer_common_t is record
96 constant xerc_init : xer_common_t := (others => '0');
99 constant FPSCR_FX : integer := 63 - 32;
100 constant FPSCR_FEX : integer := 63 - 33;
101 constant FPSCR_VX : integer := 63 - 34;
102 constant FPSCR_OX : integer := 63 - 35;
103 constant FPSCR_UX : integer := 63 - 36;
104 constant FPSCR_ZX : integer := 63 - 37;
105 constant FPSCR_XX : integer := 63 - 38;
106 constant FPSCR_VXSNAN : integer := 63 - 39;
107 constant FPSCR_VXISI : integer := 63 - 40;
108 constant FPSCR_VXIDI : integer := 63 - 41;
109 constant FPSCR_VXZDZ : integer := 63 - 42;
110 constant FPSCR_VXIMZ : integer := 63 - 43;
111 constant FPSCR_VXVC : integer := 63 - 44;
112 constant FPSCR_FR : integer := 63 - 45;
113 constant FPSCR_FI : integer := 63 - 46;
114 constant FPSCR_C : integer := 63 - 47;
115 constant FPSCR_FL : integer := 63 - 48;
116 constant FPSCR_FG : integer := 63 - 49;
117 constant FPSCR_FE : integer := 63 - 50;
118 constant FPSCR_FU : integer := 63 - 51;
119 constant FPSCR_VXSOFT : integer := 63 - 53;
120 constant FPSCR_VXSQRT : integer := 63 - 54;
121 constant FPSCR_VXCVI : integer := 63 - 55;
122 constant FPSCR_VE : integer := 63 - 56;
123 constant FPSCR_OE : integer := 63 - 57;
124 constant FPSCR_UE : integer := 63 - 58;
125 constant FPSCR_ZE : integer := 63 - 59;
126 constant FPSCR_XE : integer := 63 - 60;
127 constant FPSCR_NI : integer := 63 - 61;
128 constant FPSCR_RN : integer := 63 - 63;
130 -- Used for tracking instruction completion and pending register writes
131 constant TAG_COUNT : positive := 4;
132 constant TAG_NUMBER_BITS : natural := log2(TAG_COUNT);
133 subtype tag_number_t is integer range 0 to TAG_COUNT - 1;
134 subtype tag_index_t is unsigned(TAG_NUMBER_BITS - 1 downto 0);
135 type instr_tag_t is record
139 constant instr_tag_init : instr_tag_t := (tag => 0, valid => '0');
140 function tag_match(tag1 : instr_tag_t; tag2 : instr_tag_t) return boolean;
142 -- For now, fixed 16 sources, make this either a parametric
143 -- package of some sort or an unconstrainted array.
144 type ics_to_icp_t is record
145 -- Level interrupts only, ICS just keeps prsenting the
146 -- highest priority interrupt. Once handling edge, something
147 -- smarter involving handshake & reject support will be needed
148 src : std_ulogic_vector(3 downto 0);
149 pri : std_ulogic_vector(7 downto 0);
152 -- This needs to die...
153 type ctrl_t is record
154 tb: std_ulogic_vector(63 downto 0);
155 dec: std_ulogic_vector(63 downto 0);
156 msr: std_ulogic_vector(63 downto 0);
157 cfar: std_ulogic_vector(63 downto 0);
160 type Fetch1ToIcacheType is record
162 virt_mode : std_ulogic;
163 priv_mode : std_ulogic;
164 big_endian : std_ulogic;
165 stop_mark: std_ulogic;
166 sequential: std_ulogic;
167 predicted : std_ulogic;
168 nia: std_ulogic_vector(63 downto 0);
171 type IcacheToDecode1Type is record
173 stop_mark: std_ulogic;
174 fetch_failed: std_ulogic;
175 nia: std_ulogic_vector(63 downto 0);
176 insn: std_ulogic_vector(31 downto 0);
177 big_endian: std_ulogic;
178 next_predicted: std_ulogic;
181 type Decode1ToDecode2Type is record
183 stop_mark : std_ulogic;
184 nia: std_ulogic_vector(63 downto 0);
185 insn: std_ulogic_vector(31 downto 0);
186 ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
187 ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
188 ispro: gspr_index_t; -- (G)SPR written with LR or CTR
189 decode: decode_rom_t;
190 br_pred: std_ulogic; -- Branch was predicted to be taken
191 big_endian: std_ulogic;
193 constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
194 (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
195 ispr1 => (others => '0'), ispr2 => (others => '0'), ispro => (others => '0'),
196 decode => decode_rom_init, br_pred => '0', big_endian => '0');
198 type Decode1ToFetch1Type is record
199 redirect : std_ulogic;
200 redirect_nia : std_ulogic_vector(63 downto 0);
203 type bypass_data_t is record
205 data : std_ulogic_vector(63 downto 0);
207 constant bypass_data_init : bypass_data_t := (tag => instr_tag_init, data => (others => '0'));
209 type cr_bypass_data_t is record
211 data : std_ulogic_vector(31 downto 0);
213 constant cr_bypass_data_init : cr_bypass_data_t := (tag => instr_tag_init, data => (others => '0'));
215 type Decode2ToExecute1Type is record
219 insn_type: insn_type_t;
220 nia: std_ulogic_vector(63 downto 0);
221 instr_tag : instr_tag_t;
222 write_reg: gspr_index_t;
223 write_reg_enable: std_ulogic;
224 read_reg1: gspr_index_t;
225 read_reg2: gspr_index_t;
226 read_data1: std_ulogic_vector(63 downto 0);
227 read_data2: std_ulogic_vector(63 downto 0);
228 read_data3: std_ulogic_vector(63 downto 0);
229 cr: std_ulogic_vector(31 downto 0);
235 invert_a: std_ulogic;
237 invert_out: std_ulogic;
238 input_carry: carry_in_t;
239 output_carry: std_ulogic;
240 input_cr: std_ulogic;
241 output_cr: std_ulogic;
242 output_xer: std_ulogic;
243 is_32bit: std_ulogic;
244 is_signed: std_ulogic;
245 insn: std_ulogic_vector(31 downto 0);
246 data_len: std_ulogic_vector(3 downto 0);
247 byte_reverse : std_ulogic;
248 sign_extend : std_ulogic; -- do we need to sign extend?
249 update : std_ulogic; -- is this an update instruction?
250 reserve : std_ulogic; -- set for larx/stcx
251 br_pred : std_ulogic;
252 result_sel : std_ulogic_vector(2 downto 0); -- select source of result
253 sub_select : std_ulogic_vector(2 downto 0); -- sub-result selection
254 repeat : std_ulogic; -- set if instruction is cracked into two ops
255 second : std_ulogic; -- set if this is the second op
257 constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
258 (valid => '0', unit => NONE, fac => NONE, insn_type => OP_ILLEGAL, instr_tag => instr_tag_init,
259 write_reg_enable => '0',
260 lr => '0', br_abs => '0', rc => '0', oe => '0', invert_a => '0', addm1 => '0',
261 invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0',
262 output_cr => '0', output_xer => '0',
263 is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
264 byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'),
265 read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'),
266 cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'),
267 result_sel => "000", sub_select => "000",
268 repeat => '0', second => '0', others => (others => '0'));
270 type MultiplyInputType is record
272 data1: std_ulogic_vector(63 downto 0);
273 data2: std_ulogic_vector(63 downto 0);
274 addend: std_ulogic_vector(127 downto 0);
275 is_32bit: std_ulogic;
276 not_result: std_ulogic;
278 constant MultiplyInputInit : MultiplyInputType := (valid => '0',
279 is_32bit => '0', not_result => '0',
280 others => (others => '0'));
282 type MultiplyOutputType is record
284 result: std_ulogic_vector(127 downto 0);
285 overflow : std_ulogic;
287 constant MultiplyOutputInit : MultiplyOutputType := (valid => '0', overflow => '0',
288 others => (others => '0'));
290 type Execute1ToDividerType is record
292 dividend: std_ulogic_vector(63 downto 0);
293 divisor: std_ulogic_vector(63 downto 0);
294 is_signed: std_ulogic;
295 is_32bit: std_ulogic;
296 is_extended: std_ulogic;
297 is_modulus: std_ulogic;
298 neg_result: std_ulogic;
300 constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
301 is_extended => '0', is_modulus => '0',
302 neg_result => '0', others => (others => '0'));
304 type Decode2ToRegisterFileType is record
305 read1_enable : std_ulogic;
306 read1_reg : gspr_index_t;
307 read2_enable : std_ulogic;
308 read2_reg : gspr_index_t;
309 read3_enable : std_ulogic;
310 read3_reg : gspr_index_t;
313 type RegisterFileToDecode2Type is record
314 read1_data : std_ulogic_vector(63 downto 0);
315 read2_data : std_ulogic_vector(63 downto 0);
316 read3_data : std_ulogic_vector(63 downto 0);
319 type Decode2ToCrFileType is record
323 type CrFileToDecode2Type is record
324 read_cr_data : std_ulogic_vector(31 downto 0);
325 read_xerc_data : xer_common_t;
328 type Execute1ToLoadstore1Type is record
330 op : insn_type_t; -- what ld/st or m[tf]spr or TLB op to do
331 nia : std_ulogic_vector(63 downto 0);
332 insn : std_ulogic_vector(31 downto 0);
333 instr_tag : instr_tag_t;
334 addr1 : std_ulogic_vector(63 downto 0);
335 addr2 : std_ulogic_vector(63 downto 0);
336 data : std_ulogic_vector(63 downto 0); -- data to write, unused for read
337 write_reg : gspr_index_t;
338 length : std_ulogic_vector(3 downto 0);
339 ci : std_ulogic; -- cache-inhibited load/store
340 byte_reverse : std_ulogic;
341 sign_extend : std_ulogic; -- do we need to sign extend?
342 update : std_ulogic; -- is this an update instruction?
344 reserve : std_ulogic; -- set for larx/stcx.
345 rc : std_ulogic; -- set for stcx.
346 virt_mode : std_ulogic; -- do translation through TLB
347 priv_mode : std_ulogic; -- privileged mode (MSR[PR] = 0)
348 mode_32bit : std_ulogic; -- trim addresses to 32 bits
349 is_32bit : std_ulogic;
353 constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type :=
354 (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
355 sign_extend => '0', update => '0', xerc => xerc_init,
356 reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
357 nia => (others => '0'), insn => (others => '0'),
358 instr_tag => instr_tag_init,
359 addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'),
360 write_reg => (others => '0'),
361 length => (others => '0'),
362 mode_32bit => '0', is_32bit => '0',
363 repeat => '0', second => '0');
365 type Loadstore1ToExecute1Type is record
367 exception : std_ulogic;
368 alignment : std_ulogic;
369 invalid : std_ulogic;
370 perm_error : std_ulogic;
371 rc_error : std_ulogic;
372 badtree : std_ulogic;
373 segment_fault : std_ulogic;
374 instr_fault : std_ulogic;
377 type Loadstore1ToDcacheType is record
379 load : std_ulogic; -- is this a load
382 reserve : std_ulogic;
383 atomic : std_ulogic; -- part of a multi-transfer atomic op
384 atomic_last : std_ulogic;
385 virt_mode : std_ulogic;
386 priv_mode : std_ulogic;
387 addr : std_ulogic_vector(63 downto 0);
388 data : std_ulogic_vector(63 downto 0); -- valid the cycle after .valid = 1
389 byte_sel : std_ulogic_vector(7 downto 0);
392 type DcacheToLoadstore1Type is record
394 data : std_ulogic_vector(63 downto 0);
395 store_done : std_ulogic;
397 cache_paradox : std_ulogic;
400 type Loadstore1ToMmuType is record
408 sprn : std_ulogic_vector(9 downto 0);
409 addr : std_ulogic_vector(63 downto 0);
410 rs : std_ulogic_vector(63 downto 0);
413 type MmuToLoadstore1Type is record
416 invalid : std_ulogic;
417 badtree : std_ulogic;
419 perm_error : std_ulogic;
420 rc_error : std_ulogic;
421 sprval : std_ulogic_vector(63 downto 0);
424 type MmuToDcacheType is record
429 addr : std_ulogic_vector(63 downto 0);
430 pte : std_ulogic_vector(63 downto 0);
433 type DcacheToMmuType is record
437 data : std_ulogic_vector(63 downto 0);
440 type MmuToIcacheType is record
444 addr : std_ulogic_vector(63 downto 0);
445 pte : std_ulogic_vector(63 downto 0);
448 type Loadstore1ToWritebackType is record
450 instr_tag : instr_tag_t;
451 write_enable: std_ulogic;
452 write_reg : gspr_index_t;
453 write_data : std_ulogic_vector(63 downto 0);
456 store_done : std_ulogic;
458 constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType :=
459 (valid => '0', instr_tag => instr_tag_init, write_enable => '0', xerc => xerc_init,
460 rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
462 type Execute1ToWritebackType is record
464 instr_tag : instr_tag_t;
466 mode_32bit : std_ulogic;
467 write_enable : std_ulogic;
468 write_reg: gspr_index_t;
469 write_data: std_ulogic_vector(63 downto 0);
470 write_cr_enable : std_ulogic;
471 write_cr_mask : std_ulogic_vector(7 downto 0);
472 write_cr_data : std_ulogic_vector(31 downto 0);
473 write_xerc_enable : std_ulogic;
475 interrupt : std_ulogic;
476 intr_vec : integer range 0 to 16#fff#;
477 redirect: std_ulogic;
478 redir_mode: std_ulogic_vector(3 downto 0);
479 last_nia: std_ulogic_vector(63 downto 0);
480 br_offset: std_ulogic_vector(63 downto 0);
482 br_taken: std_ulogic;
484 srr1: std_ulogic_vector(63 downto 0);
486 constant Execute1ToWritebackInit : Execute1ToWritebackType :=
487 (valid => '0', instr_tag => instr_tag_init, rc => '0', mode_32bit => '0',
488 write_enable => '0', write_cr_enable => '0',
489 write_xerc_enable => '0', xerc => xerc_init,
490 write_data => (others => '0'), write_cr_mask => (others => '0'),
491 write_cr_data => (others => '0'), write_reg => (others => '0'),
492 interrupt => '0', intr_vec => 0, redirect => '0', redir_mode => "0000",
493 last_nia => (others => '0'), br_offset => (others => '0'),
494 br_last => '0', br_taken => '0', abs_br => '0', srr1 => (others => '0'));
496 type Execute1ToFPUType is record
499 nia : std_ulogic_vector(63 downto 0);
501 insn : std_ulogic_vector(31 downto 0);
503 fe_mode : std_ulogic_vector(1 downto 0);
504 fra : std_ulogic_vector(63 downto 0);
505 frb : std_ulogic_vector(63 downto 0);
506 frc : std_ulogic_vector(63 downto 0);
511 constant Execute1ToFPUInit : Execute1ToFPUType := (valid => '0', op => OP_ILLEGAL, nia => (others => '0'),
512 itag => instr_tag_init,
513 insn => (others => '0'), fe_mode => "00", rc => '0',
514 fra => (others => '0'), frb => (others => '0'),
515 frc => (others => '0'), frt => (others => '0'),
516 single => '0', out_cr => '0');
518 type FPUToExecute1Type is record
520 exception : std_ulogic;
521 interrupt : std_ulogic;
522 illegal : std_ulogic;
524 constant FPUToExecute1Init : FPUToExecute1Type := (others => '0');
526 type FPUToWritebackType is record
528 instr_tag : instr_tag_t;
529 write_enable : std_ulogic;
530 write_reg : gspr_index_t;
531 write_data : std_ulogic_vector(63 downto 0);
532 write_cr_enable : std_ulogic;
533 write_cr_mask : std_ulogic_vector(7 downto 0);
534 write_cr_data : std_ulogic_vector(31 downto 0);
536 constant FPUToWritebackInit : FPUToWritebackType := (valid => '0', instr_tag => instr_tag_init,
537 write_enable => '0', write_cr_enable => '0',
538 others => (others => '0'));
540 type DividerToExecute1Type is record
542 write_reg_data: std_ulogic_vector(63 downto 0);
543 overflow : std_ulogic;
545 constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
546 others => (others => '0'));
548 type WritebackToFetch1Type is record
549 redirect: std_ulogic;
550 virt_mode: std_ulogic;
551 priv_mode: std_ulogic;
552 big_endian: std_ulogic;
553 mode_32bit: std_ulogic;
554 redirect_nia: std_ulogic_vector(63 downto 0);
555 br_nia : std_ulogic_vector(63 downto 0);
556 br_last : std_ulogic;
557 br_taken : std_ulogic;
559 constant WritebackToFetch1Init : WritebackToFetch1Type :=
560 (redirect => '0', virt_mode => '0', priv_mode => '0', big_endian => '0',
561 mode_32bit => '0', redirect_nia => (others => '0'),
562 br_last => '0', br_taken => '0', br_nia => (others => '0'));
564 type WritebackToRegisterFileType is record
565 write_reg : gspr_index_t;
566 write_data : std_ulogic_vector(63 downto 0);
567 write_enable : std_ulogic;
569 constant WritebackToRegisterFileInit : WritebackToRegisterFileType :=
570 (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
572 type WritebackToCrFileType is record
573 write_cr_enable : std_ulogic;
574 write_cr_mask : std_ulogic_vector(7 downto 0);
575 write_cr_data : std_ulogic_vector(31 downto 0);
576 write_xerc_enable : std_ulogic;
577 write_xerc_data : xer_common_t;
579 constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
580 write_xerc_data => xerc_init,
581 write_cr_mask => (others => '0'),
582 write_cr_data => (others => '0'));
586 package body common is
587 function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
589 return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
591 function fast_spr_num(spr: spr_num_t) return gspr_index_t is
592 variable n : integer range 0 to 31;
593 -- tmp variable introduced as workaround for VCS compilation
594 -- simulation was failing with subtype constraint mismatch error
595 -- see GitHub PR #173
596 variable tmp : std_ulogic_vector(4 downto 0);
600 n := 0; -- N.B. decode2 relies on this specific value
602 n := 1; -- N.B. decode2 relies on this specific value
617 when SPR_SPRG3 | SPR_SPRG3U =>
631 tmp := std_ulogic_vector(to_unsigned(n, 5));
635 function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
637 return i(4 downto 0);
640 function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
645 function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
650 return gpr_to_gspr(g);
654 function is_fast_spr(s: gspr_index_t) return std_ulogic is
659 function fpr_to_gspr(f: fpr_index_t) return gspr_index_t is
664 function tag_match(tag1 : instr_tag_t; tag2 : instr_tag_t) return boolean is
666 return tag1.valid = '1' and tag2.valid = '1' and tag1.tag = tag2.tag;