common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9     -- Processor Version Number
  10     constant PVR_MICROWATT  : std_ulogic_vector(31 downto 0) := x"00630000";
  11
  12     -- MSR bit numbers
  13     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  14     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  15     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  16     constant MSR_FP  : integer := (63 - 50);    -- Floating Point available
  17     constant MSR_FE0 : integer := (63 - 52);    -- Floating Exception mode
  18     constant MSR_SE  : integer := (63 - 53);    -- Single-step bit of TE field
  19     constant MSR_BE  : integer := (63 - 54);    -- Branch trace bit of TE field
  20     constant MSR_FE1 : integer := (63 - 55);    -- Floating Exception mode
  21     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  22     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  23     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  24     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  25
  26     -- SPR numbers
  27     subtype spr_num_t is integer range 0 to 1023;
  28
  29     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  30
  31     constant SPR_XER    : spr_num_t := 1;
  32     constant SPR_LR     : spr_num_t := 8;
  33     constant SPR_CTR    : spr_num_t := 9;
  34     constant SPR_TAR    : spr_num_t := 815;
  35     constant SPR_DSISR  : spr_num_t := 18;
  36     constant SPR_DAR    : spr_num_t := 19;
  37     constant SPR_TB     : spr_num_t := 268;
  38     constant SPR_TBU    : spr_num_t := 269;
  39     constant SPR_DEC    : spr_num_t := 22;
  40     constant SPR_SRR0   : spr_num_t := 26;
  41     constant SPR_SRR1   : spr_num_t := 27;
  42     constant SPR_CFAR   : spr_num_t := 28;
  43     constant SPR_HSRR0  : spr_num_t := 314;
  44     constant SPR_HSRR1  : spr_num_t := 315;
  45     constant SPR_SPRG0  : spr_num_t := 272;
  46     constant SPR_SPRG1  : spr_num_t := 273;
  47     constant SPR_SPRG2  : spr_num_t := 274;
  48     constant SPR_SPRG3  : spr_num_t := 275;
  49     constant SPR_SPRG3U : spr_num_t := 259;
  50     constant SPR_HSPRG0 : spr_num_t := 304;
  51     constant SPR_HSPRG1 : spr_num_t := 305;
  52     constant SPR_PID    : spr_num_t := 48;
  53     constant SPR_PRTBL  : spr_num_t := 720;
  54     constant SPR_PVR    : spr_num_t := 287;
  55
  56     -- GPR indices in the register file (GPR only)
  57     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  58
  59     -- Extended GPR index (can hold an SPR or a FPR)
  60     subtype gspr_index_t is std_ulogic_vector(6 downto 0);
  61
  62     -- FPR indices
  63     subtype fpr_index_t is std_ulogic_vector(4 downto 0);
  64
  65     -- Some SPRs are stored in the register file, they use the magic
  66     -- GPR numbers above 31.
  67     --
  68     -- The function fast_spr_num() returns the corresponding fast
  69     -- pseudo-GPR number for a given SPR number. The result MSB
  70     -- indicates if this is indeed a fast SPR. If clear, then
  71     -- the SPR is not stored in the GPR file.
  72     --
  73     -- FPRs are also stored in the register file, using GSPR
  74     -- numbers from 64 to 95.
  75     --
  76     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  77
  78     -- Indices conversion functions
  79     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  80     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  81     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  82     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  83     function fpr_to_gspr(f: fpr_index_t) return gspr_index_t;
  84
  85     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  86     -- in the CR file as a kind of CR extension (with a separate write
  87     -- control). The rest is stored as a fast SPR.
  88     type xer_common_t is record
  89         ca : std_ulogic;
  90         ca32 : std_ulogic;
  91         ov : std_ulogic;
  92         ov32 : std_ulogic;
  93         so : std_ulogic;
  94     end record;
  95     constant xerc_init : xer_common_t := (others => '0');
  96
  97     -- FPSCR bit numbers
  98     constant FPSCR_FX     : integer := 63 - 32;
  99     constant FPSCR_FEX    : integer := 63 - 33;
 100     constant FPSCR_VX     : integer := 63 - 34;
 101     constant FPSCR_OX     : integer := 63 - 35;
 102     constant FPSCR_UX     : integer := 63 - 36;
 103     constant FPSCR_ZX     : integer := 63 - 37;
 104     constant FPSCR_XX     : integer := 63 - 38;
 105     constant FPSCR_VXSNAN : integer := 63 - 39;
 106     constant FPSCR_VXISI  : integer := 63 - 40;
 107     constant FPSCR_VXIDI  : integer := 63 - 41;
 108     constant FPSCR_VXZDZ  : integer := 63 - 42;
 109     constant FPSCR_VXIMZ  : integer := 63 - 43;
 110     constant FPSCR_VXVC   : integer := 63 - 44;
 111     constant FPSCR_FR     : integer := 63 - 45;
 112     constant FPSCR_FI     : integer := 63 - 46;
 113     constant FPSCR_C      : integer := 63 - 47;
 114     constant FPSCR_FL     : integer := 63 - 48;
 115     constant FPSCR_FG     : integer := 63 - 49;
 116     constant FPSCR_FE     : integer := 63 - 50;
 117     constant FPSCR_FU     : integer := 63 - 51;
 118     constant FPSCR_VXSOFT : integer := 63 - 53;
 119     constant FPSCR_VXSQRT : integer := 63 - 54;
 120     constant FPSCR_VXCVI  : integer := 63 - 55;
 121     constant FPSCR_VE     : integer := 63 - 56;
 122     constant FPSCR_OE     : integer := 63 - 57;
 123     constant FPSCR_UE     : integer := 63 - 58;
 124     constant FPSCR_ZE     : integer := 63 - 59;
 125     constant FPSCR_XE     : integer := 63 - 60;
 126     constant FPSCR_NI     : integer := 63 - 61;
 127     constant FPSCR_RN     : integer := 63 - 63;
 128
 129     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
 130
 131     -- For now, fixed 16 sources, make this either a parametric
 132     -- package of some sort or an unconstrainted array.
 133     type ics_to_icp_t is record
 134         -- Level interrupts only, ICS just keeps prsenting the
 135         -- highest priority interrupt. Once handling edge, something
 136         -- smarter involving handshake & reject support will be needed
 137         src : std_ulogic_vector(3 downto 0);
 138         pri : std_ulogic_vector(7 downto 0);
 139     end record;
 140
 141     -- This needs to die...
 142     type ctrl_t is record
 143         tb: std_ulogic_vector(63 downto 0);
 144         dec: std_ulogic_vector(63 downto 0);
 145         msr: std_ulogic_vector(63 downto 0);
 146         cfar: std_ulogic_vector(63 downto 0);
 147         irq_state : irq_state_t;
 148         srr1: std_ulogic_vector(63 downto 0);
 149     end record;
 150
 151     type Fetch1ToIcacheType is record
 152         req: std_ulogic;
 153         virt_mode : std_ulogic;
 154         priv_mode : std_ulogic;
 155         big_endian : std_ulogic;
 156         stop_mark: std_ulogic;
 157         sequential: std_ulogic;
 158         nia: std_ulogic_vector(63 downto 0);
 159     end record;
 160
 161     type IcacheToDecode1Type is record
 162         valid: std_ulogic;
 163         stop_mark: std_ulogic;
 164         fetch_failed: std_ulogic;
 165         nia: std_ulogic_vector(63 downto 0);
 166         insn: std_ulogic_vector(31 downto 0);
 167         big_endian: std_ulogic;
 168     end record;
 169
 170     type Decode1ToDecode2Type is record
 171         valid: std_ulogic;
 172         stop_mark : std_ulogic;
 173         nia: std_ulogic_vector(63 downto 0);
 174         insn: std_ulogic_vector(31 downto 0);
 175         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 176         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 177         decode: decode_rom_t;
 178         br_pred: std_ulogic; -- Branch was predicted to be taken
 179         big_endian: std_ulogic;
 180     end record;
 181     constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
 182         (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
 183          ispr1 => (others => '0'), ispr2 => (others => '0'), decode => decode_rom_init,
 184          br_pred => '0', big_endian => '0');
 185
 186     type Decode1ToFetch1Type is record
 187         redirect     : std_ulogic;
 188         redirect_nia : std_ulogic_vector(63 downto 0);
 189     end record;
 190
 191     type Decode2ToExecute1Type is record
 192         valid: std_ulogic;
 193         unit : unit_t;
 194         fac : facility_t;
 195         insn_type: insn_type_t;
 196         nia: std_ulogic_vector(63 downto 0);
 197         write_reg: gspr_index_t;
 198         read_reg1: gspr_index_t;
 199         read_reg2: gspr_index_t;
 200         read_data1: std_ulogic_vector(63 downto 0);
 201         read_data2: std_ulogic_vector(63 downto 0);
 202         read_data3: std_ulogic_vector(63 downto 0);
 203         bypass_data1: std_ulogic;
 204         bypass_data2: std_ulogic;
 205         bypass_data3: std_ulogic;
 206         cr: std_ulogic_vector(31 downto 0);
 207         bypass_cr : std_ulogic;
 208         xerc: xer_common_t;
 209         lr: std_ulogic;
 210         rc: std_ulogic;
 211         oe: std_ulogic;
 212         invert_a: std_ulogic;
 213         invert_out: std_ulogic;
 214         input_carry: carry_in_t;
 215         output_carry: std_ulogic;
 216         input_cr: std_ulogic;
 217         output_cr: std_ulogic;
 218         is_32bit: std_ulogic;
 219         is_signed: std_ulogic;
 220         insn: std_ulogic_vector(31 downto 0);
 221         data_len: std_ulogic_vector(3 downto 0);
 222         byte_reverse : std_ulogic;
 223         sign_extend : std_ulogic;                       -- do we need to sign extend?
 224         update : std_ulogic;                            -- is this an update instruction?
 225         reserve : std_ulogic;                           -- set for larx/stcx
 226         br_pred : std_ulogic;
 227         repeat : std_ulogic;                            -- set if instruction is cracked into two ops
 228         second : std_ulogic;                            -- set if this is the second op
 229     end record;
 230     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 231         (valid => '0', unit => NONE, fac => NONE, insn_type => OP_ILLEGAL,
 232          bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 233          bypass_cr => '0', lr => '0', rc => '0', oe => '0', invert_a => '0',
 234          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 235          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
 236          byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'),
 237          read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'),
 238          cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'),
 239          repeat => '0', second => '0', others => (others => '0'));
 240
 241     type MultiplyInputType is record
 242         valid: std_ulogic;
 243         data1: std_ulogic_vector(63 downto 0);
 244         data2: std_ulogic_vector(63 downto 0);
 245         addend: std_ulogic_vector(127 downto 0);
 246         is_32bit: std_ulogic;
 247         not_result: std_ulogic;
 248     end record;
 249     constant MultiplyInputInit : MultiplyInputType := (valid => '0',
 250                                                        is_32bit => '0', not_result => '0',
 251                                                        others => (others => '0'));
 252
 253     type MultiplyOutputType is record
 254         valid: std_ulogic;
 255         result: std_ulogic_vector(127 downto 0);
 256         overflow : std_ulogic;
 257     end record;
 258     constant MultiplyOutputInit : MultiplyOutputType := (valid => '0', overflow => '0',
 259                                                          others => (others => '0'));
 260
 261     type Execute1ToDividerType is record
 262         valid: std_ulogic;
 263         dividend: std_ulogic_vector(63 downto 0);
 264         divisor: std_ulogic_vector(63 downto 0);
 265         is_signed: std_ulogic;
 266         is_32bit: std_ulogic;
 267         is_extended: std_ulogic;
 268         is_modulus: std_ulogic;
 269         neg_result: std_ulogic;
 270     end record;
 271     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 272                                                               is_extended => '0', is_modulus => '0',
 273                                                               neg_result => '0', others => (others => '0'));
 274
 275     type Decode2ToRegisterFileType is record
 276         read1_enable : std_ulogic;
 277         read1_reg : gspr_index_t;
 278         read2_enable : std_ulogic;
 279         read2_reg : gspr_index_t;
 280         read3_enable : std_ulogic;
 281         read3_reg : gspr_index_t;
 282     end record;
 283
 284     type RegisterFileToDecode2Type is record
 285         read1_data : std_ulogic_vector(63 downto 0);
 286         read2_data : std_ulogic_vector(63 downto 0);
 287         read3_data : std_ulogic_vector(63 downto 0);
 288     end record;
 289
 290     type Decode2ToCrFileType is record
 291         read : std_ulogic;
 292     end record;
 293
 294     type CrFileToDecode2Type is record
 295         read_cr_data   : std_ulogic_vector(31 downto 0);
 296         read_xerc_data : xer_common_t;
 297     end record;
 298
 299     type Execute1ToFetch1Type is record
 300         redirect: std_ulogic;
 301         virt_mode: std_ulogic;
 302         priv_mode: std_ulogic;
 303         big_endian: std_ulogic;
 304         mode_32bit: std_ulogic;
 305         redirect_nia: std_ulogic_vector(63 downto 0);
 306     end record;
 307     constant Execute1ToFetch1Init : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
 308                                                              priv_mode => '0', big_endian => '0',
 309                                                              mode_32bit => '0', others => (others => '0'));
 310
 311     type Execute1ToLoadstore1Type is record
 312         valid : std_ulogic;
 313         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 314         nia : std_ulogic_vector(63 downto 0);
 315         insn : std_ulogic_vector(31 downto 0);
 316         addr1 : std_ulogic_vector(63 downto 0);
 317         addr2 : std_ulogic_vector(63 downto 0);
 318         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 319         write_reg : gspr_index_t;
 320         length : std_ulogic_vector(3 downto 0);
 321         ci : std_ulogic;                                -- cache-inhibited load/store
 322         byte_reverse : std_ulogic;
 323         sign_extend : std_ulogic;                       -- do we need to sign extend?
 324         update : std_ulogic;                            -- is this an update instruction?
 325         update_reg : gpr_index_t;                       -- if so, the register to update
 326         xerc : xer_common_t;
 327         reserve : std_ulogic;                           -- set for larx/stcx.
 328         rc : std_ulogic;                                -- set for stcx.
 329         virt_mode : std_ulogic;                         -- do translation through TLB
 330         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 331         mode_32bit : std_ulogic;                        -- trim addresses to 32 bits
 332         is_32bit : std_ulogic;
 333         repeat : std_ulogic;
 334         second : std_ulogic;
 335     end record;
 336     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 337                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 338                                                                      reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 339                                                                      nia => (others => '0'), insn => (others => '0'),
 340                                                                      addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'),
 341                                                                      write_reg => (others => '0'), length => (others => '0'),
 342                                                                      mode_32bit => '0', is_32bit => '0',
 343                                                                      repeat => '0', second => '0', others => (others => '0'));
 344
 345     type Loadstore1ToExecute1Type is record
 346         busy : std_ulogic;
 347         exception : std_ulogic;
 348         alignment : std_ulogic;
 349         invalid : std_ulogic;
 350         perm_error : std_ulogic;
 351         rc_error : std_ulogic;
 352         badtree : std_ulogic;
 353         segment_fault : std_ulogic;
 354         instr_fault : std_ulogic;
 355     end record;
 356
 357     type Loadstore1ToDcacheType is record
 358         valid : std_ulogic;
 359         load : std_ulogic;                              -- is this a load
 360         dcbz : std_ulogic;
 361         nc : std_ulogic;
 362         reserve : std_ulogic;
 363         atomic : std_ulogic;                            -- part of a multi-transfer atomic op
 364         atomic_last : std_ulogic;
 365         virt_mode : std_ulogic;
 366         priv_mode : std_ulogic;
 367         addr : std_ulogic_vector(63 downto 0);
 368         data : std_ulogic_vector(63 downto 0);
 369         byte_sel : std_ulogic_vector(7 downto 0);
 370     end record;
 371
 372     type DcacheToLoadstore1Type is record
 373         valid : std_ulogic;
 374         data : std_ulogic_vector(63 downto 0);
 375         store_done : std_ulogic;
 376         error : std_ulogic;
 377         cache_paradox : std_ulogic;
 378     end record;
 379
 380     type Loadstore1ToMmuType is record
 381         valid : std_ulogic;
 382         tlbie : std_ulogic;
 383         slbia : std_ulogic;
 384         mtspr : std_ulogic;
 385         iside : std_ulogic;
 386         load  : std_ulogic;
 387         priv  : std_ulogic;
 388         sprn  : std_ulogic_vector(9 downto 0);
 389         addr  : std_ulogic_vector(63 downto 0);
 390         rs    : std_ulogic_vector(63 downto 0);
 391     end record;
 392
 393     type MmuToLoadstore1Type is record
 394         done       : std_ulogic;
 395         err        : std_ulogic;
 396         invalid    : std_ulogic;
 397         badtree    : std_ulogic;
 398         segerr     : std_ulogic;
 399         perm_error : std_ulogic;
 400         rc_error   : std_ulogic;
 401         sprval     : std_ulogic_vector(63 downto 0);
 402     end record;
 403
 404     type MmuToDcacheType is record
 405         valid : std_ulogic;
 406         tlbie : std_ulogic;
 407         doall : std_ulogic;
 408         tlbld : std_ulogic;
 409         addr  : std_ulogic_vector(63 downto 0);
 410         pte   : std_ulogic_vector(63 downto 0);
 411     end record;
 412
 413     type DcacheToMmuType is record
 414         stall : std_ulogic;
 415         done  : std_ulogic;
 416         err   : std_ulogic;
 417         data  : std_ulogic_vector(63 downto 0);
 418     end record;
 419
 420     type MmuToIcacheType is record
 421         tlbld : std_ulogic;
 422         tlbie : std_ulogic;
 423         doall : std_ulogic;
 424         addr  : std_ulogic_vector(63 downto 0);
 425         pte   : std_ulogic_vector(63 downto 0);
 426     end record;
 427
 428     type Loadstore1ToWritebackType is record
 429         valid : std_ulogic;
 430         write_enable: std_ulogic;
 431         write_reg : gspr_index_t;
 432         write_data : std_ulogic_vector(63 downto 0);
 433         xerc : xer_common_t;
 434         rc : std_ulogic;
 435         store_done : std_ulogic;
 436     end record;
 437     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 438                                                                        rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
 439
 440     type Execute1ToWritebackType is record
 441         valid: std_ulogic;
 442         rc : std_ulogic;
 443         mode_32bit : std_ulogic;
 444         write_enable : std_ulogic;
 445         write_reg: gspr_index_t;
 446         write_data: std_ulogic_vector(63 downto 0);
 447         write_cr_enable : std_ulogic;
 448         write_cr_mask : std_ulogic_vector(7 downto 0);
 449         write_cr_data : std_ulogic_vector(31 downto 0);
 450         write_xerc_enable : std_ulogic;
 451         xerc : xer_common_t;
 452         exc_write_enable : std_ulogic;
 453         exc_write_reg : gspr_index_t;
 454         exc_write_data : std_ulogic_vector(63 downto 0);
 455     end record;
 456     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', mode_32bit => '0', write_enable => '0',
 457                                                                    write_cr_enable => '0', exc_write_enable => '0',
 458                                                                    write_xerc_enable => '0', xerc => xerc_init,
 459                                    write_data => (others => '0'), write_cr_mask => (others => '0'),
 460                                    write_cr_data => (others => '0'), write_reg => (others => '0'),
 461                                    exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
 462
 463     type Execute1ToFPUType is record
 464         valid   : std_ulogic;
 465         op      : insn_type_t;
 466         nia     : std_ulogic_vector(63 downto 0);
 467         insn    : std_ulogic_vector(31 downto 0);
 468         single  : std_ulogic;
 469         fe_mode : std_ulogic_vector(1 downto 0);
 470         fra     : std_ulogic_vector(63 downto 0);
 471         frb     : std_ulogic_vector(63 downto 0);
 472         frc     : std_ulogic_vector(63 downto 0);
 473         frt     : gspr_index_t;
 474         rc      : std_ulogic;
 475         out_cr  : std_ulogic;
 476     end record;
 477     constant Execute1ToFPUInit : Execute1ToFPUType := (valid => '0', op => OP_ILLEGAL, nia => (others => '0'),
 478                                                        insn  => (others => '0'), fe_mode => "00", rc => '0',
 479                                                        fra => (others => '0'), frb => (others => '0'),
 480                                                        frc => (others => '0'), frt => (others => '0'),
 481                                                        single => '0', out_cr => '0');
 482
 483     type FPUToExecute1Type is record
 484         busy      : std_ulogic;
 485         exception : std_ulogic;
 486         interrupt : std_ulogic;
 487         illegal   : std_ulogic;
 488     end record;
 489     constant FPUToExecute1Init : FPUToExecute1Type := (others => '0');
 490
 491     type FPUToWritebackType is record
 492         valid           : std_ulogic;
 493         write_enable    : std_ulogic;
 494         write_reg       : gspr_index_t;
 495         write_data      : std_ulogic_vector(63 downto 0);
 496         write_cr_enable : std_ulogic;
 497         write_cr_mask   : std_ulogic_vector(7 downto 0);
 498         write_cr_data   : std_ulogic_vector(31 downto 0);
 499     end record;
 500     constant FPUToWritebackInit : FPUToWritebackType :=  (valid => '0', write_enable => '0', write_cr_enable => '0', others => (others => '0'));
 501
 502     type DividerToExecute1Type is record
 503         valid: std_ulogic;
 504         write_reg_data: std_ulogic_vector(63 downto 0);
 505         overflow : std_ulogic;
 506     end record;
 507     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 508                                                                others => (others => '0'));
 509
 510     type WritebackToRegisterFileType is record
 511         write_reg : gspr_index_t;
 512         write_data : std_ulogic_vector(63 downto 0);
 513         write_enable : std_ulogic;
 514     end record;
 515     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
 516
 517     type WritebackToCrFileType is record
 518         write_cr_enable : std_ulogic;
 519         write_cr_mask : std_ulogic_vector(7 downto 0);
 520         write_cr_data : std_ulogic_vector(31 downto 0);
 521         write_xerc_enable : std_ulogic;
 522         write_xerc_data : xer_common_t;
 523     end record;
 524     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 525                                                                write_xerc_data => xerc_init,
 526                                                                write_cr_mask => (others => '0'),
 527                                                                write_cr_data => (others => '0'));
 528
 529 end common;
 530
 531 package body common is
 532     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 533     begin
 534         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 535     end;
 536     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 537        variable n : integer range 0 to 31;
 538        -- tmp variable introduced as workaround for VCS compilation
 539        -- simulation was failing with subtype constraint mismatch error
 540        -- see GitHub PR #173
 541        variable tmp : std_ulogic_vector(4 downto 0);
 542     begin
 543        case spr is
 544        when SPR_LR =>
 545            n := 0;
 546        when SPR_CTR =>
 547            n:= 1;
 548        when SPR_SRR0 =>
 549            n := 2;
 550        when SPR_SRR1 =>
 551            n := 3;
 552        when SPR_HSRR0 =>
 553            n := 4;
 554        when SPR_HSRR1 =>
 555            n := 5;
 556        when SPR_SPRG0 =>
 557            n := 6;
 558        when SPR_SPRG1 =>
 559            n := 7;
 560        when SPR_SPRG2 =>
 561            n := 8;
 562        when SPR_SPRG3 | SPR_SPRG3U =>
 563            n := 9;
 564        when SPR_HSPRG0 =>
 565            n := 10;
 566        when SPR_HSPRG1 =>
 567            n := 11;
 568        when SPR_XER =>
 569            n := 12;
 570        when SPR_TAR =>
 571            n := 13;
 572        when others =>
 573            n := 0;
 574            return "0000000";
 575        end case;
 576        tmp := std_ulogic_vector(to_unsigned(n, 5));
 577        return "01" & tmp;
 578     end;
 579
 580     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 581     begin
 582         return i(4 downto 0);
 583     end;
 584
 585     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 586     begin
 587         return "00" & i;
 588     end;
 589
 590     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 591     begin
 592         if s(5) = '1' then
 593             return s;
 594         else
 595             return gpr_to_gspr(g);
 596         end if;
 597     end;
 598
 599     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 600     begin
 601         return s(5);
 602     end;
 603
 604     function fpr_to_gspr(f: fpr_index_t) return gspr_index_t is
 605     begin
 606         return "10" & f;
 607     end;
 608 end common;