2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use work.decode_types.all;
11 subtype spr_num_t is integer range 0 to 1023;
13 function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
15 constant SPR_XER : spr_num_t := 1;
16 constant SPR_LR : spr_num_t := 8;
17 constant SPR_CTR : spr_num_t := 9;
18 constant SPR_TB : spr_num_t := 268;
19 constant SPR_SRR0 : spr_num_t := 26;
20 constant SPR_SRR1 : spr_num_t := 27;
21 constant SPR_HSRR0 : spr_num_t := 314;
22 constant SPR_HSRR1 : spr_num_t := 315;
23 constant SPR_SPRG0 : spr_num_t := 272;
24 constant SPR_SPRG1 : spr_num_t := 273;
25 constant SPR_SPRG2 : spr_num_t := 274;
26 constant SPR_SPRG3 : spr_num_t := 275;
27 constant SPR_SPRG3U : spr_num_t := 259;
28 constant SPR_HSPRG0 : spr_num_t := 304;
29 constant SPR_HSPRG1 : spr_num_t := 305;
31 -- GPR indices in the register file (GPR only)
32 subtype gpr_index_t is std_ulogic_vector(4 downto 0);
34 -- Extended GPR indice (can hold an SPR)
35 subtype gspr_index_t is std_ulogic_vector(5 downto 0);
37 -- Some SPRs are stored in the register file, they use the magic
38 -- GPR numbers above 31.
40 -- The function fast_spr_num() returns the corresponding fast
41 -- pseudo-GPR number for a given SPR number. The result MSB
42 -- indicates if this is indeed a fast SPR. If clear, then
43 -- the SPR is not stored in the GPR file.
45 function fast_spr_num(spr: spr_num_t) return gspr_index_t;
47 -- Indices conversion functions
48 function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
49 function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
50 function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
51 function is_fast_spr(s: gspr_index_t) return std_ulogic;
53 -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
54 -- in the CR file as a kind of CR extension (with a separate write
55 -- control). The rest is stored as a fast SPR.
56 type xer_common_t is record
63 constant xerc_init : xer_common_t := (others => '0');
65 -- This needs to die...
67 tb: std_ulogic_vector(63 downto 0);
70 type Fetch1ToIcacheType is record
72 stop_mark: std_ulogic;
73 nia: std_ulogic_vector(63 downto 0);
76 type IcacheToFetch2Type is record
78 stop_mark: std_ulogic;
79 nia: std_ulogic_vector(63 downto 0);
80 insn: std_ulogic_vector(31 downto 0);
83 type Fetch2ToDecode1Type is record
85 stop_mark : std_ulogic;
86 nia: std_ulogic_vector(63 downto 0);
87 insn: std_ulogic_vector(31 downto 0);
89 constant Fetch2ToDecode1Init : Fetch2ToDecode1Type := (valid => '0', stop_mark => '0', others => (others => '0'));
91 type Decode1ToDecode2Type is record
93 stop_mark : std_ulogic;
94 nia: std_ulogic_vector(63 downto 0);
95 insn: std_ulogic_vector(31 downto 0);
96 ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
97 ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
100 constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', stop_mark => '0', decode => decode_rom_init, others => (others => '0'));
102 type Decode2ToExecute1Type is record
104 insn_type: insn_type_t;
105 nia: std_ulogic_vector(63 downto 0);
106 write_reg: gspr_index_t;
107 read_reg1: gspr_index_t;
108 read_reg2: gspr_index_t;
109 read_data1: std_ulogic_vector(63 downto 0);
110 read_data2: std_ulogic_vector(63 downto 0);
111 read_data3: std_ulogic_vector(63 downto 0);
112 bypass_data1: std_ulogic;
113 bypass_data2: std_ulogic;
114 bypass_data3: std_ulogic;
115 cr: std_ulogic_vector(31 downto 0);
120 invert_a: std_ulogic;
121 invert_out: std_ulogic;
122 input_carry: carry_in_t;
123 output_carry: std_ulogic;
124 input_cr: std_ulogic;
125 output_cr: std_ulogic;
126 is_32bit: std_ulogic;
127 is_signed: std_ulogic;
128 insn: std_ulogic_vector(31 downto 0);
129 data_len: std_ulogic_vector(3 downto 0);
130 byte_reverse : std_ulogic;
131 sign_extend : std_ulogic; -- do we need to sign extend?
132 update : std_ulogic; -- is this an update instruction?
134 constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
135 (valid => '0', insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
136 lr => '0', rc => '0', oe => '0', invert_a => '0',
137 invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
138 is_32bit => '0', is_signed => '0', xerc => xerc_init,
139 byte_reverse => '0', sign_extend => '0', update => '0', others => (others => '0'));
141 type Execute1ToMultiplyType is record
143 insn_type: insn_type_t;
144 data1: std_ulogic_vector(64 downto 0);
145 data2: std_ulogic_vector(64 downto 0);
146 is_32bit: std_ulogic;
148 constant Execute1ToMultiplyInit : Execute1ToMultiplyType := (valid => '0', insn_type => OP_ILLEGAL,
150 others => (others => '0'));
152 type Execute1ToDividerType is record
154 dividend: std_ulogic_vector(63 downto 0);
155 divisor: std_ulogic_vector(63 downto 0);
156 is_signed: std_ulogic;
157 is_32bit: std_ulogic;
158 is_extended: std_ulogic;
159 is_modulus: std_ulogic;
160 neg_result: std_ulogic;
162 constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
163 is_extended => '0', is_modulus => '0',
164 neg_result => '0', others => (others => '0'));
166 type Decode2ToRegisterFileType is record
167 read1_enable : std_ulogic;
168 read1_reg : gspr_index_t;
169 read2_enable : std_ulogic;
170 read2_reg : gspr_index_t;
171 read3_enable : std_ulogic;
172 read3_reg : gpr_index_t;
175 type RegisterFileToDecode2Type is record
176 read1_data : std_ulogic_vector(63 downto 0);
177 read2_data : std_ulogic_vector(63 downto 0);
178 read3_data : std_ulogic_vector(63 downto 0);
181 type Decode2ToCrFileType is record
185 type CrFileToDecode2Type is record
186 read_cr_data : std_ulogic_vector(31 downto 0);
187 read_xerc_data : xer_common_t;
190 type Execute1ToFetch1Type is record
191 redirect: std_ulogic;
192 redirect_nia: std_ulogic_vector(63 downto 0);
194 constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', others => (others => '0'));
196 type Execute1ToLoadstore1Type is record
198 load : std_ulogic; -- is this a load or store
199 addr1 : std_ulogic_vector(63 downto 0);
200 addr2 : std_ulogic_vector(63 downto 0);
201 data : std_ulogic_vector(63 downto 0); -- data to write, unused for read
202 write_reg : gpr_index_t;
203 length : std_ulogic_vector(3 downto 0);
204 byte_reverse : std_ulogic;
205 sign_extend : std_ulogic; -- do we need to sign extend?
206 update : std_ulogic; -- is this an update instruction?
207 update_reg : gpr_index_t; -- if so, the register to update
210 constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', load => '0', byte_reverse => '0',
211 sign_extend => '0', update => '0', xerc => xerc_init,
212 others => (others => '0'));
214 type Loadstore1ToDcacheType is record
218 addr : std_ulogic_vector(63 downto 0);
219 data : std_ulogic_vector(63 downto 0);
220 write_reg : gpr_index_t;
221 length : std_ulogic_vector(3 downto 0);
222 byte_reverse : std_ulogic;
223 sign_extend : std_ulogic;
225 update_reg : gpr_index_t;
229 type DcacheToWritebackType is record
231 write_enable: std_ulogic;
232 write_reg : gpr_index_t;
233 write_data : std_ulogic_vector(63 downto 0);
234 write_len : std_ulogic_vector(3 downto 0);
235 write_shift : std_ulogic_vector(2 downto 0);
236 sign_extend : std_ulogic;
237 byte_reverse : std_ulogic;
238 second_word : std_ulogic;
241 constant DcacheToWritebackInit : DcacheToWritebackType := (valid => '0', write_enable => '0', sign_extend => '0',
242 byte_reverse => '0', second_word => '0', xerc => xerc_init,
243 others => (others => '0'));
245 type Execute1ToWritebackType is record
248 write_enable : std_ulogic;
249 write_reg: gspr_index_t;
250 write_data: std_ulogic_vector(63 downto 0);
251 write_cr_enable : std_ulogic;
252 write_cr_mask : std_ulogic_vector(7 downto 0);
253 write_cr_data : std_ulogic_vector(31 downto 0);
254 write_xerc_enable : std_ulogic;
257 constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', write_enable => '0',
258 write_cr_enable => '0',
259 write_xerc_enable => '0', xerc => xerc_init,
260 others => (others => '0'));
262 type MultiplyToExecute1Type is record
264 write_reg_data: std_ulogic_vector(63 downto 0);
265 overflow : std_ulogic;
267 constant MultiplyToExecute1Init : MultiplyToExecute1Type := (valid => '0', overflow => '0',
268 others => (others => '0'));
270 type DividerToExecute1Type is record
272 write_reg_data: std_ulogic_vector(63 downto 0);
273 overflow : std_ulogic;
275 constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
276 others => (others => '0'));
278 type WritebackToRegisterFileType is record
279 write_reg : gspr_index_t;
280 write_data : std_ulogic_vector(63 downto 0);
281 write_enable : std_ulogic;
283 constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', others => (others => '0'));
285 type WritebackToCrFileType is record
286 write_cr_enable : std_ulogic;
287 write_cr_mask : std_ulogic_vector(7 downto 0);
288 write_cr_data : std_ulogic_vector(31 downto 0);
289 write_xerc_enable : std_ulogic;
290 write_xerc_data : xer_common_t;
292 constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
293 write_xerc_data => xerc_init,
294 others => (others => '0'));
297 package body common is
298 function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
300 return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
302 function fast_spr_num(spr: spr_num_t) return gspr_index_t is
303 variable n : integer range 0 to 31;
324 when SPR_SPRG3 | SPR_SPRG3U =>
336 return "1" & std_ulogic_vector(to_unsigned(n, 5));
339 function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
341 return i(4 downto 0);
344 function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
349 function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
354 return gpr_to_gspr(g);
358 function is_fast_spr(s: gspr_index_t) return std_ulogic is