configs/common/FSConfig.py

   1 # Copyright (c) 2010-2012 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
  14 # Copyright (c) 2006-2008 The Regents of The University of Michigan
  15 # All rights reserved.
  16 #
  17 # Redistribution and use in source and binary forms, with or without
  18 # modification, are permitted provided that the following conditions are
  19 # met: redistributions of source code must retain the above copyright
  20 # notice, this list of conditions and the following disclaimer;
  21 # redistributions in binary form must reproduce the above copyright
  22 # notice, this list of conditions and the following disclaimer in the
  23 # documentation and/or other materials provided with the distribution;
  24 # neither the name of the copyright holders nor the names of its
  25 # contributors may be used to endorse or promote products derived from
  26 # this software without specific prior written permission.
  27 #
  28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39 #
  40 # Authors: Kevin Lim
  41
  42 from m5.objects import *
  43 from Benchmarks import *
  44 from m5.util import *
  45
  46 class CowIdeDisk(IdeDisk):
  47     image = CowDiskImage(child=RawDiskImage(read_only=True),
  48                          read_only=False)
  49
  50     def childImage(self, ci):
  51         self.image.child.image_file = ci
  52
  53 class MemBus(CoherentXBar):
  54     badaddr_responder = BadAddr()
  55     default = Self.badaddr_responder.pio
  56
  57
  58 def fillInCmdline(mdesc, template, **kwargs):
  59     kwargs.setdefault('disk', mdesc.disk())
  60     kwargs.setdefault('mem', mdesc.mem())
  61     kwargs.setdefault('script', mdesc.script())
  62     return template % kwargs
  63
  64 def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None):
  65
  66     class BaseTsunami(Tsunami):
  67         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
  68         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
  69                             pci_func=0, pci_dev=0, pci_bus=0)
  70
  71     self = LinuxAlphaSystem()
  72     if not mdesc:
  73         # generic system
  74         mdesc = SysConfig()
  75     self.readfile = mdesc.script()
  76
  77     self.tsunami = BaseTsunami()
  78
  79     # Create the io bus to connect all device ports
  80     self.iobus = NoncoherentXBar()
  81     self.tsunami.attachIO(self.iobus)
  82
  83     self.tsunami.ide.pio = self.iobus.master
  84     self.tsunami.ide.config = self.iobus.master
  85
  86     self.tsunami.ethernet.pio = self.iobus.master
  87     self.tsunami.ethernet.config = self.iobus.master
  88
  89     if ruby:
  90         # Store the dma devices for later connection to dma ruby ports.
  91         # Append an underscore to dma_ports to avoid the SimObjectVector check.
  92         self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
  93     else:
  94         self.membus = MemBus()
  95
  96         # By default the bridge responds to all addresses above the I/O
  97         # base address (including the PCI config space)
  98         IO_address_space_base = 0x80000000000
  99         self.bridge = Bridge(delay='50ns',
 100                          ranges = [AddrRange(IO_address_space_base, Addr.max)])
 101         self.bridge.master = self.iobus.slave
 102         self.bridge.slave = self.membus.master
 103
 104         self.tsunami.ide.dma = self.iobus.slave
 105         self.tsunami.ethernet.dma = self.iobus.slave
 106
 107         self.system_port = self.membus.slave
 108
 109     self.mem_ranges = [AddrRange(mdesc.mem())]
 110     self.disk0 = CowIdeDisk(driveID='master')
 111     self.disk2 = CowIdeDisk(driveID='master')
 112     self.disk0.childImage(mdesc.disk())
 113     self.disk2.childImage(disk('linux-bigswap2.img'))
 114     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
 115                                                read_only = True))
 116     self.intrctrl = IntrControl()
 117     self.mem_mode = mem_mode
 118     self.terminal = Terminal()
 119     self.kernel = binary('vmlinux')
 120     self.pal = binary('ts_osfpal')
 121     self.console = binary('console')
 122     if not cmdline:
 123         cmdline = 'root=/dev/hda1 console=ttyS0'
 124     self.boot_osflags = fillInCmdline(mdesc, cmdline)
 125
 126     return self
 127
 128 def makeSparcSystem(mem_mode, mdesc=None):
 129     # Constants from iob.cc and uart8250.cc
 130     iob_man_addr = 0x9800000000
 131     uart_pio_size = 8
 132
 133     class CowMmDisk(MmDisk):
 134         image = CowDiskImage(child=RawDiskImage(read_only=True),
 135                              read_only=False)
 136
 137         def childImage(self, ci):
 138             self.image.child.image_file = ci
 139
 140     self = SparcSystem()
 141     if not mdesc:
 142         # generic system
 143         mdesc = SysConfig()
 144     self.readfile = mdesc.script()
 145     self.iobus = NoncoherentXBar()
 146     self.membus = MemBus()
 147     self.bridge = Bridge(delay='50ns')
 148     self.t1000 = T1000()
 149     self.t1000.attachOnChipIO(self.membus)
 150     self.t1000.attachIO(self.iobus)
 151     self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
 152                        AddrRange(Addr('2GB'), size ='256MB')]
 153     self.bridge.master = self.iobus.slave
 154     self.bridge.slave = self.membus.master
 155     self.rom.port = self.membus.master
 156     self.nvram.port = self.membus.master
 157     self.hypervisor_desc.port = self.membus.master
 158     self.partition_desc.port = self.membus.master
 159     self.intrctrl = IntrControl()
 160     self.disk0 = CowMmDisk()
 161     self.disk0.childImage(disk('disk.s10hw2'))
 162     self.disk0.pio = self.iobus.master
 163
 164     # The puart0 and hvuart are placed on the IO bus, so create ranges
 165     # for them. The remaining IO range is rather fragmented, so poke
 166     # holes for the iob and partition descriptors etc.
 167     self.bridge.ranges = \
 168         [
 169         AddrRange(self.t1000.puart0.pio_addr,
 170                   self.t1000.puart0.pio_addr + uart_pio_size - 1),
 171         AddrRange(self.disk0.pio_addr,
 172                   self.t1000.fake_jbi.pio_addr +
 173                   self.t1000.fake_jbi.pio_size - 1),
 174         AddrRange(self.t1000.fake_clk.pio_addr,
 175                   iob_man_addr - 1),
 176         AddrRange(self.t1000.fake_l2_1.pio_addr,
 177                   self.t1000.fake_ssi.pio_addr +
 178                   self.t1000.fake_ssi.pio_size - 1),
 179         AddrRange(self.t1000.hvuart.pio_addr,
 180                   self.t1000.hvuart.pio_addr + uart_pio_size - 1)
 181         ]
 182     self.reset_bin = binary('reset_new.bin')
 183     self.hypervisor_bin = binary('q_new.bin')
 184     self.openboot_bin = binary('openboot_new.bin')
 185     self.nvram_bin = binary('nvram1')
 186     self.hypervisor_desc_bin = binary('1up-hv.bin')
 187     self.partition_desc_bin = binary('1up-md.bin')
 188
 189     self.system_port = self.membus.slave
 190
 191     return self
 192
 193 def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
 194                   dtb_filename=None, bare_metal=False, cmdline=None):
 195     assert machine_type
 196
 197     if bare_metal:
 198         self = ArmSystem()
 199     else:
 200         self = LinuxArmSystem()
 201
 202     if not mdesc:
 203         # generic system
 204         mdesc = SysConfig()
 205
 206     self.readfile = mdesc.script()
 207     self.iobus = NoncoherentXBar()
 208     self.membus = MemBus()
 209     self.membus.badaddr_responder.warn_access = "warn"
 210     self.bridge = Bridge(delay='50ns')
 211     self.bridge.master = self.iobus.slave
 212     self.bridge.slave = self.membus.master
 213
 214     self.mem_mode = mem_mode
 215
 216     if machine_type == "RealView_PBX":
 217         self.realview = RealViewPBX()
 218     elif machine_type == "RealView_EB":
 219         self.realview = RealViewEB()
 220     elif machine_type == "VExpress_EMM":
 221         self.realview = VExpress_EMM()
 222         if not dtb_filename:
 223             dtb_filename = 'vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb' % num_cpus
 224     elif machine_type == "VExpress_EMM64":
 225         self.realview = VExpress_EMM64()
 226         if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img':
 227             print "Selected 64-bit ARM architecture, updating default disk image..."
 228             mdesc.diskname = 'linaro-minimal-aarch64.img'
 229         if not dtb_filename:
 230             dtb_filename = 'vexpress.aarch64.20140821.dtb'
 231     else:
 232         print "Unknown Machine Type"
 233         sys.exit(1)
 234
 235     self.cf0 = CowIdeDisk(driveID='master')
 236     self.cf0.childImage(mdesc.disk())
 237
 238     # Attach any PCI devices this platform supports
 239     self.realview.attachPciDevices()
 240     # default to an IDE controller rather than a CF one
 241     try:
 242         self.realview.ide.disks = [self.cf0]
 243     except:
 244         self.realview.cf_ctrl.disks = [self.cf0]
 245
 246     self.mem_ranges = []
 247     size_remain = long(Addr(mdesc.mem()))
 248     for region in self.realview._mem_regions:
 249         if size_remain > long(region[1]):
 250             self.mem_ranges.append(AddrRange(region[0], size=region[1]))
 251             size_remain = size_remain - long(region[1])
 252         else:
 253             self.mem_ranges.append(AddrRange(region[0], size=size_remain))
 254             size_remain = 0
 255             break
 256         warn("Memory size specified spans more than one region. Creating" \
 257              " another memory controller for that range.")
 258
 259     if size_remain > 0:
 260         fatal("The currently selected ARM platforms doesn't support" \
 261               " the amount of DRAM you've selected. Please try" \
 262               " another platform")
 263
 264     if bare_metal:
 265         # EOT character on UART will end the simulation
 266         self.realview.uart.end_on_eot = True
 267     else:
 268         if machine_type == "VExpress_EMM64":
 269             self.kernel = binary('vmlinux.aarch64.20140821')
 270         elif machine_type == "VExpress_EMM":
 271             self.kernel = binary('vmlinux.aarch32.ll_20131205.0-gem5')
 272         else:
 273             self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
 274
 275         if dtb_filename:
 276             self.dtb_filename = binary(dtb_filename)
 277         self.machine_type = machine_type
 278         # Ensure that writes to the UART actually go out early in the boot
 279         if not cmdline:
 280             cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
 281                       'lpj=19988480 norandmaps rw loglevel=8 ' + \
 282                       'mem=%(mem)s root=/dev/sda1'
 283
 284         self.realview.setupBootLoader(self.membus, self, binary)
 285         self.gic_cpu_addr = self.realview.gic.cpu_addr
 286         self.flags_addr = self.realview.realview_io.pio_addr + 0x30
 287
 288         if mdesc.disk().lower().count('android'):
 289             cmdline += " init=/init "
 290         self.boot_osflags = fillInCmdline(mdesc, cmdline)
 291     self.realview.attachOnChipIO(self.membus, self.bridge)
 292     self.realview.attachIO(self.iobus)
 293     self.intrctrl = IntrControl()
 294     self.terminal = Terminal()
 295     self.vncserver = VncServer()
 296
 297     self.system_port = self.membus.slave
 298
 299     return self
 300
 301
 302 def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
 303     class BaseMalta(Malta):
 304         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
 305         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
 306                             pci_func=0, pci_dev=0, pci_bus=0)
 307
 308     self = LinuxMipsSystem()
 309     if not mdesc:
 310         # generic system
 311         mdesc = SysConfig()
 312     self.readfile = mdesc.script()
 313     self.iobus = NoncoherentXBar()
 314     self.membus = MemBus()
 315     self.bridge = Bridge(delay='50ns')
 316     self.mem_ranges = [AddrRange('1GB')]
 317     self.bridge.master = self.iobus.slave
 318     self.bridge.slave = self.membus.master
 319     self.disk0 = CowIdeDisk(driveID='master')
 320     self.disk2 = CowIdeDisk(driveID='master')
 321     self.disk0.childImage(mdesc.disk())
 322     self.disk2.childImage(disk('linux-bigswap2.img'))
 323     self.malta = BaseMalta()
 324     self.malta.attachIO(self.iobus)
 325     self.malta.ide.pio = self.iobus.master
 326     self.malta.ide.config = self.iobus.master
 327     self.malta.ide.dma = self.iobus.slave
 328     self.malta.ethernet.pio = self.iobus.master
 329     self.malta.ethernet.config = self.iobus.master
 330     self.malta.ethernet.dma = self.iobus.slave
 331     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
 332                                                read_only = True))
 333     self.intrctrl = IntrControl()
 334     self.mem_mode = mem_mode
 335     self.terminal = Terminal()
 336     self.kernel = binary('mips/vmlinux')
 337     self.console = binary('mips/console')
 338     if not cmdline:
 339         cmdline = 'root=/dev/hda1 console=ttyS0'
 340     self.boot_osflags = fillInCmdline(mdesc, cmdline)
 341
 342     self.system_port = self.membus.slave
 343
 344     return self
 345
 346 def x86IOAddress(port):
 347     IO_address_space_base = 0x8000000000000000
 348     return IO_address_space_base + port
 349
 350 def connectX86ClassicSystem(x86_sys, numCPUs):
 351     # Constants similar to x86_traits.hh
 352     IO_address_space_base = 0x8000000000000000
 353     pci_config_address_space_base = 0xc000000000000000
 354     interrupts_address_space_base = 0xa000000000000000
 355     APIC_range_size = 1 << 12;
 356
 357     x86_sys.membus = MemBus()
 358
 359     # North Bridge
 360     x86_sys.iobus = NoncoherentXBar()
 361     x86_sys.bridge = Bridge(delay='50ns')
 362     x86_sys.bridge.master = x86_sys.iobus.slave
 363     x86_sys.bridge.slave = x86_sys.membus.master
 364     # Allow the bridge to pass through:
 365     #  1) kernel configured PCI device memory map address: address range
 366     #     [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
 367     #  2) the bridge to pass through the IO APIC (two pages, already contained in 1),
 368     #  3) everything in the IO address range up to the local APIC, and
 369     #  4) then the entire PCI address space and beyond.
 370     x86_sys.bridge.ranges = \
 371         [
 372         AddrRange(0xC0000000, 0xFFFF0000),
 373         AddrRange(IO_address_space_base,
 374                   interrupts_address_space_base - 1),
 375         AddrRange(pci_config_address_space_base,
 376                   Addr.max)
 377         ]
 378
 379     # Create a bridge from the IO bus to the memory bus to allow access to
 380     # the local APIC (two pages)
 381     x86_sys.apicbridge = Bridge(delay='50ns')
 382     x86_sys.apicbridge.slave = x86_sys.iobus.master
 383     x86_sys.apicbridge.master = x86_sys.membus.slave
 384     x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
 385                                            interrupts_address_space_base +
 386                                            numCPUs * APIC_range_size
 387                                            - 1)]
 388
 389     # connect the io bus
 390     x86_sys.pc.attachIO(x86_sys.iobus)
 391
 392     x86_sys.system_port = x86_sys.membus.slave
 393
 394 def connectX86RubySystem(x86_sys):
 395     # North Bridge
 396     x86_sys.iobus = NoncoherentXBar()
 397
 398     # add the ide to the list of dma devices that later need to attach to
 399     # dma controllers
 400     x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
 401     x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
 402
 403
 404 def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False):
 405     if self == None:
 406         self = X86System()
 407
 408     if not mdesc:
 409         # generic system
 410         mdesc = SysConfig()
 411     self.readfile = mdesc.script()
 412
 413     self.mem_mode = mem_mode
 414
 415     # Physical memory
 416     # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
 417     # for various devices.  Hence, if the physical memory size is greater than
 418     # 3GB, we need to split it into two parts.
 419     excess_mem_size = \
 420         convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
 421     if excess_mem_size <= 0:
 422         self.mem_ranges = [AddrRange(mdesc.mem())]
 423     else:
 424         warn("Physical memory size specified is %s which is greater than " \
 425              "3GB.  Twice the number of memory controllers would be " \
 426              "created."  % (mdesc.mem()))
 427
 428         self.mem_ranges = [AddrRange('3GB'),
 429             AddrRange(Addr('4GB'), size = excess_mem_size)]
 430
 431     # Platform
 432     self.pc = Pc()
 433
 434     # Create and connect the busses required by each memory system
 435     if Ruby:
 436         connectX86RubySystem(self)
 437     else:
 438         connectX86ClassicSystem(self, numCPUs)
 439
 440     self.intrctrl = IntrControl()
 441
 442     # Disks
 443     disk0 = CowIdeDisk(driveID='master')
 444     disk2 = CowIdeDisk(driveID='master')
 445     disk0.childImage(mdesc.disk())
 446     disk2.childImage(disk('linux-bigswap2.img'))
 447     self.pc.south_bridge.ide.disks = [disk0, disk2]
 448
 449     # Add in a Bios information structure.
 450     structures = [X86SMBiosBiosInformation()]
 451     self.smbios_table.structures = structures
 452
 453     # Set up the Intel MP table
 454     base_entries = []
 455     ext_entries = []
 456     for i in xrange(numCPUs):
 457         bp = X86IntelMPProcessor(
 458                 local_apic_id = i,
 459                 local_apic_version = 0x14,
 460                 enable = True,
 461                 bootstrap = (i == 0))
 462         base_entries.append(bp)
 463     io_apic = X86IntelMPIOAPIC(
 464             id = numCPUs,
 465             version = 0x11,
 466             enable = True,
 467             address = 0xfec00000)
 468     self.pc.south_bridge.io_apic.apic_id = io_apic.id
 469     base_entries.append(io_apic)
 470     # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
 471     # but linux kernel cannot config PCI device if it was not connected to PCI bus,
 472     # so we fix PCI bus id to 0, and ISA bus id to 1.
 473     pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI')
 474     base_entries.append(pci_bus)
 475     isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA')
 476     base_entries.append(isa_bus)
 477     connect_busses = X86IntelMPBusHierarchy(bus_id=1,
 478             subtractive_decode=True, parent_bus=0)
 479     ext_entries.append(connect_busses)
 480     pci_dev4_inta = X86IntelMPIOIntAssignment(
 481             interrupt_type = 'INT',
 482             polarity = 'ConformPolarity',
 483             trigger = 'ConformTrigger',
 484             source_bus_id = 0,
 485             source_bus_irq = 0 + (4 << 2),
 486             dest_io_apic_id = io_apic.id,
 487             dest_io_apic_intin = 16)
 488     base_entries.append(pci_dev4_inta)
 489     def assignISAInt(irq, apicPin):
 490         assign_8259_to_apic = X86IntelMPIOIntAssignment(
 491                 interrupt_type = 'ExtInt',
 492                 polarity = 'ConformPolarity',
 493                 trigger = 'ConformTrigger',
 494                 source_bus_id = 1,
 495                 source_bus_irq = irq,
 496                 dest_io_apic_id = io_apic.id,
 497                 dest_io_apic_intin = 0)
 498         base_entries.append(assign_8259_to_apic)
 499         assign_to_apic = X86IntelMPIOIntAssignment(
 500                 interrupt_type = 'INT',
 501                 polarity = 'ConformPolarity',
 502                 trigger = 'ConformTrigger',
 503                 source_bus_id = 1,
 504                 source_bus_irq = irq,
 505                 dest_io_apic_id = io_apic.id,
 506                 dest_io_apic_intin = apicPin)
 507         base_entries.append(assign_to_apic)
 508     assignISAInt(0, 2)
 509     assignISAInt(1, 1)
 510     for i in range(3, 15):
 511         assignISAInt(i, i)
 512     self.intel_mp_table.base_entries = base_entries
 513     self.intel_mp_table.ext_entries = ext_entries
 514
 515 def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False,
 516                        cmdline=None):
 517     self = LinuxX86System()
 518
 519     # Build up the x86 system and then specialize it for Linux
 520     makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
 521
 522     # We assume below that there's at least 1MB of memory. We'll require 2
 523     # just to avoid corner cases.
 524     phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
 525     assert(phys_mem_size >= 0x200000)
 526     assert(len(self.mem_ranges) <= 2)
 527
 528     entries = \
 529        [
 530         # Mark the first megabyte of memory as reserved
 531         X86E820Entry(addr = 0, size = '639kB', range_type = 1),
 532         X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
 533         # Mark the rest of physical memory as available
 534         X86E820Entry(addr = 0x100000,
 535                 size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
 536                 range_type = 1),
 537         ]
 538
 539     # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
 540     # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
 541     # specific range can pass though bridge to iobus.
 542     if len(self.mem_ranges) == 1:
 543         entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
 544             size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
 545             range_type=2))
 546
 547     # Reserve the last 16kB of the 32-bit address space for the m5op interface
 548     entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2))
 549
 550     # In case the physical memory is greater than 3GB, we split it into two
 551     # parts and add a separate e820 entry for the second part.  This entry
 552     # starts at 0x100000000,  which is the first address after the space
 553     # reserved for devices.
 554     if len(self.mem_ranges) == 2:
 555         entries.append(X86E820Entry(addr = 0x100000000,
 556             size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
 557
 558     self.e820_table.entries = entries
 559
 560     # Command line
 561     if not cmdline:
 562         cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
 563     self.boot_osflags = fillInCmdline(mdesc, cmdline)
 564     self.kernel = binary('x86_64-vmlinux-2.6.22.9')
 565     return self
 566
 567
 568 def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
 569     self = Root(full_system = full_system)
 570     self.testsys = testSystem
 571     self.drivesys = driveSystem
 572     self.etherlink = EtherLink()
 573
 574     if hasattr(testSystem, 'realview'):
 575         self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
 576         self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
 577     elif hasattr(testSystem, 'tsunami'):
 578         self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 579         self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
 580     else:
 581         fatal("Don't know how to connect these system together")
 582
 583     if dumpfile:
 584         self.etherdump = EtherDump(file=dumpfile)
 585         self.etherlink.dump = Parent.etherdump
 586
 587     return self