2 use ieee.std_logic_1164.all;
9 PIPELINE_DEPTH : natural := 2
15 complete_in : in std_ulogic;
16 valid_in : in std_ulogic;
17 repeated : in std_ulogic;
18 flush_in : in std_ulogic;
19 busy_in : in std_ulogic;
20 deferred : in std_ulogic;
21 sgl_pipe_in : in std_ulogic;
22 stop_mark_in : in std_ulogic;
24 gpr_write_valid_in : in std_ulogic;
25 gpr_write_in : in gspr_index_t;
26 gpr_bypassable : in std_ulogic;
28 update_gpr_write_valid : in std_ulogic;
29 update_gpr_write_reg : in gspr_index_t;
31 gpr_a_read_valid_in : in std_ulogic;
32 gpr_a_read_in : in gspr_index_t;
34 gpr_b_read_valid_in : in std_ulogic;
35 gpr_b_read_in : in gspr_index_t;
37 gpr_c_read_valid_in : in std_ulogic;
38 gpr_c_read_in : in gspr_index_t;
40 cr_read_in : in std_ulogic;
41 cr_write_in : in std_ulogic;
42 cr_bypassable : in std_ulogic;
44 valid_out : out std_ulogic;
45 stall_out : out std_ulogic;
46 stopped_out : out std_ulogic;
48 gpr_bypass_a : out std_ulogic;
49 gpr_bypass_b : out std_ulogic;
50 gpr_bypass_c : out std_ulogic;
51 cr_bypass : out std_ulogic
55 architecture rtl of control is
56 type state_type is (IDLE, WAIT_FOR_PREV_TO_COMPLETE, WAIT_FOR_CURR_TO_COMPLETE);
58 type reg_internal_type is record
60 outstanding : integer range -1 to PIPELINE_DEPTH+2;
62 constant reg_internal_init : reg_internal_type := (state => IDLE, outstanding => 0);
64 signal r_int, rin_int : reg_internal_type := reg_internal_init;
66 signal stall_a_out : std_ulogic;
67 signal stall_b_out : std_ulogic;
68 signal stall_c_out : std_ulogic;
69 signal cr_stall_out : std_ulogic;
71 signal gpr_write_valid : std_ulogic := '0';
72 signal cr_write_valid : std_ulogic := '0';
75 gpr_hazard0: entity work.gpr_hazard
77 PIPELINE_DEPTH => PIPELINE_DEPTH
83 complete_in => complete_in,
88 gpr_write_valid_in => gpr_write_valid,
89 gpr_write_in => gpr_write_in,
90 bypass_avail => gpr_bypassable,
91 gpr_read_valid_in => gpr_a_read_valid_in,
92 gpr_read_in => gpr_a_read_in,
94 ugpr_write_valid => update_gpr_write_valid,
95 ugpr_write_reg => update_gpr_write_reg,
97 stall_out => stall_a_out,
98 use_bypass => gpr_bypass_a
101 gpr_hazard1: entity work.gpr_hazard
103 PIPELINE_DEPTH => PIPELINE_DEPTH
108 deferred => deferred,
109 complete_in => complete_in,
110 flush_in => flush_in,
111 issuing => valid_out,
112 repeated => repeated,
114 gpr_write_valid_in => gpr_write_valid,
115 gpr_write_in => gpr_write_in,
116 bypass_avail => gpr_bypassable,
117 gpr_read_valid_in => gpr_b_read_valid_in,
118 gpr_read_in => gpr_b_read_in,
120 ugpr_write_valid => update_gpr_write_valid,
121 ugpr_write_reg => update_gpr_write_reg,
123 stall_out => stall_b_out,
124 use_bypass => gpr_bypass_b
127 gpr_hazard2: entity work.gpr_hazard
129 PIPELINE_DEPTH => PIPELINE_DEPTH
134 deferred => deferred,
135 complete_in => complete_in,
136 flush_in => flush_in,
137 issuing => valid_out,
138 repeated => repeated,
140 gpr_write_valid_in => gpr_write_valid,
141 gpr_write_in => gpr_write_in,
142 bypass_avail => gpr_bypassable,
143 gpr_read_valid_in => gpr_c_read_valid_in,
144 gpr_read_in => gpr_c_read_in,
146 ugpr_write_valid => update_gpr_write_valid,
147 ugpr_write_reg => update_gpr_write_reg,
149 stall_out => stall_c_out,
150 use_bypass => gpr_bypass_c
153 cr_hazard0: entity work.cr_hazard
155 PIPELINE_DEPTH => PIPELINE_DEPTH
160 deferred => deferred,
161 complete_in => complete_in,
162 flush_in => flush_in,
163 issuing => valid_out,
165 cr_read_in => cr_read_in,
166 cr_write_in => cr_write_valid,
167 bypassable => cr_bypassable,
169 stall_out => cr_stall_out,
170 use_bypass => cr_bypass
173 control0: process(clk)
175 if rising_edge(clk) then
176 assert rin_int.outstanding >= 0 and rin_int.outstanding <= (PIPELINE_DEPTH+1)
177 report "Outstanding bad " & integer'image(rin_int.outstanding) severity failure;
182 control1 : process(all)
183 variable v_int : reg_internal_type;
184 variable valid_tmp : std_ulogic;
185 variable stall_tmp : std_ulogic;
190 valid_tmp := valid_in and not flush_in;
193 if flush_in = '1' then
194 -- expect to see complete_in next cycle
195 v_int.outstanding := 1;
196 elsif complete_in = '1' then
197 v_int.outstanding := r_int.outstanding - 1;
201 v_int := reg_internal_init;
205 -- Handle debugger stop
207 if stop_mark_in = '1' and v_int.outstanding = 0 then
211 -- state machine to handle instructions that must be single
212 -- through the pipeline.
215 if valid_tmp = '1' then
216 if (sgl_pipe_in = '1') then
217 if v_int.outstanding /= 0 then
218 v_int.state := WAIT_FOR_PREV_TO_COMPLETE;
221 -- send insn out and wait on it to complete
222 v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
225 -- let it go out if there are no GPR hazards
226 stall_tmp := stall_a_out or stall_b_out or stall_c_out or cr_stall_out;
230 when WAIT_FOR_PREV_TO_COMPLETE =>
231 if v_int.outstanding = 0 then
232 -- send insn out and wait on it to complete
233 v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
238 when WAIT_FOR_CURR_TO_COMPLETE =>
239 if v_int.outstanding = 0 then
241 -- XXX Don't replicate this
242 if valid_tmp = '1' then
243 if (sgl_pipe_in = '1') then
244 if v_int.outstanding /= 0 then
245 v_int.state := WAIT_FOR_PREV_TO_COMPLETE;
248 -- send insn out and wait on it to complete
249 v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
252 -- let it go out if there are no GPR hazards
253 stall_tmp := stall_a_out or stall_b_out or stall_c_out or cr_stall_out;
261 if stall_tmp = '1' then
265 if valid_tmp = '1' then
266 if deferred = '0' then
267 v_int.outstanding := v_int.outstanding + 1;
269 gpr_write_valid <= gpr_write_valid_in;
270 cr_write_valid <= cr_write_in;
272 gpr_write_valid <= '0';
273 cr_write_valid <= '0';
277 valid_out <= valid_tmp;
278 stall_out <= stall_tmp or deferred;