core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false;
  12         DISABLE_FLATTEN : boolean := false;
  13         EX1_BYPASS : boolean := true;
  14         HAS_FPU : boolean := true;
  15         HAS_BTC : boolean := true;
  16         ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
  17         LOG_LENGTH : natural := 512
  18         );
  19     port (
  20         clk          : in std_ulogic;
  21         rst          : in std_ulogic;
  22
  23         -- Alternate reset (0xffff0000) for use by DRAM init fw
  24         alt_reset    : in std_ulogic;
  25
  26         -- Wishbone interface
  27         wishbone_insn_in  : in wishbone_slave_out;
  28         wishbone_insn_out : out wishbone_master_out;
  29
  30         wishbone_data_in  : in wishbone_slave_out;
  31         wishbone_data_out : out wishbone_master_out;
  32
  33         dmi_addr        : in std_ulogic_vector(3 downto 0);
  34         dmi_din         : in std_ulogic_vector(63 downto 0);
  35         dmi_dout        : out std_ulogic_vector(63 downto 0);
  36         dmi_req         : in std_ulogic;
  37         dmi_wr          : in std_ulogic;
  38         dmi_ack         : out std_ulogic;
  39
  40         ext_irq         : in std_ulogic;
  41
  42         terminated_out   : out std_logic
  43         );
  44 end core;
  45
  46 architecture behave of core is
  47     -- icache signals
  48     signal fetch1_to_icache : Fetch1ToIcacheType;
  49     signal icache_to_decode1 : IcacheToDecode1Type;
  50     signal mmu_to_icache : MmuToIcacheType;
  51
  52     -- decode signals
  53     signal decode1_to_decode2: Decode1ToDecode2Type;
  54     signal decode1_to_fetch1: Decode1ToFetch1Type;
  55     signal decode2_to_execute1: Decode2ToExecute1Type;
  56
  57     -- register file signals
  58     signal register_file_to_decode2: RegisterFileToDecode2Type;
  59     signal decode2_to_register_file: Decode2ToRegisterFileType;
  60     signal writeback_to_register_file: WritebackToRegisterFileType;
  61
  62     -- CR file signals
  63     signal decode2_to_cr_file: Decode2ToCrFileType;
  64     signal cr_file_to_decode2: CrFileToDecode2Type;
  65     signal writeback_to_cr_file: WritebackToCrFileType;
  66
  67     -- execute signals
  68     signal execute1_to_writeback: Execute1ToWritebackType;
  69     signal execute1_to_fetch1: Execute1ToFetch1Type;
  70
  71     -- load store signals
  72     signal execute1_to_loadstore1: Execute1ToLoadstore1Type;
  73     signal loadstore1_to_execute1: Loadstore1ToExecute1Type;
  74     signal loadstore1_to_writeback: Loadstore1ToWritebackType;
  75     signal loadstore1_to_mmu: Loadstore1ToMmuType;
  76     signal mmu_to_loadstore1: MmuToLoadstore1Type;
  77
  78     -- dcache signals
  79     signal loadstore1_to_dcache: Loadstore1ToDcacheType;
  80     signal dcache_to_loadstore1: DcacheToLoadstore1Type;
  81     signal mmu_to_dcache: MmuToDcacheType;
  82     signal dcache_to_mmu: DcacheToMmuType;
  83
  84     -- FPU signals
  85     signal execute1_to_fpu: Execute1ToFPUType;
  86     signal fpu_to_execute1: FPUToExecute1Type;
  87     signal fpu_to_writeback: FPUToWritebackType;
  88
  89     -- local signals
  90     signal fetch1_stall_in : std_ulogic;
  91     signal icache_stall_out : std_ulogic;
  92     signal icache_stall_in : std_ulogic;
  93     signal decode1_stall_in : std_ulogic;
  94     signal decode1_busy     : std_ulogic;
  95     signal decode2_busy_in : std_ulogic;
  96     signal decode2_stall_out : std_ulogic;
  97     signal ex1_icache_inval: std_ulogic;
  98     signal ex1_busy_out: std_ulogic;
  99     signal dcache_stall_out: std_ulogic;
 100
 101     signal flush: std_ulogic;
 102     signal decode1_flush: std_ulogic;
 103     signal fetch1_flush: std_ulogic;
 104
 105     signal complete: instr_tag_t;
 106     signal terminate: std_ulogic;
 107     signal core_rst: std_ulogic;
 108     signal icache_inv: std_ulogic;
 109
 110     -- Delayed/Latched resets and alt_reset
 111     signal rst_fetch1  : std_ulogic := '1';
 112     signal rst_fetch2  : std_ulogic := '1';
 113     signal rst_icache  : std_ulogic := '1';
 114     signal rst_dcache  : std_ulogic := '1';
 115     signal rst_dec1    : std_ulogic := '1';
 116     signal rst_dec2    : std_ulogic := '1';
 117     signal rst_ex1     : std_ulogic := '1';
 118     signal rst_fpu     : std_ulogic := '1';
 119     signal rst_ls1     : std_ulogic := '1';
 120     signal rst_dbg     : std_ulogic := '1';
 121     signal alt_reset_d : std_ulogic;
 122
 123     signal sim_cr_dump: std_ulogic;
 124
 125     -- Debug actions
 126     signal dbg_core_stop: std_ulogic;
 127     signal dbg_core_rst: std_ulogic;
 128     signal dbg_icache_rst: std_ulogic;
 129
 130     signal dbg_gpr_req : std_ulogic;
 131     signal dbg_gpr_ack : std_ulogic;
 132     signal dbg_gpr_addr : gspr_index_t;
 133     signal dbg_gpr_data : std_ulogic_vector(63 downto 0);
 134
 135     signal msr : std_ulogic_vector(63 downto 0);
 136
 137     -- Debug status
 138     signal dbg_core_is_stopped: std_ulogic;
 139
 140     -- Logging signals
 141     signal log_data    : std_ulogic_vector(255 downto 0);
 142     signal log_rd_addr : std_ulogic_vector(31 downto 0);
 143     signal log_wr_addr : std_ulogic_vector(31 downto 0);
 144     signal log_rd_data : std_ulogic_vector(63 downto 0);
 145
 146     function keep_h(disable : boolean) return string is
 147     begin
 148         if disable then
 149             return "yes";
 150         else
 151             return "no";
 152         end if;
 153     end function;
 154     attribute keep_hierarchy : string;
 155     attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
 156     attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
 157     attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
 158     attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
 159     attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
 160     attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
 161     attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
 162     attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
 163     attribute keep_hierarchy of mmu_0 : label is keep_h(DISABLE_FLATTEN);
 164     attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
 165     attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
 166     attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
 167 begin
 168
 169     core_rst <= dbg_core_rst or rst;
 170
 171     resets: process(clk)
 172     begin
 173         if rising_edge(clk) then
 174             rst_fetch1  <= core_rst;
 175             rst_fetch2  <= core_rst;
 176             rst_icache  <= core_rst;
 177             rst_dcache  <= core_rst;
 178             rst_dec1    <= core_rst;
 179             rst_dec2    <= core_rst;
 180             rst_ex1     <= core_rst;
 181             rst_fpu     <= core_rst;
 182             rst_ls1     <= core_rst;
 183             rst_dbg     <= rst;
 184             alt_reset_d <= alt_reset;
 185         end if;
 186     end process;
 187
 188     fetch1_0: entity work.fetch1
 189         generic map (
 190             RESET_ADDRESS => (others => '0'),
 191             ALT_RESET_ADDRESS => ALT_RESET_ADDRESS,
 192             HAS_BTC => HAS_BTC
 193             )
 194         port map (
 195             clk => clk,
 196             rst => rst_fetch1,
 197             alt_reset_in => alt_reset_d,
 198             stall_in => fetch1_stall_in,
 199             flush_in => fetch1_flush,
 200             inval_btc => ex1_icache_inval or mmu_to_icache.tlbie,
 201             stop_in => dbg_core_stop,
 202             d_in => decode1_to_fetch1,
 203             e_in => execute1_to_fetch1,
 204             i_out => fetch1_to_icache,
 205             log_out => log_data(42 downto 0)
 206             );
 207
 208     fetch1_stall_in <= icache_stall_out or decode1_busy;
 209     fetch1_flush <= flush or decode1_flush;
 210
 211     icache_0: entity work.icache
 212         generic map(
 213             SIM => SIM,
 214             LINE_SIZE => 64,
 215             NUM_LINES => 64,
 216             NUM_WAYS => 2,
 217             LOG_LENGTH => LOG_LENGTH
 218             )
 219         port map(
 220             clk => clk,
 221             rst => rst_icache,
 222             i_in => fetch1_to_icache,
 223             i_out => icache_to_decode1,
 224             m_in => mmu_to_icache,
 225             flush_in => fetch1_flush,
 226             inval_in => dbg_icache_rst or ex1_icache_inval,
 227             stall_in => icache_stall_in,
 228             stall_out => icache_stall_out,
 229             wishbone_out => wishbone_insn_out,
 230             wishbone_in => wishbone_insn_in,
 231             log_out => log_data(96 downto 43)
 232             );
 233
 234     icache_stall_in <= decode1_busy;
 235
 236     decode1_0: entity work.decode1
 237         generic map(
 238             HAS_FPU => HAS_FPU,
 239             LOG_LENGTH => LOG_LENGTH
 240             )
 241         port map (
 242             clk => clk,
 243             rst => rst_dec1,
 244             stall_in => decode1_stall_in,
 245             flush_in => flush,
 246             flush_out => decode1_flush,
 247             busy_out => decode1_busy,
 248             f_in => icache_to_decode1,
 249             d_out => decode1_to_decode2,
 250             f_out => decode1_to_fetch1,
 251             log_out => log_data(109 downto 97)
 252             );
 253
 254     decode1_stall_in <= decode2_stall_out;
 255
 256     decode2_0: entity work.decode2
 257         generic map (
 258             EX1_BYPASS => EX1_BYPASS,
 259             HAS_FPU => HAS_FPU,
 260             LOG_LENGTH => LOG_LENGTH
 261             )
 262         port map (
 263             clk => clk,
 264             rst => rst_dec2,
 265             busy_in => decode2_busy_in,
 266             stall_out => decode2_stall_out,
 267             flush_in => flush,
 268             complete_in => complete,
 269             stopped_out => dbg_core_is_stopped,
 270             d_in => decode1_to_decode2,
 271             e_out => decode2_to_execute1,
 272             r_in => register_file_to_decode2,
 273             r_out => decode2_to_register_file,
 274             c_in => cr_file_to_decode2,
 275             c_out => decode2_to_cr_file,
 276             log_out => log_data(119 downto 110)
 277             );
 278     decode2_busy_in <= ex1_busy_out;
 279
 280     register_file_0: entity work.register_file
 281         generic map (
 282             SIM => SIM,
 283             HAS_FPU => HAS_FPU,
 284             LOG_LENGTH => LOG_LENGTH
 285             )
 286         port map (
 287             clk => clk,
 288             d_in => decode2_to_register_file,
 289             d_out => register_file_to_decode2,
 290             w_in => writeback_to_register_file,
 291             dbg_gpr_req => dbg_gpr_req,
 292             dbg_gpr_ack => dbg_gpr_ack,
 293             dbg_gpr_addr => dbg_gpr_addr,
 294             dbg_gpr_data => dbg_gpr_data,
 295             sim_dump => terminate,
 296             sim_dump_done => sim_cr_dump,
 297             log_out => log_data(255 downto 184)
 298             );
 299
 300     cr_file_0: entity work.cr_file
 301         generic map (
 302             SIM => SIM,
 303             LOG_LENGTH => LOG_LENGTH
 304             )
 305         port map (
 306             clk => clk,
 307             d_in => decode2_to_cr_file,
 308             d_out => cr_file_to_decode2,
 309             w_in => writeback_to_cr_file,
 310             sim_dump => sim_cr_dump,
 311             log_out => log_data(183 downto 171)
 312             );
 313
 314     execute1_0: entity work.execute1
 315         generic map (
 316             EX1_BYPASS => EX1_BYPASS,
 317             HAS_FPU => HAS_FPU,
 318             LOG_LENGTH => LOG_LENGTH
 319             )
 320         port map (
 321             clk => clk,
 322             rst => rst_ex1,
 323             flush_out => flush,
 324             busy_out => ex1_busy_out,
 325             e_in => decode2_to_execute1,
 326             l_in => loadstore1_to_execute1,
 327             fp_in => fpu_to_execute1,
 328             ext_irq_in => ext_irq,
 329             l_out => execute1_to_loadstore1,
 330             f_out => execute1_to_fetch1,
 331             fp_out => execute1_to_fpu,
 332             e_out => execute1_to_writeback,
 333             icache_inval => ex1_icache_inval,
 334             dbg_msr_out => msr,
 335             terminate_out => terminate,
 336             log_out => log_data(134 downto 120),
 337             log_rd_addr => log_rd_addr,
 338             log_rd_data => log_rd_data,
 339             log_wr_addr => log_wr_addr
 340             );
 341
 342     with_fpu: if HAS_FPU generate
 343     begin
 344         fpu_0: entity work.fpu
 345             port map (
 346                 clk => clk,
 347                 rst => rst_fpu,
 348                 e_in => execute1_to_fpu,
 349                 e_out => fpu_to_execute1,
 350                 w_out => fpu_to_writeback
 351                 );
 352     end generate;
 353
 354     no_fpu: if not HAS_FPU generate
 355     begin
 356         fpu_to_execute1 <= FPUToExecute1Init;
 357         fpu_to_writeback <= FPUToWritebackInit;
 358     end generate;
 359
 360     loadstore1_0: entity work.loadstore1
 361         generic map (
 362             HAS_FPU => HAS_FPU,
 363             LOG_LENGTH => LOG_LENGTH
 364             )
 365         port map (
 366             clk => clk,
 367             rst => rst_ls1,
 368             l_in => execute1_to_loadstore1,
 369             e_out => loadstore1_to_execute1,
 370             l_out => loadstore1_to_writeback,
 371             d_out => loadstore1_to_dcache,
 372             d_in => dcache_to_loadstore1,
 373             m_out => loadstore1_to_mmu,
 374             m_in => mmu_to_loadstore1,
 375             dc_stall => dcache_stall_out,
 376             log_out => log_data(149 downto 140)
 377             );
 378
 379     mmu_0: entity work.mmu
 380         port map (
 381             clk => clk,
 382             rst => core_rst,
 383             l_in => loadstore1_to_mmu,
 384             l_out => mmu_to_loadstore1,
 385             d_out => mmu_to_dcache,
 386             d_in => dcache_to_mmu,
 387             i_out => mmu_to_icache
 388             );
 389
 390     dcache_0: entity work.dcache
 391         generic map(
 392             LINE_SIZE => 64,
 393             NUM_LINES => 64,
 394             NUM_WAYS => 2,
 395             LOG_LENGTH => LOG_LENGTH
 396             )
 397         port map (
 398             clk => clk,
 399             rst => rst_dcache,
 400             d_in => loadstore1_to_dcache,
 401             d_out => dcache_to_loadstore1,
 402             m_in => mmu_to_dcache,
 403             m_out => dcache_to_mmu,
 404             stall_out => dcache_stall_out,
 405             wishbone_in => wishbone_data_in,
 406             wishbone_out => wishbone_data_out,
 407             log_out => log_data(170 downto 151)
 408             );
 409
 410     writeback_0: entity work.writeback
 411         port map (
 412             clk => clk,
 413             e_in => execute1_to_writeback,
 414             l_in => loadstore1_to_writeback,
 415             fp_in => fpu_to_writeback,
 416             w_out => writeback_to_register_file,
 417             c_out => writeback_to_cr_file,
 418             complete_out => complete
 419             );
 420
 421     log_data(150) <= '0';
 422     log_data(139 downto 135) <= "00000";
 423
 424     debug_0: entity work.core_debug
 425         generic map (
 426             LOG_LENGTH => LOG_LENGTH
 427             )
 428         port map (
 429             clk => clk,
 430             rst => rst_dbg,
 431             dmi_addr => dmi_addr,
 432             dmi_din => dmi_din,
 433             dmi_dout => dmi_dout,
 434             dmi_req => dmi_req,
 435             dmi_wr => dmi_wr,
 436             dmi_ack => dmi_ack,
 437             core_stop => dbg_core_stop,
 438             core_rst => dbg_core_rst,
 439             icache_rst => dbg_icache_rst,
 440             terminate => terminate,
 441             core_stopped => dbg_core_is_stopped,
 442             nia => fetch1_to_icache.nia,
 443             msr => msr,
 444             dbg_gpr_req => dbg_gpr_req,
 445             dbg_gpr_ack => dbg_gpr_ack,
 446             dbg_gpr_addr => dbg_gpr_addr,
 447             dbg_gpr_data => dbg_gpr_data,
 448             log_data => log_data,
 449             log_read_addr => log_rd_addr,
 450             log_read_data => log_rd_data,
 451             log_write_addr => log_wr_addr,
 452             terminated_out => terminated_out
 453             );
 454
 455 end behave;