core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false;
  12         DISABLE_FLATTEN : boolean := false;
  13         EX1_BYPASS : boolean := true;
  14         HAS_FPU : boolean := true;
  15         HAS_BTC : boolean := true;
  16         ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
  17         LOG_LENGTH : natural := 512
  18         );
  19     port (
  20         clk          : in std_ulogic;
  21         rst          : in std_ulogic;
  22
  23         -- Alternate reset (0xffff0000) for use by DRAM init fw
  24         alt_reset    : in std_ulogic;
  25
  26         -- Wishbone interface
  27         wishbone_insn_in  : in wishbone_slave_out;
  28         wishbone_insn_out : out wishbone_master_out;
  29
  30         wishbone_data_in  : in wishbone_slave_out;
  31         wishbone_data_out : out wishbone_master_out;
  32
  33         dmi_addr        : in std_ulogic_vector(3 downto 0);
  34         dmi_din         : in std_ulogic_vector(63 downto 0);
  35         dmi_dout        : out std_ulogic_vector(63 downto 0);
  36         dmi_req         : in std_ulogic;
  37         dmi_wr          : in std_ulogic;
  38         dmi_ack         : out std_ulogic;
  39
  40         ext_irq         : in std_ulogic;
  41
  42         terminated_out   : out std_logic
  43         );
  44 end core;
  45
  46 architecture behave of core is
  47     -- icache signals
  48     signal fetch1_to_icache : Fetch1ToIcacheType;
  49     signal icache_to_decode1 : IcacheToDecode1Type;
  50     signal mmu_to_icache : MmuToIcacheType;
  51
  52     -- decode signals
  53     signal decode1_to_decode2: Decode1ToDecode2Type;
  54     signal decode1_to_fetch1: Decode1ToFetch1Type;
  55     signal decode2_to_execute1: Decode2ToExecute1Type;
  56
  57     -- register file signals
  58     signal register_file_to_decode2: RegisterFileToDecode2Type;
  59     signal decode2_to_register_file: Decode2ToRegisterFileType;
  60     signal writeback_to_register_file: WritebackToRegisterFileType;
  61
  62     -- CR file signals
  63     signal decode2_to_cr_file: Decode2ToCrFileType;
  64     signal cr_file_to_decode2: CrFileToDecode2Type;
  65     signal writeback_to_cr_file: WritebackToCrFileType;
  66
  67     -- execute signals
  68     signal execute1_to_writeback: Execute1ToWritebackType;
  69     signal execute1_to_fetch1: Execute1ToFetch1Type;
  70     signal execute1_bypass: bypass_data_t;
  71     signal execute1_cr_bypass: cr_bypass_data_t;
  72
  73     -- load store signals
  74     signal execute1_to_loadstore1: Execute1ToLoadstore1Type;
  75     signal loadstore1_to_execute1: Loadstore1ToExecute1Type;
  76     signal loadstore1_to_writeback: Loadstore1ToWritebackType;
  77     signal loadstore1_to_mmu: Loadstore1ToMmuType;
  78     signal mmu_to_loadstore1: MmuToLoadstore1Type;
  79
  80     -- dcache signals
  81     signal loadstore1_to_dcache: Loadstore1ToDcacheType;
  82     signal dcache_to_loadstore1: DcacheToLoadstore1Type;
  83     signal mmu_to_dcache: MmuToDcacheType;
  84     signal dcache_to_mmu: DcacheToMmuType;
  85
  86     -- FPU signals
  87     signal execute1_to_fpu: Execute1ToFPUType;
  88     signal fpu_to_execute1: FPUToExecute1Type;
  89     signal fpu_to_writeback: FPUToWritebackType;
  90
  91     -- local signals
  92     signal fetch1_stall_in : std_ulogic;
  93     signal icache_stall_out : std_ulogic;
  94     signal icache_stall_in : std_ulogic;
  95     signal decode1_stall_in : std_ulogic;
  96     signal decode1_busy     : std_ulogic;
  97     signal decode2_busy_in : std_ulogic;
  98     signal decode2_stall_out : std_ulogic;
  99     signal ex1_icache_inval: std_ulogic;
 100     signal ex1_busy_out: std_ulogic;
 101     signal dcache_stall_out: std_ulogic;
 102
 103     signal flush: std_ulogic;
 104     signal decode1_flush: std_ulogic;
 105     signal fetch1_flush: std_ulogic;
 106
 107     signal complete: instr_tag_t;
 108     signal terminate: std_ulogic;
 109     signal core_rst: std_ulogic;
 110     signal icache_inv: std_ulogic;
 111
 112     -- Delayed/Latched resets and alt_reset
 113     signal rst_fetch1  : std_ulogic := '1';
 114     signal rst_fetch2  : std_ulogic := '1';
 115     signal rst_icache  : std_ulogic := '1';
 116     signal rst_dcache  : std_ulogic := '1';
 117     signal rst_dec1    : std_ulogic := '1';
 118     signal rst_dec2    : std_ulogic := '1';
 119     signal rst_ex1     : std_ulogic := '1';
 120     signal rst_fpu     : std_ulogic := '1';
 121     signal rst_ls1     : std_ulogic := '1';
 122     signal rst_dbg     : std_ulogic := '1';
 123     signal alt_reset_d : std_ulogic;
 124
 125     signal sim_cr_dump: std_ulogic;
 126
 127     -- Debug actions
 128     signal dbg_core_stop: std_ulogic;
 129     signal dbg_core_rst: std_ulogic;
 130     signal dbg_icache_rst: std_ulogic;
 131
 132     signal dbg_gpr_req : std_ulogic;
 133     signal dbg_gpr_ack : std_ulogic;
 134     signal dbg_gpr_addr : gspr_index_t;
 135     signal dbg_gpr_data : std_ulogic_vector(63 downto 0);
 136
 137     signal msr : std_ulogic_vector(63 downto 0);
 138
 139     -- Debug status
 140     signal dbg_core_is_stopped: std_ulogic;
 141
 142     -- Logging signals
 143     signal log_data    : std_ulogic_vector(255 downto 0);
 144     signal log_rd_addr : std_ulogic_vector(31 downto 0);
 145     signal log_wr_addr : std_ulogic_vector(31 downto 0);
 146     signal log_rd_data : std_ulogic_vector(63 downto 0);
 147
 148     function keep_h(disable : boolean) return string is
 149     begin
 150         if disable then
 151             return "yes";
 152         else
 153             return "no";
 154         end if;
 155     end function;
 156     attribute keep_hierarchy : string;
 157     attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
 158     attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
 159     attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
 160     attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
 161     attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
 162     attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
 163     attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
 164     attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
 165     attribute keep_hierarchy of mmu_0 : label is keep_h(DISABLE_FLATTEN);
 166     attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
 167     attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
 168     attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
 169 begin
 170
 171     core_rst <= dbg_core_rst or rst;
 172
 173     resets: process(clk)
 174     begin
 175         if rising_edge(clk) then
 176             rst_fetch1  <= core_rst;
 177             rst_fetch2  <= core_rst;
 178             rst_icache  <= core_rst;
 179             rst_dcache  <= core_rst;
 180             rst_dec1    <= core_rst;
 181             rst_dec2    <= core_rst;
 182             rst_ex1     <= core_rst;
 183             rst_fpu     <= core_rst;
 184             rst_ls1     <= core_rst;
 185             rst_dbg     <= rst;
 186             alt_reset_d <= alt_reset;
 187         end if;
 188     end process;
 189
 190     fetch1_0: entity work.fetch1
 191         generic map (
 192             RESET_ADDRESS => (others => '0'),
 193             ALT_RESET_ADDRESS => ALT_RESET_ADDRESS,
 194             HAS_BTC => HAS_BTC
 195             )
 196         port map (
 197             clk => clk,
 198             rst => rst_fetch1,
 199             alt_reset_in => alt_reset_d,
 200             stall_in => fetch1_stall_in,
 201             flush_in => fetch1_flush,
 202             inval_btc => ex1_icache_inval or mmu_to_icache.tlbie,
 203             stop_in => dbg_core_stop,
 204             d_in => decode1_to_fetch1,
 205             e_in => execute1_to_fetch1,
 206             i_out => fetch1_to_icache,
 207             log_out => log_data(42 downto 0)
 208             );
 209
 210     fetch1_stall_in <= icache_stall_out or decode1_busy;
 211     fetch1_flush <= flush or decode1_flush;
 212
 213     icache_0: entity work.icache
 214         generic map(
 215             SIM => SIM,
 216             LINE_SIZE => 64,
 217             NUM_LINES => 64,
 218             NUM_WAYS => 2,
 219             LOG_LENGTH => LOG_LENGTH
 220             )
 221         port map(
 222             clk => clk,
 223             rst => rst_icache,
 224             i_in => fetch1_to_icache,
 225             i_out => icache_to_decode1,
 226             m_in => mmu_to_icache,
 227             flush_in => fetch1_flush,
 228             inval_in => dbg_icache_rst or ex1_icache_inval,
 229             stall_in => icache_stall_in,
 230             stall_out => icache_stall_out,
 231             wishbone_out => wishbone_insn_out,
 232             wishbone_in => wishbone_insn_in,
 233             log_out => log_data(96 downto 43)
 234             );
 235
 236     icache_stall_in <= decode1_busy;
 237
 238     decode1_0: entity work.decode1
 239         generic map(
 240             HAS_FPU => HAS_FPU,
 241             LOG_LENGTH => LOG_LENGTH
 242             )
 243         port map (
 244             clk => clk,
 245             rst => rst_dec1,
 246             stall_in => decode1_stall_in,
 247             flush_in => flush,
 248             flush_out => decode1_flush,
 249             busy_out => decode1_busy,
 250             f_in => icache_to_decode1,
 251             d_out => decode1_to_decode2,
 252             f_out => decode1_to_fetch1,
 253             log_out => log_data(109 downto 97)
 254             );
 255
 256     decode1_stall_in <= decode2_stall_out;
 257
 258     decode2_0: entity work.decode2
 259         generic map (
 260             EX1_BYPASS => EX1_BYPASS,
 261             HAS_FPU => HAS_FPU,
 262             LOG_LENGTH => LOG_LENGTH
 263             )
 264         port map (
 265             clk => clk,
 266             rst => rst_dec2,
 267             busy_in => decode2_busy_in,
 268             stall_out => decode2_stall_out,
 269             flush_in => flush,
 270             complete_in => complete,
 271             stopped_out => dbg_core_is_stopped,
 272             d_in => decode1_to_decode2,
 273             e_out => decode2_to_execute1,
 274             r_in => register_file_to_decode2,
 275             r_out => decode2_to_register_file,
 276             c_in => cr_file_to_decode2,
 277             c_out => decode2_to_cr_file,
 278             execute_bypass => execute1_bypass,
 279             execute_cr_bypass => execute1_cr_bypass,
 280             log_out => log_data(119 downto 110)
 281             );
 282     decode2_busy_in <= ex1_busy_out;
 283
 284     register_file_0: entity work.register_file
 285         generic map (
 286             SIM => SIM,
 287             HAS_FPU => HAS_FPU,
 288             LOG_LENGTH => LOG_LENGTH
 289             )
 290         port map (
 291             clk => clk,
 292             d_in => decode2_to_register_file,
 293             d_out => register_file_to_decode2,
 294             w_in => writeback_to_register_file,
 295             dbg_gpr_req => dbg_gpr_req,
 296             dbg_gpr_ack => dbg_gpr_ack,
 297             dbg_gpr_addr => dbg_gpr_addr,
 298             dbg_gpr_data => dbg_gpr_data,
 299             sim_dump => terminate,
 300             sim_dump_done => sim_cr_dump,
 301             log_out => log_data(255 downto 184)
 302             );
 303
 304     cr_file_0: entity work.cr_file
 305         generic map (
 306             SIM => SIM,
 307             LOG_LENGTH => LOG_LENGTH
 308             )
 309         port map (
 310             clk => clk,
 311             d_in => decode2_to_cr_file,
 312             d_out => cr_file_to_decode2,
 313             w_in => writeback_to_cr_file,
 314             sim_dump => sim_cr_dump,
 315             log_out => log_data(183 downto 171)
 316             );
 317
 318     execute1_0: entity work.execute1
 319         generic map (
 320             EX1_BYPASS => EX1_BYPASS,
 321             HAS_FPU => HAS_FPU,
 322             LOG_LENGTH => LOG_LENGTH
 323             )
 324         port map (
 325             clk => clk,
 326             rst => rst_ex1,
 327             flush_out => flush,
 328             busy_out => ex1_busy_out,
 329             e_in => decode2_to_execute1,
 330             l_in => loadstore1_to_execute1,
 331             fp_in => fpu_to_execute1,
 332             ext_irq_in => ext_irq,
 333             l_out => execute1_to_loadstore1,
 334             f_out => execute1_to_fetch1,
 335             fp_out => execute1_to_fpu,
 336             e_out => execute1_to_writeback,
 337             bypass_data => execute1_bypass,
 338             bypass_cr_data => execute1_cr_bypass,
 339             icache_inval => ex1_icache_inval,
 340             dbg_msr_out => msr,
 341             terminate_out => terminate,
 342             log_out => log_data(134 downto 120),
 343             log_rd_addr => log_rd_addr,
 344             log_rd_data => log_rd_data,
 345             log_wr_addr => log_wr_addr
 346             );
 347
 348     with_fpu: if HAS_FPU generate
 349     begin
 350         fpu_0: entity work.fpu
 351             port map (
 352                 clk => clk,
 353                 rst => rst_fpu,
 354                 e_in => execute1_to_fpu,
 355                 e_out => fpu_to_execute1,
 356                 w_out => fpu_to_writeback
 357                 );
 358     end generate;
 359
 360     no_fpu: if not HAS_FPU generate
 361     begin
 362         fpu_to_execute1 <= FPUToExecute1Init;
 363         fpu_to_writeback <= FPUToWritebackInit;
 364     end generate;
 365
 366     loadstore1_0: entity work.loadstore1
 367         generic map (
 368             HAS_FPU => HAS_FPU,
 369             LOG_LENGTH => LOG_LENGTH
 370             )
 371         port map (
 372             clk => clk,
 373             rst => rst_ls1,
 374             l_in => execute1_to_loadstore1,
 375             e_out => loadstore1_to_execute1,
 376             l_out => loadstore1_to_writeback,
 377             d_out => loadstore1_to_dcache,
 378             d_in => dcache_to_loadstore1,
 379             m_out => loadstore1_to_mmu,
 380             m_in => mmu_to_loadstore1,
 381             dc_stall => dcache_stall_out,
 382             log_out => log_data(149 downto 140)
 383             );
 384
 385     mmu_0: entity work.mmu
 386         port map (
 387             clk => clk,
 388             rst => core_rst,
 389             l_in => loadstore1_to_mmu,
 390             l_out => mmu_to_loadstore1,
 391             d_out => mmu_to_dcache,
 392             d_in => dcache_to_mmu,
 393             i_out => mmu_to_icache
 394             );
 395
 396     dcache_0: entity work.dcache
 397         generic map(
 398             LINE_SIZE => 64,
 399             NUM_LINES => 64,
 400             NUM_WAYS => 2,
 401             LOG_LENGTH => LOG_LENGTH
 402             )
 403         port map (
 404             clk => clk,
 405             rst => rst_dcache,
 406             d_in => loadstore1_to_dcache,
 407             d_out => dcache_to_loadstore1,
 408             m_in => mmu_to_dcache,
 409             m_out => dcache_to_mmu,
 410             stall_out => dcache_stall_out,
 411             wishbone_in => wishbone_data_in,
 412             wishbone_out => wishbone_data_out,
 413             log_out => log_data(170 downto 151)
 414             );
 415
 416     writeback_0: entity work.writeback
 417         port map (
 418             clk => clk,
 419             e_in => execute1_to_writeback,
 420             l_in => loadstore1_to_writeback,
 421             fp_in => fpu_to_writeback,
 422             w_out => writeback_to_register_file,
 423             c_out => writeback_to_cr_file,
 424             complete_out => complete
 425             );
 426
 427     log_data(150) <= '0';
 428     log_data(139 downto 135) <= "00000";
 429
 430     debug_0: entity work.core_debug
 431         generic map (
 432             LOG_LENGTH => LOG_LENGTH
 433             )
 434         port map (
 435             clk => clk,
 436             rst => rst_dbg,
 437             dmi_addr => dmi_addr,
 438             dmi_din => dmi_din,
 439             dmi_dout => dmi_dout,
 440             dmi_req => dmi_req,
 441             dmi_wr => dmi_wr,
 442             dmi_ack => dmi_ack,
 443             core_stop => dbg_core_stop,
 444             core_rst => dbg_core_rst,
 445             icache_rst => dbg_icache_rst,
 446             terminate => terminate,
 447             core_stopped => dbg_core_is_stopped,
 448             nia => fetch1_to_icache.nia,
 449             msr => msr,
 450             dbg_gpr_req => dbg_gpr_req,
 451             dbg_gpr_ack => dbg_gpr_ack,
 452             dbg_gpr_addr => dbg_gpr_addr,
 453             dbg_gpr_data => dbg_gpr_data,
 454             log_data => log_data,
 455             log_read_addr => log_rd_addr,
 456             log_read_data => log_rd_data,
 457             log_write_addr => log_wr_addr,
 458             terminated_out => terminated_out
 459             );
 460
 461 end behave;