core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false;
  12         DISABLE_FLATTEN : boolean := false;
  13         EX1_BYPASS : boolean := true;
  14         HAS_FPU : boolean := true;
  15         HAS_BTC : boolean := true;
  16         RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
  17         ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
  18         LOG_LENGTH : natural := 512
  19         );
  20     port (
  21         clk          : in std_ulogic;
  22         rst          : in std_ulogic;
  23
  24         -- Alternate reset (0xffff0000) for use by DRAM init fw
  25         alt_reset    : in std_ulogic;
  26
  27         -- Wishbone interface
  28         wishbone_insn_in  : in wishbone_slave_out;
  29         wishbone_insn_out : out wishbone_master_out;
  30
  31         wishbone_data_in  : in wishbone_slave_out;
  32         wishbone_data_out : out wishbone_master_out;
  33
  34         dmi_addr        : in std_ulogic_vector(3 downto 0);
  35         dmi_din         : in std_ulogic_vector(63 downto 0);
  36         dmi_dout        : out std_ulogic_vector(63 downto 0);
  37         dmi_req         : in std_ulogic;
  38         dmi_wr          : in std_ulogic;
  39         dmi_ack         : out std_ulogic;
  40
  41         ext_irq         : in std_ulogic;
  42
  43         terminated_out   : out std_logic;
  44
  45     -- for verilator debugging
  46     nia_req: out std_ulogic;
  47     nia: out std_ulogic_vector(63 downto 0);
  48     msr_o: out std_ulogic_vector(63 downto 0);
  49     insn: out std_ulogic_vector(31 downto 0);
  50     ldst_req: out std_ulogic;
  51     ldst_addr: out std_ulogic_vector(63 downto 0)
  52         );
  53 end core;
  54
  55 architecture behave of core is
  56     -- icache signals
  57     signal fetch1_to_icache : Fetch1ToIcacheType;
  58     signal writeback_to_fetch1: WritebackToFetch1Type;
  59     signal icache_to_decode1 : IcacheToDecode1Type;
  60     signal mmu_to_icache : MmuToIcacheType;
  61
  62     -- decode signals
  63     signal decode1_to_decode2: Decode1ToDecode2Type;
  64     signal decode1_to_fetch1: Decode1ToFetch1Type;
  65     signal decode2_to_execute1: Decode2ToExecute1Type;
  66
  67     -- register file signals
  68     signal register_file_to_decode2: RegisterFileToDecode2Type;
  69     signal decode2_to_register_file: Decode2ToRegisterFileType;
  70     signal writeback_to_register_file: WritebackToRegisterFileType;
  71
  72     -- CR file signals
  73     signal decode2_to_cr_file: Decode2ToCrFileType;
  74     signal cr_file_to_decode2: CrFileToDecode2Type;
  75     signal writeback_to_cr_file: WritebackToCrFileType;
  76
  77     -- execute signals
  78     signal execute1_to_writeback: Execute1ToWritebackType;
  79     signal execute1_bypass: bypass_data_t;
  80     signal execute1_cr_bypass: cr_bypass_data_t;
  81
  82     -- load store signals
  83     signal execute1_to_loadstore1: Execute1ToLoadstore1Type;
  84     signal loadstore1_to_execute1: Loadstore1ToExecute1Type;
  85     signal loadstore1_to_writeback: Loadstore1ToWritebackType;
  86     signal loadstore1_to_mmu: Loadstore1ToMmuType;
  87     signal mmu_to_loadstore1: MmuToLoadstore1Type;
  88
  89     -- dcache signals
  90     signal loadstore1_to_dcache: Loadstore1ToDcacheType;
  91     signal dcache_to_loadstore1: DcacheToLoadstore1Type;
  92     signal mmu_to_dcache: MmuToDcacheType;
  93     signal dcache_to_mmu: DcacheToMmuType;
  94
  95     -- FPU signals
  96     signal execute1_to_fpu: Execute1ToFPUType;
  97     signal fpu_to_execute1: FPUToExecute1Type;
  98     signal fpu_to_writeback: FPUToWritebackType;
  99
 100     -- local signals
 101     signal fetch1_stall_in : std_ulogic;
 102     signal icache_stall_out : std_ulogic;
 103     signal icache_stall_in : std_ulogic;
 104     signal decode1_stall_in : std_ulogic;
 105     signal decode1_busy     : std_ulogic;
 106     signal decode2_busy_in : std_ulogic;
 107     signal decode2_stall_out : std_ulogic;
 108     signal ex1_icache_inval: std_ulogic;
 109     signal ex1_busy_out: std_ulogic;
 110     signal dcache_stall_out: std_ulogic;
 111
 112     signal flush: std_ulogic;
 113     signal decode1_flush: std_ulogic;
 114     signal fetch1_flush: std_ulogic;
 115
 116     signal complete: instr_tag_t;
 117     signal terminate: std_ulogic;
 118     signal core_rst: std_ulogic;
 119     signal icache_inv: std_ulogic;
 120     signal do_interrupt: std_ulogic;
 121
 122     -- Delayed/Latched resets and alt_reset
 123     signal rst_fetch1  : std_ulogic := '1';
 124     signal rst_fetch2  : std_ulogic := '1';
 125     signal rst_icache  : std_ulogic := '1';
 126     signal rst_dcache  : std_ulogic := '1';
 127     signal rst_dec1    : std_ulogic := '1';
 128     signal rst_dec2    : std_ulogic := '1';
 129     signal rst_ex1     : std_ulogic := '1';
 130     signal rst_fpu     : std_ulogic := '1';
 131     signal rst_ls1     : std_ulogic := '1';
 132     signal rst_wback   : std_ulogic := '1';
 133     signal rst_dbg     : std_ulogic := '1';
 134     signal alt_reset_d : std_ulogic;
 135
 136     signal sim_cr_dump: std_ulogic;
 137
 138     -- Debug actions
 139     signal dbg_core_stop: std_ulogic;
 140     signal dbg_core_rst: std_ulogic;
 141     signal dbg_icache_rst: std_ulogic;
 142
 143     signal dbg_gpr_req : std_ulogic;
 144     signal dbg_gpr_ack : std_ulogic;
 145     signal dbg_gpr_addr : gspr_index_t;
 146     signal dbg_gpr_data : std_ulogic_vector(63 downto 0);
 147
 148     signal msr : std_ulogic_vector(63 downto 0);
 149
 150     -- Debug status
 151     signal dbg_core_is_stopped: std_ulogic;
 152
 153     -- Logging signals
 154     signal log_data    : std_ulogic_vector(255 downto 0);
 155     signal log_rd_addr : std_ulogic_vector(31 downto 0);
 156     signal log_wr_addr : std_ulogic_vector(31 downto 0);
 157     signal log_rd_data : std_ulogic_vector(63 downto 0);
 158
 159     function keep_h(disable : boolean) return string is
 160     begin
 161         if disable then
 162             return "yes";
 163         else
 164             return "no";
 165         end if;
 166     end function;
 167     attribute keep_hierarchy : string;
 168     attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
 169     attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
 170     attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
 171     attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
 172     attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
 173     attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
 174     attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
 175     attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
 176     attribute keep_hierarchy of mmu_0 : label is keep_h(DISABLE_FLATTEN);
 177     attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
 178     attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
 179     attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
 180 begin
 181
 182     core_rst <= dbg_core_rst or rst;
 183
 184     resets: process(clk)
 185     begin
 186         if rising_edge(clk) then
 187             rst_fetch1  <= core_rst;
 188             rst_fetch2  <= core_rst;
 189             rst_icache  <= core_rst;
 190             rst_dcache  <= core_rst;
 191             rst_dec1    <= core_rst;
 192             rst_dec2    <= core_rst;
 193             rst_ex1     <= core_rst;
 194             rst_fpu     <= core_rst;
 195             rst_ls1     <= core_rst;
 196             rst_wback   <= core_rst;
 197             rst_dbg     <= rst;
 198             alt_reset_d <= alt_reset;
 199         end if;
 200     end process;
 201
 202     fetch1_0: entity work.fetch1
 203         generic map (
 204             RESET_ADDRESS => RESET_ADDRESS,
 205             ALT_RESET_ADDRESS => ALT_RESET_ADDRESS,
 206             HAS_BTC => HAS_BTC
 207             )
 208         port map (
 209             clk => clk,
 210             rst => rst_fetch1,
 211             alt_reset_in => alt_reset_d,
 212             stall_in => fetch1_stall_in,
 213             flush_in => fetch1_flush,
 214             inval_btc => ex1_icache_inval or mmu_to_icache.tlbie,
 215             stop_in => dbg_core_stop,
 216             d_in => decode1_to_fetch1,
 217             w_in => writeback_to_fetch1,
 218             i_out => fetch1_to_icache,
 219             log_out => log_data(42 downto 0)
 220             );
 221
 222     fetch1_stall_in <= icache_stall_out or decode1_busy;
 223     fetch1_flush <= flush or decode1_flush;
 224
 225     icache_0: entity work.icache
 226         generic map(
 227             SIM => SIM,
 228             LINE_SIZE => 64,
 229             NUM_LINES => 64,
 230             NUM_WAYS => 2,
 231             LOG_LENGTH => LOG_LENGTH
 232             )
 233         port map(
 234             clk => clk,
 235             rst => rst_icache,
 236             i_in => fetch1_to_icache,
 237             i_out => icache_to_decode1,
 238             m_in => mmu_to_icache,
 239             flush_in => fetch1_flush,
 240             inval_in => dbg_icache_rst or ex1_icache_inval,
 241             stall_in => icache_stall_in,
 242             stall_out => icache_stall_out,
 243             wishbone_out => wishbone_insn_out,
 244             wishbone_in => wishbone_insn_in,
 245             log_out => log_data(96 downto 43)
 246             );
 247
 248     icache_stall_in <= decode1_busy;
 249
 250     decode1_0: entity work.decode1
 251         generic map(
 252             HAS_FPU => HAS_FPU,
 253             LOG_LENGTH => LOG_LENGTH
 254             )
 255         port map (
 256             clk => clk,
 257             rst => rst_dec1,
 258             stall_in => decode1_stall_in,
 259             flush_in => flush,
 260             flush_out => decode1_flush,
 261             busy_out => decode1_busy,
 262             f_in => icache_to_decode1,
 263             d_out => decode1_to_decode2,
 264             f_out => decode1_to_fetch1,
 265             log_out => log_data(109 downto 97)
 266             );
 267
 268     decode1_stall_in <= decode2_stall_out;
 269
 270     decode2_0: entity work.decode2
 271         generic map (
 272             EX1_BYPASS => EX1_BYPASS,
 273             HAS_FPU => HAS_FPU,
 274             LOG_LENGTH => LOG_LENGTH
 275             )
 276         port map (
 277             clk => clk,
 278             rst => rst_dec2,
 279             busy_in => decode2_busy_in,
 280             stall_out => decode2_stall_out,
 281             flush_in => flush,
 282             complete_in => complete,
 283             stopped_out => dbg_core_is_stopped,
 284             d_in => decode1_to_decode2,
 285             e_out => decode2_to_execute1,
 286             r_in => register_file_to_decode2,
 287             r_out => decode2_to_register_file,
 288             c_in => cr_file_to_decode2,
 289             c_out => decode2_to_cr_file,
 290             execute_bypass => execute1_bypass,
 291             execute_cr_bypass => execute1_cr_bypass,
 292             log_out => log_data(119 downto 110)
 293             );
 294     decode2_busy_in <= ex1_busy_out;
 295
 296     register_file_0: entity work.register_file
 297         generic map (
 298             SIM => SIM,
 299             HAS_FPU => HAS_FPU,
 300             LOG_LENGTH => LOG_LENGTH
 301             )
 302         port map (
 303             clk => clk,
 304             d_in => decode2_to_register_file,
 305             d_out => register_file_to_decode2,
 306             w_in => writeback_to_register_file,
 307             dbg_gpr_req => dbg_gpr_req,
 308             dbg_gpr_ack => dbg_gpr_ack,
 309             dbg_gpr_addr => dbg_gpr_addr,
 310             dbg_gpr_data => dbg_gpr_data,
 311             sim_dump => terminate,
 312             sim_dump_done => sim_cr_dump,
 313             log_out => log_data(255 downto 184)
 314             );
 315
 316     cr_file_0: entity work.cr_file
 317         generic map (
 318             SIM => SIM,
 319             LOG_LENGTH => LOG_LENGTH
 320             )
 321         port map (
 322             clk => clk,
 323             d_in => decode2_to_cr_file,
 324             d_out => cr_file_to_decode2,
 325             w_in => writeback_to_cr_file,
 326             sim_dump => sim_cr_dump,
 327             log_out => log_data(183 downto 171)
 328             );
 329
 330     execute1_0: entity work.execute1
 331         generic map (
 332             EX1_BYPASS => EX1_BYPASS,
 333             HAS_FPU => HAS_FPU,
 334             LOG_LENGTH => LOG_LENGTH
 335             )
 336         port map (
 337             clk => clk,
 338             rst => rst_ex1,
 339             flush_in => flush,
 340             busy_out => ex1_busy_out,
 341             e_in => decode2_to_execute1,
 342             l_in => loadstore1_to_execute1,
 343             fp_in => fpu_to_execute1,
 344             ext_irq_in => ext_irq,
 345             interrupt_in => do_interrupt,
 346             l_out => execute1_to_loadstore1,
 347             fp_out => execute1_to_fpu,
 348             e_out => execute1_to_writeback,
 349             bypass_data => execute1_bypass,
 350             bypass_cr_data => execute1_cr_bypass,
 351             icache_inval => ex1_icache_inval,
 352             dbg_msr_out => msr,
 353             terminate_out => terminate,
 354             log_out => log_data(134 downto 120),
 355             log_rd_addr => log_rd_addr,
 356             log_rd_data => log_rd_data,
 357             log_wr_addr => log_wr_addr
 358             );
 359
 360     with_fpu: if HAS_FPU generate
 361     begin
 362         fpu_0: entity work.fpu
 363             port map (
 364                 clk => clk,
 365                 rst => rst_fpu,
 366                 e_in => execute1_to_fpu,
 367                 e_out => fpu_to_execute1,
 368                 w_out => fpu_to_writeback
 369                 );
 370     end generate;
 371
 372     no_fpu: if not HAS_FPU generate
 373     begin
 374         fpu_to_execute1 <= FPUToExecute1Init;
 375         fpu_to_writeback <= FPUToWritebackInit;
 376     end generate;
 377
 378     loadstore1_0: entity work.loadstore1
 379         generic map (
 380             HAS_FPU => HAS_FPU,
 381             LOG_LENGTH => LOG_LENGTH
 382             )
 383         port map (
 384             clk => clk,
 385             rst => rst_ls1,
 386             l_in => execute1_to_loadstore1,
 387             e_out => loadstore1_to_execute1,
 388             l_out => loadstore1_to_writeback,
 389             d_out => loadstore1_to_dcache,
 390             d_in => dcache_to_loadstore1,
 391             m_out => loadstore1_to_mmu,
 392             m_in => mmu_to_loadstore1,
 393             dc_stall => dcache_stall_out,
 394             log_out => log_data(149 downto 140)
 395             );
 396
 397     mmu_0: entity work.mmu
 398         port map (
 399             clk => clk,
 400             rst => core_rst,
 401             l_in => loadstore1_to_mmu,
 402             l_out => mmu_to_loadstore1,
 403             d_out => mmu_to_dcache,
 404             d_in => dcache_to_mmu,
 405             i_out => mmu_to_icache
 406             );
 407
 408     dcache_0: entity work.dcache
 409         generic map(
 410             LINE_SIZE => 64,
 411             NUM_LINES => 64,
 412             NUM_WAYS => 2,
 413             LOG_LENGTH => LOG_LENGTH
 414             )
 415         port map (
 416             clk => clk,
 417             rst => rst_dcache,
 418             d_in => loadstore1_to_dcache,
 419             d_out => dcache_to_loadstore1,
 420             m_in => mmu_to_dcache,
 421             m_out => dcache_to_mmu,
 422             stall_out => dcache_stall_out,
 423             wishbone_in => wishbone_data_in,
 424             wishbone_out => wishbone_data_out,
 425             log_out => log_data(170 downto 151)
 426             );
 427
 428     writeback_0: entity work.writeback
 429         port map (
 430             clk => clk,
 431             rst => rst_wback,
 432             flush_out => flush,
 433             e_in => execute1_to_writeback,
 434             l_in => loadstore1_to_writeback,
 435             fp_in => fpu_to_writeback,
 436             w_out => writeback_to_register_file,
 437             c_out => writeback_to_cr_file,
 438             f_out => writeback_to_fetch1,
 439             interrupt_out => do_interrupt,
 440             complete_out => complete
 441             );
 442
 443     log_data(150) <= '0';
 444     log_data(139 downto 135) <= "00000";
 445
 446     -- snoop and report instruction being executed
 447     nia <= icache_to_decode1.nia;
 448     msr_o <= msr;
 449     insn <= icache_to_decode1.insn;
 450     nia_req <= icache_to_decode1.valid and fetch1_to_icache.sequential;
 451     -- hmmm....
 452     ldst_req <= execute1_to_loadstore1.valid;
 453     ldst_addr <= std_ulogic_vector(unsigned(execute1_to_loadstore1.addr1) +
 454                                    unsigned(execute1_to_loadstore1.addr2))
 455                   when execute1_to_loadstore1.valid = '1' else (others => '0');
 456
 457     debug_0: entity work.core_debug
 458
 459         generic map (
 460             LOG_LENGTH => LOG_LENGTH
 461             )
 462         port map (
 463             clk => clk,
 464             rst => rst_dbg,
 465             dmi_addr => dmi_addr,
 466             dmi_din => dmi_din,
 467             dmi_dout => dmi_dout,
 468             dmi_req => dmi_req,
 469             dmi_wr => dmi_wr,
 470             dmi_ack => dmi_ack,
 471             core_stop => dbg_core_stop,
 472             core_rst => dbg_core_rst,
 473             icache_rst => dbg_icache_rst,
 474             terminate => terminate,
 475             core_stopped => dbg_core_is_stopped,
 476             nia => fetch1_to_icache.nia,
 477             msr => msr,
 478             dbg_gpr_req => dbg_gpr_req,
 479             dbg_gpr_ack => dbg_gpr_ack,
 480             dbg_gpr_addr => dbg_gpr_addr,
 481             dbg_gpr_data => dbg_gpr_data,
 482             log_data => log_data,
 483             log_read_addr => log_rd_addr,
 484             log_read_data => log_rd_data,
 485             log_write_addr => log_wr_addr,
 486             terminated_out => terminated_out
 487             );
 488
 489 end behave;