core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false;
  12         DISABLE_FLATTEN : boolean := false;
  13         EX1_BYPASS : boolean := true;
  14         HAS_FPU : boolean := true;
  15         HAS_BTC : boolean := true;
  16         ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
  17         LOG_LENGTH : natural := 512
  18         );
  19     port (
  20         clk          : in std_ulogic;
  21         rst          : in std_ulogic;
  22
  23         -- Alternate reset (0xffff0000) for use by DRAM init fw
  24         alt_reset    : in std_ulogic;
  25
  26         -- Wishbone interface
  27         wishbone_insn_in  : in wishbone_slave_out;
  28         wishbone_insn_out : out wishbone_master_out;
  29
  30         wishbone_data_in  : in wishbone_slave_out;
  31         wishbone_data_out : out wishbone_master_out;
  32
  33         dmi_addr        : in std_ulogic_vector(3 downto 0);
  34         dmi_din         : in std_ulogic_vector(63 downto 0);
  35         dmi_dout        : out std_ulogic_vector(63 downto 0);
  36         dmi_req         : in std_ulogic;
  37         dmi_wr          : in std_ulogic;
  38         dmi_ack         : out std_ulogic;
  39
  40         ext_irq         : in std_ulogic;
  41
  42         terminated_out   : out std_logic
  43         );
  44 end core;
  45
  46 architecture behave of core is
  47     -- icache signals
  48     signal fetch1_to_icache : Fetch1ToIcacheType;
  49     signal writeback_to_fetch1: WritebackToFetch1Type;
  50     signal icache_to_decode1 : IcacheToDecode1Type;
  51     signal mmu_to_icache : MmuToIcacheType;
  52
  53     -- decode signals
  54     signal decode1_to_decode2: Decode1ToDecode2Type;
  55     signal decode1_to_fetch1: Decode1ToFetch1Type;
  56     signal decode2_to_execute1: Decode2ToExecute1Type;
  57
  58     -- register file signals
  59     signal register_file_to_decode2: RegisterFileToDecode2Type;
  60     signal decode2_to_register_file: Decode2ToRegisterFileType;
  61     signal writeback_to_register_file: WritebackToRegisterFileType;
  62
  63     -- CR file signals
  64     signal decode2_to_cr_file: Decode2ToCrFileType;
  65     signal cr_file_to_decode2: CrFileToDecode2Type;
  66     signal writeback_to_cr_file: WritebackToCrFileType;
  67
  68     -- execute signals
  69     signal execute1_to_writeback: Execute1ToWritebackType;
  70     signal execute1_bypass: bypass_data_t;
  71     signal execute1_cr_bypass: cr_bypass_data_t;
  72
  73     -- load store signals
  74     signal execute1_to_loadstore1: Execute1ToLoadstore1Type;
  75     signal loadstore1_to_execute1: Loadstore1ToExecute1Type;
  76     signal loadstore1_to_writeback: Loadstore1ToWritebackType;
  77     signal loadstore1_to_mmu: Loadstore1ToMmuType;
  78     signal mmu_to_loadstore1: MmuToLoadstore1Type;
  79
  80     -- dcache signals
  81     signal loadstore1_to_dcache: Loadstore1ToDcacheType;
  82     signal dcache_to_loadstore1: DcacheToLoadstore1Type;
  83     signal mmu_to_dcache: MmuToDcacheType;
  84     signal dcache_to_mmu: DcacheToMmuType;
  85
  86     -- FPU signals
  87     signal execute1_to_fpu: Execute1ToFPUType;
  88     signal fpu_to_execute1: FPUToExecute1Type;
  89     signal fpu_to_writeback: FPUToWritebackType;
  90
  91     -- local signals
  92     signal fetch1_stall_in : std_ulogic;
  93     signal icache_stall_out : std_ulogic;
  94     signal icache_stall_in : std_ulogic;
  95     signal decode1_stall_in : std_ulogic;
  96     signal decode1_busy     : std_ulogic;
  97     signal decode2_busy_in : std_ulogic;
  98     signal decode2_stall_out : std_ulogic;
  99     signal ex1_icache_inval: std_ulogic;
 100     signal ex1_busy_out: std_ulogic;
 101     signal dcache_stall_out: std_ulogic;
 102
 103     signal flush: std_ulogic;
 104     signal decode1_flush: std_ulogic;
 105     signal fetch1_flush: std_ulogic;
 106
 107     signal complete: instr_tag_t;
 108     signal terminate: std_ulogic;
 109     signal core_rst: std_ulogic;
 110     signal icache_inv: std_ulogic;
 111     signal do_interrupt: std_ulogic;
 112
 113     -- Delayed/Latched resets and alt_reset
 114     signal rst_fetch1  : std_ulogic := '1';
 115     signal rst_fetch2  : std_ulogic := '1';
 116     signal rst_icache  : std_ulogic := '1';
 117     signal rst_dcache  : std_ulogic := '1';
 118     signal rst_dec1    : std_ulogic := '1';
 119     signal rst_dec2    : std_ulogic := '1';
 120     signal rst_ex1     : std_ulogic := '1';
 121     signal rst_fpu     : std_ulogic := '1';
 122     signal rst_ls1     : std_ulogic := '1';
 123     signal rst_wback   : std_ulogic := '1';
 124     signal rst_dbg     : std_ulogic := '1';
 125     signal alt_reset_d : std_ulogic;
 126
 127     signal sim_cr_dump: std_ulogic;
 128
 129     -- Debug actions
 130     signal dbg_core_stop: std_ulogic;
 131     signal dbg_core_rst: std_ulogic;
 132     signal dbg_icache_rst: std_ulogic;
 133
 134     signal dbg_gpr_req : std_ulogic;
 135     signal dbg_gpr_ack : std_ulogic;
 136     signal dbg_gpr_addr : gspr_index_t;
 137     signal dbg_gpr_data : std_ulogic_vector(63 downto 0);
 138
 139     signal msr : std_ulogic_vector(63 downto 0);
 140
 141     -- Debug status
 142     signal dbg_core_is_stopped: std_ulogic;
 143
 144     -- Logging signals
 145     signal log_data    : std_ulogic_vector(255 downto 0);
 146     signal log_rd_addr : std_ulogic_vector(31 downto 0);
 147     signal log_wr_addr : std_ulogic_vector(31 downto 0);
 148     signal log_rd_data : std_ulogic_vector(63 downto 0);
 149
 150     function keep_h(disable : boolean) return string is
 151     begin
 152         if disable then
 153             return "yes";
 154         else
 155             return "no";
 156         end if;
 157     end function;
 158     attribute keep_hierarchy : string;
 159     attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
 160     attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
 161     attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
 162     attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
 163     attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
 164     attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
 165     attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
 166     attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
 167     attribute keep_hierarchy of mmu_0 : label is keep_h(DISABLE_FLATTEN);
 168     attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
 169     attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
 170     attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
 171 begin
 172
 173     core_rst <= dbg_core_rst or rst;
 174
 175     resets: process(clk)
 176     begin
 177         if rising_edge(clk) then
 178             rst_fetch1  <= core_rst;
 179             rst_fetch2  <= core_rst;
 180             rst_icache  <= core_rst;
 181             rst_dcache  <= core_rst;
 182             rst_dec1    <= core_rst;
 183             rst_dec2    <= core_rst;
 184             rst_ex1     <= core_rst;
 185             rst_fpu     <= core_rst;
 186             rst_ls1     <= core_rst;
 187             rst_wback   <= core_rst;
 188             rst_dbg     <= rst;
 189             alt_reset_d <= alt_reset;
 190         end if;
 191     end process;
 192
 193     fetch1_0: entity work.fetch1
 194         generic map (
 195             RESET_ADDRESS => (others => '0'),
 196             ALT_RESET_ADDRESS => ALT_RESET_ADDRESS,
 197             HAS_BTC => HAS_BTC
 198             )
 199         port map (
 200             clk => clk,
 201             rst => rst_fetch1,
 202             alt_reset_in => alt_reset_d,
 203             stall_in => fetch1_stall_in,
 204             flush_in => fetch1_flush,
 205             inval_btc => ex1_icache_inval or mmu_to_icache.tlbie,
 206             stop_in => dbg_core_stop,
 207             d_in => decode1_to_fetch1,
 208             w_in => writeback_to_fetch1,
 209             i_out => fetch1_to_icache,
 210             log_out => log_data(42 downto 0)
 211             );
 212
 213     fetch1_stall_in <= icache_stall_out or decode1_busy;
 214     fetch1_flush <= flush or decode1_flush;
 215
 216     icache_0: entity work.icache
 217         generic map(
 218             SIM => SIM,
 219             LINE_SIZE => 64,
 220             NUM_LINES => 64,
 221             NUM_WAYS => 2,
 222             LOG_LENGTH => LOG_LENGTH
 223             )
 224         port map(
 225             clk => clk,
 226             rst => rst_icache,
 227             i_in => fetch1_to_icache,
 228             i_out => icache_to_decode1,
 229             m_in => mmu_to_icache,
 230             flush_in => fetch1_flush,
 231             inval_in => dbg_icache_rst or ex1_icache_inval,
 232             stall_in => icache_stall_in,
 233             stall_out => icache_stall_out,
 234             wishbone_out => wishbone_insn_out,
 235             wishbone_in => wishbone_insn_in,
 236             log_out => log_data(96 downto 43)
 237             );
 238
 239     icache_stall_in <= decode1_busy;
 240
 241     decode1_0: entity work.decode1
 242         generic map(
 243             HAS_FPU => HAS_FPU,
 244             LOG_LENGTH => LOG_LENGTH
 245             )
 246         port map (
 247             clk => clk,
 248             rst => rst_dec1,
 249             stall_in => decode1_stall_in,
 250             flush_in => flush,
 251             flush_out => decode1_flush,
 252             busy_out => decode1_busy,
 253             f_in => icache_to_decode1,
 254             d_out => decode1_to_decode2,
 255             f_out => decode1_to_fetch1,
 256             log_out => log_data(109 downto 97)
 257             );
 258
 259     decode1_stall_in <= decode2_stall_out;
 260
 261     decode2_0: entity work.decode2
 262         generic map (
 263             EX1_BYPASS => EX1_BYPASS,
 264             HAS_FPU => HAS_FPU,
 265             LOG_LENGTH => LOG_LENGTH
 266             )
 267         port map (
 268             clk => clk,
 269             rst => rst_dec2,
 270             busy_in => decode2_busy_in,
 271             stall_out => decode2_stall_out,
 272             flush_in => flush,
 273             complete_in => complete,
 274             stopped_out => dbg_core_is_stopped,
 275             d_in => decode1_to_decode2,
 276             e_out => decode2_to_execute1,
 277             r_in => register_file_to_decode2,
 278             r_out => decode2_to_register_file,
 279             c_in => cr_file_to_decode2,
 280             c_out => decode2_to_cr_file,
 281             execute_bypass => execute1_bypass,
 282             execute_cr_bypass => execute1_cr_bypass,
 283             log_out => log_data(119 downto 110)
 284             );
 285     decode2_busy_in <= ex1_busy_out;
 286
 287     register_file_0: entity work.register_file
 288         generic map (
 289             SIM => SIM,
 290             HAS_FPU => HAS_FPU,
 291             LOG_LENGTH => LOG_LENGTH
 292             )
 293         port map (
 294             clk => clk,
 295             d_in => decode2_to_register_file,
 296             d_out => register_file_to_decode2,
 297             w_in => writeback_to_register_file,
 298             dbg_gpr_req => dbg_gpr_req,
 299             dbg_gpr_ack => dbg_gpr_ack,
 300             dbg_gpr_addr => dbg_gpr_addr,
 301             dbg_gpr_data => dbg_gpr_data,
 302             sim_dump => terminate,
 303             sim_dump_done => sim_cr_dump,
 304             log_out => log_data(255 downto 184)
 305             );
 306
 307     cr_file_0: entity work.cr_file
 308         generic map (
 309             SIM => SIM,
 310             LOG_LENGTH => LOG_LENGTH
 311             )
 312         port map (
 313             clk => clk,
 314             d_in => decode2_to_cr_file,
 315             d_out => cr_file_to_decode2,
 316             w_in => writeback_to_cr_file,
 317             sim_dump => sim_cr_dump,
 318             log_out => log_data(183 downto 171)
 319             );
 320
 321     execute1_0: entity work.execute1
 322         generic map (
 323             EX1_BYPASS => EX1_BYPASS,
 324             HAS_FPU => HAS_FPU,
 325             LOG_LENGTH => LOG_LENGTH
 326             )
 327         port map (
 328             clk => clk,
 329             rst => rst_ex1,
 330             flush_in => flush,
 331             busy_out => ex1_busy_out,
 332             e_in => decode2_to_execute1,
 333             l_in => loadstore1_to_execute1,
 334             fp_in => fpu_to_execute1,
 335             ext_irq_in => ext_irq,
 336             interrupt_in => do_interrupt,
 337             l_out => execute1_to_loadstore1,
 338             fp_out => execute1_to_fpu,
 339             e_out => execute1_to_writeback,
 340             bypass_data => execute1_bypass,
 341             bypass_cr_data => execute1_cr_bypass,
 342             icache_inval => ex1_icache_inval,
 343             dbg_msr_out => msr,
 344             terminate_out => terminate,
 345             log_out => log_data(134 downto 120),
 346             log_rd_addr => log_rd_addr,
 347             log_rd_data => log_rd_data,
 348             log_wr_addr => log_wr_addr
 349             );
 350
 351     with_fpu: if HAS_FPU generate
 352     begin
 353         fpu_0: entity work.fpu
 354             port map (
 355                 clk => clk,
 356                 rst => rst_fpu,
 357                 e_in => execute1_to_fpu,
 358                 e_out => fpu_to_execute1,
 359                 w_out => fpu_to_writeback
 360                 );
 361     end generate;
 362
 363     no_fpu: if not HAS_FPU generate
 364     begin
 365         fpu_to_execute1 <= FPUToExecute1Init;
 366         fpu_to_writeback <= FPUToWritebackInit;
 367     end generate;
 368
 369     loadstore1_0: entity work.loadstore1
 370         generic map (
 371             HAS_FPU => HAS_FPU,
 372             LOG_LENGTH => LOG_LENGTH
 373             )
 374         port map (
 375             clk => clk,
 376             rst => rst_ls1,
 377             l_in => execute1_to_loadstore1,
 378             e_out => loadstore1_to_execute1,
 379             l_out => loadstore1_to_writeback,
 380             d_out => loadstore1_to_dcache,
 381             d_in => dcache_to_loadstore1,
 382             m_out => loadstore1_to_mmu,
 383             m_in => mmu_to_loadstore1,
 384             dc_stall => dcache_stall_out,
 385             log_out => log_data(149 downto 140)
 386             );
 387
 388     mmu_0: entity work.mmu
 389         port map (
 390             clk => clk,
 391             rst => core_rst,
 392             l_in => loadstore1_to_mmu,
 393             l_out => mmu_to_loadstore1,
 394             d_out => mmu_to_dcache,
 395             d_in => dcache_to_mmu,
 396             i_out => mmu_to_icache
 397             );
 398
 399     dcache_0: entity work.dcache
 400         generic map(
 401             LINE_SIZE => 64,
 402             NUM_LINES => 64,
 403             NUM_WAYS => 2,
 404             LOG_LENGTH => LOG_LENGTH
 405             )
 406         port map (
 407             clk => clk,
 408             rst => rst_dcache,
 409             d_in => loadstore1_to_dcache,
 410             d_out => dcache_to_loadstore1,
 411             m_in => mmu_to_dcache,
 412             m_out => dcache_to_mmu,
 413             stall_out => dcache_stall_out,
 414             wishbone_in => wishbone_data_in,
 415             wishbone_out => wishbone_data_out,
 416             log_out => log_data(170 downto 151)
 417             );
 418
 419     writeback_0: entity work.writeback
 420         port map (
 421             clk => clk,
 422             rst => rst_wback,
 423             flush_out => flush,
 424             e_in => execute1_to_writeback,
 425             l_in => loadstore1_to_writeback,
 426             fp_in => fpu_to_writeback,
 427             w_out => writeback_to_register_file,
 428             c_out => writeback_to_cr_file,
 429             f_out => writeback_to_fetch1,
 430             interrupt_out => do_interrupt,
 431             complete_out => complete
 432             );
 433
 434     log_data(150) <= '0';
 435     log_data(139 downto 135) <= "00000";
 436
 437     debug_0: entity work.core_debug
 438         generic map (
 439             LOG_LENGTH => LOG_LENGTH
 440             )
 441         port map (
 442             clk => clk,
 443             rst => rst_dbg,
 444             dmi_addr => dmi_addr,
 445             dmi_din => dmi_din,
 446             dmi_dout => dmi_dout,
 447             dmi_req => dmi_req,
 448             dmi_wr => dmi_wr,
 449             dmi_ack => dmi_ack,
 450             core_stop => dbg_core_stop,
 451             core_rst => dbg_core_rst,
 452             icache_rst => dbg_icache_rst,
 453             terminate => terminate,
 454             core_stopped => dbg_core_is_stopped,
 455             nia => fetch1_to_icache.nia,
 456             msr => msr,
 457             dbg_gpr_req => dbg_gpr_req,
 458             dbg_gpr_ack => dbg_gpr_ack,
 459             dbg_gpr_addr => dbg_gpr_addr,
 460             dbg_gpr_data => dbg_gpr_data,
 461             log_data => log_data,
 462             log_read_addr => log_rd_addr,
 463             log_read_data => log_rd_data,
 464             log_write_addr => log_wr_addr,
 465             terminated_out => terminated_out
 466             );
 467
 468 end behave;