core_debug.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.utils.all;
   7 use work.common.all;
   8
   9 entity core_debug is
  10     generic (
  11         -- Length of log buffer
  12         LOG_LENGTH : natural := 512
  13         );
  14     port (
  15         clk          : in std_logic;
  16         rst          : in std_logic;
  17
  18         dmi_addr        : in std_ulogic_vector(3 downto 0);
  19         dmi_din         : in std_ulogic_vector(63 downto 0);
  20         dmi_dout        : out std_ulogic_vector(63 downto 0);
  21         dmi_req         : in std_ulogic;
  22         dmi_wr          : in std_ulogic;
  23         dmi_ack         : out std_ulogic;
  24
  25         -- Debug actions
  26         core_stop       : out std_ulogic;
  27         core_rst        : out std_ulogic;
  28         icache_rst      : out std_ulogic;
  29
  30         -- Core status inputs
  31         terminate       : in std_ulogic;
  32         core_stopped    : in std_ulogic;
  33         nia             : in std_ulogic_vector(63 downto 0);
  34         msr             : in std_ulogic_vector(63 downto 0);
  35
  36         -- GSPR register read port
  37         dbg_gpr_req     : out std_ulogic;
  38         dbg_gpr_ack     : in std_ulogic;
  39         dbg_gpr_addr    : out gspr_index_t;
  40         dbg_gpr_data    : in std_ulogic_vector(63 downto 0);
  41
  42         -- Core logging data
  43         log_data        : in std_ulogic_vector(255 downto 0);
  44         log_read_addr   : in std_ulogic_vector(31 downto 0);
  45         log_read_data   : out std_ulogic_vector(63 downto 0);
  46         log_write_addr  : out std_ulogic_vector(31 downto 0);
  47
  48         -- Misc
  49         terminated_out  : out std_ulogic
  50         );
  51 end core_debug;
  52
  53 architecture behave of core_debug is
  54         -- DMI needs fixing... make a one clock pulse
  55     signal dmi_req_1: std_ulogic;
  56
  57     -- CTRL register (direct actions, write 1 to act, read back 0)
  58     -- bit     0 : Core stop
  59     -- bit     1 : Core reset (doesn't clear stop)
  60     -- bit     2 : Icache reset
  61     -- bit     3 : Single step
  62     -- bit     4 : Core start
  63     constant DBG_CORE_CTRL         : std_ulogic_vector(3 downto 0) := "0000";
  64     constant DBG_CORE_CTRL_STOP    : integer := 0;
  65     constant DBG_CORE_CTRL_RESET   : integer := 1;
  66     constant DBG_CORE_CTRL_ICRESET : integer := 2;
  67     constant DBG_CORE_CTRL_STEP    : integer := 3;
  68     constant DBG_CORE_CTRL_START   : integer := 4;
  69
  70     -- STAT register (read only)
  71     -- bit    0 : Core stopping (wait til bit 1 set)
  72     -- bit    1 : Core stopped
  73     -- bit    2 : Core terminated (clears with start or reset)
  74     constant DBG_CORE_STAT         : std_ulogic_vector(3 downto 0) := "0001";
  75     constant DBG_CORE_STAT_STOPPING  : integer := 0;
  76     constant DBG_CORE_STAT_STOPPED   : integer := 1;
  77     constant DBG_CORE_STAT_TERM      : integer := 2;
  78
  79     -- NIA register (read only for now)
  80     constant DBG_CORE_NIA            : std_ulogic_vector(3 downto 0) := "0010";
  81
  82     -- MSR (read only)
  83     constant DBG_CORE_MSR            : std_ulogic_vector(3 downto 0) := "0011";
  84
  85     -- GSPR register index
  86     constant DBG_CORE_GSPR_INDEX     : std_ulogic_vector(3 downto 0) := "0100";
  87
  88     -- GSPR register data
  89     constant DBG_CORE_GSPR_DATA      : std_ulogic_vector(3 downto 0) := "0101";
  90
  91     -- Log buffer address and data registers
  92     constant DBG_CORE_LOG_ADDR       : std_ulogic_vector(3 downto 0) := "0110";
  93     constant DBG_CORE_LOG_DATA       : std_ulogic_vector(3 downto 0) := "0111";
  94
  95     constant LOG_INDEX_BITS : natural := log2(LOG_LENGTH);
  96
  97     -- Some internal wires
  98     signal stat_reg : std_ulogic_vector(63 downto 0);
  99
 100     -- Some internal latches
 101     signal stopping     : std_ulogic;
 102     signal do_step      : std_ulogic;
 103     signal do_reset     : std_ulogic;
 104     signal do_icreset   : std_ulogic;
 105     signal terminated   : std_ulogic;
 106     signal do_gspr_rd   : std_ulogic;
 107     signal gspr_index   : gspr_index_t;
 108
 109     signal log_dmi_addr : std_ulogic_vector(31 downto 0) := (others => '0');
 110     signal log_dmi_data : std_ulogic_vector(63 downto 0) := (others => '0');
 111     signal do_dmi_log_rd : std_ulogic;
 112     signal dmi_read_log_data : std_ulogic;
 113     signal dmi_read_log_data_1 : std_ulogic;
 114
 115 begin
 116        -- Single cycle register accesses on DMI except for GSPR data
 117     dmi_ack <= dmi_req when dmi_addr /= DBG_CORE_GSPR_DATA
 118                else dbg_gpr_ack;
 119     dbg_gpr_req <= dmi_req when dmi_addr = DBG_CORE_GSPR_DATA
 120                    else '0';
 121
 122     -- Status register read composition
 123     stat_reg <= (2 => terminated,
 124                  1 => core_stopped,
 125                  0 => stopping,
 126                  others => '0');
 127
 128     -- DMI read data mux
 129     with dmi_addr select dmi_dout <=
 130         stat_reg        when DBG_CORE_STAT,
 131         nia             when DBG_CORE_NIA,
 132         msr             when DBG_CORE_MSR,
 133         dbg_gpr_data    when DBG_CORE_GSPR_DATA,
 134         log_write_addr & log_dmi_addr when DBG_CORE_LOG_ADDR,
 135         log_dmi_data    when DBG_CORE_LOG_DATA,
 136         (others => '0') when others;
 137
 138     -- DMI writes
 139     reg_write: process(clk)
 140     begin
 141         if rising_edge(clk) then
 142             -- Reset the 1-cycle "do" signals
 143             do_step <= '0';
 144             do_reset <= '0';
 145             do_icreset <= '0';
 146             do_dmi_log_rd <= '0';
 147
 148             if (rst) then
 149                 stopping <= '0';
 150                 terminated <= '0';
 151             else
 152                 -- Edge detect on dmi_req for 1-shot pulses
 153                 dmi_req_1 <= dmi_req;
 154                 if dmi_req = '1' and dmi_req_1 = '0' then
 155                     if dmi_wr = '1' then
 156                         report("DMI write to " & to_hstring(dmi_addr));
 157
 158                         -- Control register actions
 159                         if dmi_addr = DBG_CORE_CTRL then
 160                             if dmi_din(DBG_CORE_CTRL_RESET) = '1' then
 161                                 do_reset <= '1';
 162                                 terminated <= '0';
 163                             end if;
 164                             if dmi_din(DBG_CORE_CTRL_STOP) = '1' then
 165                                 stopping <= '1';
 166                             end if;
 167                             if dmi_din(DBG_CORE_CTRL_STEP) = '1' then
 168                                 do_step <= '1';
 169                                 terminated <= '0';
 170                             end if;
 171                             if dmi_din(DBG_CORE_CTRL_ICRESET) = '1' then
 172                                 do_icreset <= '1';
 173                             end if;
 174                             if dmi_din(DBG_CORE_CTRL_START) = '1' then
 175                                 stopping <= '0';
 176                                 terminated <= '0';
 177                             end if;
 178                         elsif dmi_addr = DBG_CORE_GSPR_INDEX then
 179                             gspr_index <= dmi_din(gspr_index_t'left downto 0);
 180                         elsif dmi_addr = DBG_CORE_LOG_ADDR then
 181                             log_dmi_addr <= dmi_din(31 downto 0);
 182                             do_dmi_log_rd <= '1';
 183                         end if;
 184                     else
 185                         report("DMI read from " & to_string(dmi_addr));
 186                     end if;
 187
 188                 elsif dmi_read_log_data = '0' and dmi_read_log_data_1 = '1' then
 189                     -- Increment log_dmi_addr after the end of a read from DBG_CORE_LOG_DATA
 190                     log_dmi_addr(LOG_INDEX_BITS + 1 downto 0) <=
 191                         std_ulogic_vector(unsigned(log_dmi_addr(LOG_INDEX_BITS+1 downto 0)) + 1);
 192                     do_dmi_log_rd <= '1';
 193                 end if;
 194                 dmi_read_log_data_1 <= dmi_read_log_data;
 195                 if dmi_req = '1' and dmi_addr = DBG_CORE_LOG_DATA then
 196                     dmi_read_log_data <= '1';
 197                 else
 198                     dmi_read_log_data <= '0';
 199                 end if;
 200
 201                 -- Set core stop on terminate. We'll be stopping some time *after*
 202                 -- the offending instruction, at least until we can do back flushes
 203                 -- that preserve NIA which we can't just yet.
 204                 if terminate = '1' then
 205                     stopping <= '1';
 206                     terminated <= '1';
 207                 end if;
 208             end if;
 209         end if;
 210     end process;
 211
 212     dbg_gpr_addr <= gspr_index;
 213
 214     -- Core control signals generated by the debug module
 215     core_stop <= stopping and not do_step;
 216     core_rst <= do_reset;
 217     icache_rst <= do_icreset;
 218     terminated_out <= terminated;
 219
 220     -- Logging RAM
 221     maybe_log: if LOG_LENGTH > 0 generate
 222         subtype log_ptr_t is unsigned(LOG_INDEX_BITS - 1 downto 0);
 223         type log_array_t is array(0 to LOG_LENGTH - 1) of std_ulogic_vector(255 downto 0);
 224         signal log_array    : log_array_t;
 225         signal log_rd_ptr   : log_ptr_t;
 226         signal log_wr_ptr   : log_ptr_t;
 227         signal log_toggle   : std_ulogic;
 228         signal log_wr_enable : std_ulogic;
 229         signal log_rd_ptr_latched : log_ptr_t;
 230         signal log_rd       : std_ulogic_vector(255 downto 0);
 231         signal log_dmi_reading : std_ulogic;
 232         signal log_dmi_read_done : std_ulogic;
 233
 234         function select_dword(data : std_ulogic_vector(255 downto 0);
 235                               addr : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
 236             variable firstbit : integer;
 237         begin
 238             firstbit := to_integer(unsigned(addr(1 downto 0))) * 64;
 239             return data(firstbit + 63 downto firstbit);
 240         end;
 241
 242         attribute ram_style : string;
 243         attribute ram_style of log_array : signal is "block";
 244         attribute ram_decomp : string;
 245         attribute ram_decomp of log_array : signal is "power";
 246
 247     begin
 248         -- Use MSB of read addresses to stop the logging
 249         log_wr_enable <= not (log_read_addr(31) or log_dmi_addr(31));
 250
 251         log_ram: process(clk)
 252         begin
 253             if rising_edge(clk) then
 254                 if log_wr_enable = '1' then
 255                     log_array(to_integer(log_wr_ptr)) <= log_data;
 256                 end if;
 257                 log_rd <= log_array(to_integer(log_rd_ptr_latched));
 258             end if;
 259         end process;
 260
 261
 262         log_buffer: process(clk)
 263             variable b : integer;
 264             variable data : std_ulogic_vector(255 downto 0);
 265         begin
 266             if rising_edge(clk) then
 267                 if rst = '1' then
 268                     log_wr_ptr <= (others => '0');
 269                     log_toggle <= '0';
 270                 elsif log_wr_enable = '1' then
 271                     if log_wr_ptr = to_unsigned(LOG_LENGTH - 1, LOG_INDEX_BITS) then
 272                         log_toggle <= not log_toggle;
 273                     end if;
 274                     log_wr_ptr <= log_wr_ptr + 1;
 275                 end if;
 276                 if do_dmi_log_rd = '1' then
 277                     log_rd_ptr_latched <= unsigned(log_dmi_addr(LOG_INDEX_BITS + 1 downto 2));
 278                 else
 279                     log_rd_ptr_latched <= unsigned(log_read_addr(LOG_INDEX_BITS + 1 downto 2));
 280                 end if;
 281                 if log_dmi_read_done = '1' then
 282                     log_dmi_data <= select_dword(log_rd, log_dmi_addr);
 283                 else
 284                     log_read_data <= select_dword(log_rd, log_read_addr);
 285                 end if;
 286                 log_dmi_read_done <= log_dmi_reading;
 287                 log_dmi_reading <= do_dmi_log_rd;
 288             end if;
 289         end process;
 290         log_write_addr(LOG_INDEX_BITS - 1 downto 0) <= std_ulogic_vector(log_wr_ptr);
 291         log_write_addr(LOG_INDEX_BITS) <= '1';
 292         log_write_addr(31 downto LOG_INDEX_BITS + 1) <= (others => '0');
 293     end generate;
 294
 295     no_log: if LOG_LENGTH = 0 generate
 296     begin
 297         log_read_data <= (others => '0');
 298         log_write_addr <= x"00000001";
 299     end generate;
 300
 301 end behave;
 302