core_dram_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8 use work.utils.all;
   9
  10 entity core_dram_tb is
  11     generic (
  12         MEMORY_SIZE    : natural := (384*1024);
  13         MAIN_RAM_FILE  : string  := "main_ram.bin";
  14         DRAM_INIT_FILE : string  := "";
  15         DRAM_INIT_SIZE : natural := 16#c000#;
  16         L2_TRACE : boolean := false;
  17         LITEDRAM_TRACE : boolean := false
  18         );
  19 end core_dram_tb;
  20
  21 architecture behave of core_dram_tb is
  22     signal clk, rst: std_logic;
  23     signal system_clk, soc_rst : std_ulogic;
  24
  25     -- testbench signals
  26     constant clk_period : time := 10 ns;
  27
  28     -- Sim DRAM
  29     signal wb_dram_in : wishbone_master_out;
  30     signal wb_dram_out : wishbone_slave_out;
  31     signal wb_ext_io_in : wb_io_master_out;
  32     signal wb_ext_io_out : wb_io_slave_out;
  33     signal wb_ext_is_dram_csr : std_ulogic;
  34     signal wb_ext_is_dram_init : std_ulogic;
  35
  36     -- SPI
  37     signal spi_sck     : std_ulogic;
  38     signal spi_cs_n    : std_ulogic := '1';
  39     signal spi_sdat_o  : std_ulogic_vector(3 downto 0);
  40     signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
  41     signal spi_sdat_i  : std_ulogic_vector(3 downto 0);
  42     signal fl_hold_n   : std_logic;
  43     signal fl_wp_n     : std_logic;
  44     signal fl_mosi     : std_logic;
  45     signal fl_miso     : std_logic;
  46
  47     -- ROM size
  48     function get_rom_size return natural is
  49     begin
  50         if MEMORY_SIZE = 0 then
  51             return DRAM_INIT_SIZE;
  52         else
  53             return 0;
  54         end if;
  55     end function;
  56
  57     constant ROM_SIZE : natural := get_rom_size;
  58 begin
  59
  60     soc0: entity work.soc
  61         generic map(
  62             SIM => true,
  63             MEMORY_SIZE => MEMORY_SIZE,
  64             RAM_INIT_FILE => MAIN_RAM_FILE,
  65             HAS_DRAM => true,
  66             DRAM_SIZE => 256 * 1024 * 1024,
  67             DRAM_INIT_SIZE => ROM_SIZE,
  68             CLK_FREQ => 100000000,
  69             HAS_SPI_FLASH    => true,
  70             SPI_FLASH_DLINES => 4,
  71             SPI_FLASH_OFFSET => 0
  72             )
  73         port map(
  74             rst => soc_rst,
  75             system_clk => system_clk,
  76             wb_dram_in => wb_dram_in,
  77             wb_dram_out => wb_dram_out,
  78             wb_ext_io_in => wb_ext_io_in,
  79             wb_ext_io_out => wb_ext_io_out,
  80             wb_ext_is_dram_csr => wb_ext_is_dram_csr,
  81             wb_ext_is_dram_init => wb_ext_is_dram_init,
  82             spi_flash_sck     => spi_sck,
  83             spi_flash_cs_n    => spi_cs_n,
  84             spi_flash_sdat_o  => spi_sdat_o,
  85             spi_flash_sdat_oe => spi_sdat_oe,
  86             spi_flash_sdat_i  => spi_sdat_i
  87             );
  88
  89         flash: entity work.s25fl128s
  90         generic map (
  91             TimingModel => "S25FL128SAGNFI000_R_30pF",
  92             LongTimming => false,
  93             tdevice_PU => 10 ns,
  94             tdevice_PP256 => 100 ns,
  95             tdevice_PP512 => 100 ns,
  96             tdevice_WRR   => 100 ns,
  97             UserPreload => TRUE
  98             )
  99         port map(
 100             SCK => spi_sck,
 101             SI => fl_mosi,
 102             CSNeg => spi_cs_n,
 103             HOLDNeg => fl_hold_n,
 104             WPNeg => fl_wp_n,
 105             RSTNeg => '1',
 106             SO => fl_miso
 107             );
 108
 109     fl_mosi   <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
 110     fl_miso   <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
 111     fl_wp_n   <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
 112     fl_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else '1' when spi_sdat_oe(0) = '1' else 'Z';
 113
 114     spi_sdat_i(0) <= fl_mosi;
 115     spi_sdat_i(1) <= fl_miso;
 116     spi_sdat_i(2) <= fl_wp_n;
 117     spi_sdat_i(3) <= fl_hold_n;
 118
 119     dram: entity work.litedram_wrapper
 120         generic map(
 121             DRAM_ABITS => 24,
 122             DRAM_ALINES => 1,
 123             DRAM_DLINES => 16,
 124             DRAM_CKLINES => 1,
 125             DRAM_PORT_WIDTH => 128,
 126             PAYLOAD_FILE => DRAM_INIT_FILE,
 127             PAYLOAD_SIZE => ROM_SIZE,
 128             TRACE => L2_TRACE,
 129             LITEDRAM_TRACE => LITEDRAM_TRACE
 130             )
 131         port map(
 132             clk_in          => clk,
 133             rst             => rst,
 134             system_clk      => system_clk,
 135             system_reset    => soc_rst,
 136
 137             wb_in           => wb_dram_in,
 138             wb_out          => wb_dram_out,
 139             wb_ctrl_in      => wb_ext_io_in,
 140             wb_ctrl_out     => wb_ext_io_out,
 141             wb_ctrl_is_csr  => wb_ext_is_dram_csr,
 142             wb_ctrl_is_init => wb_ext_is_dram_init
 143             );
 144
 145     clk_process: process
 146     begin
 147         clk <= '0';
 148         wait for clk_period/2;
 149         clk <= '1';
 150         wait for clk_period/2;
 151     end process;
 152
 153     rst_process: process
 154     begin
 155         rst <= '1';
 156         wait for 10*clk_period;
 157         rst <= '0';
 158         wait;
 159     end process;
 160
 161     jtag: entity work.sim_jtag;
 162
 163 end;