2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 PIPELINE_DEPTH : natural := 1
11 busy_in : in std_ulogic;
12 deferred : in std_ulogic;
13 complete_in : in std_ulogic;
14 flush_in : in std_ulogic;
15 issuing : in std_ulogic;
17 cr_read_in : in std_ulogic;
18 cr_write_in : in std_ulogic;
19 bypassable : in std_ulogic;
21 stall_out : out std_ulogic;
22 use_bypass : out std_ulogic
25 architecture behaviour of cr_hazard is
26 type pipeline_entry_type is record
30 constant pipeline_entry_init : pipeline_entry_type := (valid => '0', bypass => '0');
32 type pipeline_t is array(0 to PIPELINE_DEPTH) of pipeline_entry_type;
33 constant pipeline_t_init : pipeline_t := (others => pipeline_entry_init);
35 signal r, rin : pipeline_t := pipeline_t_init;
37 cr_hazard0: process(clk)
39 if rising_edge(clk) then
44 cr_hazard1: process(all)
45 variable v : pipeline_t;
49 -- XXX assumes PIPELINE_DEPTH = 1
50 if complete_in = '1' then
56 if cr_read_in = '1' then
57 loop_0: for i in 0 to PIPELINE_DEPTH loop
58 if v(i).valid = '1' then
59 if r(i).bypass = '1' then
68 -- XXX assumes PIPELINE_DEPTH = 1
73 if deferred = '0' and issuing = '1' then
74 v(0).valid := cr_write_in;
75 v(0).bypass := bypassable;
77 if flush_in = '1' then