cr_hazard.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 entity cr_hazard is
   6     generic (
   7         PIPELINE_DEPTH : natural := 1
   8         );
   9     port(
  10         clk         : in std_ulogic;
  11         busy_in     : in std_ulogic;
  12         deferred    : in std_ulogic;
  13         complete_in : in std_ulogic;
  14         flush_in    : in std_ulogic;
  15         issuing     : in std_ulogic;
  16
  17         cr_read_in  : in std_ulogic;
  18         cr_write_in : in std_ulogic;
  19         bypassable  : in std_ulogic;
  20
  21         stall_out   : out std_ulogic;
  22         use_bypass  : out std_ulogic
  23         );
  24 end entity cr_hazard;
  25 architecture behaviour of cr_hazard is
  26     type pipeline_entry_type is record
  27         valid  : std_ulogic;
  28         bypass : std_ulogic;
  29     end record;
  30     constant pipeline_entry_init : pipeline_entry_type := (valid => '0', bypass => '0');
  31
  32     type pipeline_t is array(0 to PIPELINE_DEPTH) of pipeline_entry_type;
  33     constant pipeline_t_init : pipeline_t := (others => pipeline_entry_init);
  34
  35     signal r, rin : pipeline_t := pipeline_t_init;
  36 begin
  37     cr_hazard0: process(clk)
  38     begin
  39         if rising_edge(clk) then
  40             r <= rin;
  41         end if;
  42     end process;
  43
  44     cr_hazard1: process(all)
  45         variable v     : pipeline_t;
  46     begin
  47         v := r;
  48
  49         -- XXX assumes PIPELINE_DEPTH = 1
  50         if complete_in = '1' then
  51             v(1).valid := '0';
  52         end if;
  53
  54         use_bypass <= '0';
  55         stall_out <= '0';
  56         if cr_read_in = '1' then
  57             loop_0: for i in 0 to PIPELINE_DEPTH loop
  58                 if v(i).valid = '1' then
  59                     if r(i).bypass = '1' then
  60                         use_bypass <= '1';
  61                     else
  62                         stall_out <= '1';
  63                     end if;
  64                 end if;
  65             end loop;
  66         end if;
  67
  68         -- XXX assumes PIPELINE_DEPTH = 1
  69         if busy_in = '0' then
  70             v(1) := r(0);
  71             v(0).valid := '0';
  72         end if;
  73         if deferred = '0' and issuing = '1' then
  74             v(0).valid := cr_write_in;
  75             v(0).bypass := bypassable;
  76         end if;
  77         if flush_in = '1' then
  78             v(0).valid := '0';
  79             v(1).valid := '0';
  80         end if;
  81
  82         -- update registers
  83         rin <= v;
  84
  85     end process;
  86 end;