crypto_router_asic.mdwn

   1 # Crypto-router ASIC
   2
   3 * NLnet page: [[nlnet_2021_crypto_router]]
   4 * Top-level bugreport: <https://bugs.libre-soc.org/show_bug.cgi?id=589>
   5
   6 # Specifications
   7
   8 All of these are entirely Libre-Licensed or are to be written as Libre-Licensed:
   9
  10 * 300 mhz single-core,
  11   [Libre-SOC](https://git.libre-soc.org/?p=soc.git;a=blob;f=README.md;hb=HEAD)
  12   OpenPOWER CPU with
  13   [[openpower/sv/bitmanip]] extensions
  14 * 180/130 nm (TBD)
  15 * 5x [[shakti/m_class/RGMII]] Gigabit Ethernet PHYs
  16 * 2x USB [[shakti/m_class/ULPI]] PHYs
  17 * Direct DMA interface (independent bulk transfer)
  18 * [JTAG](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;hb=HEAD),
  19   GPIO, I2C, PWM, UART, SPI, QSPI, SD/MMC
  20 * On-board Dual-ported SRAM (for Packet Buffers)
  21 * Opencores [[shakti/m_class/sdram]]
  22 * Wishbone interfaces to all peripherals
  23 * [XICS ICP / ICS](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/interrupts/xics.py;hb=HEAD)
  24   Interrupt Controller
  25
  26
  27
  28 # Example packet transfer
  29
  30 * Packet comes in on RGMII port 1.  Each PHY has its own dual-ported SRAM
  31 * Packet is **directly** stored in internal (dual-ported SRAM) by
  32   the RGMII PHY itself
  33 * Interrupt notification is sent to the processor (XICS)
  34 * Processor inspects packet over Wishbone interface directly
  35   connected to 2nd SRAM port.
  36 * Processor computes, based on decoding the ETH Frame, where the
  37   packet must be sent to (which other RGM-II port: e.g. Port 2)
  38 * Processor initiates Memory-to-Memory DMA transfer
  39 * DMA Memory-to-Memory transfer, using Wishbone Bus, copies the ETH Frame
  40   from one on-board SRAM to the target on-board SRAM associated with Port 2.
  41 * DMA Engine generates interrupt (XICS) to the CPU to say it is completed
  42 * Processor notifies target RGM-II PHY to activate "send" of frame out
  43   through target RGM-II port 2.
  44
  45 # Testing and Verification
  46
  47 We will need full HDL simulations as well as post P&R simulations.
  48 These may be achieved as follows:
  49
  50 * ISA-level unit tests as well as Formal Correctness Proofs.
  51   Example [bpermd proof](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/formal/proof_bpermd.py;hb=HEAD)
  52   and individual unit tests for the
  53   [Logical pipeline](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/test/test_pipe_caller.py;hb=HEAD)
  54 * [Litex sim.py](https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=sim.py;hb=HEAD)
  55   with some peripherals developed in c++ as verilator modules
  56 * nmigen-based OpenPOWER Libre-SOC core co-simulation such as
  57   this unit test,
  58   [test_issuer.py](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/test/test_issuer.py;hb=HEAD)
  59 * [cocotb pre/post PnR](https://git.libre-soc.org/?p=soc-cocotb-sim.git;a=tree;f=ls180;hb=HEAD) including GHDL, Icarus and Verilator
  60   (where best suited)
  61
  62 Actual instructions being developed (bitmanip) may therefore be
  63 unit tested prior to deployment.  Following that, rapid simulations
  64 may be achieved by running Litex (the same HDL may also easily
  65 be uploaded to an FPGA).  When it comes to Place-and-Route of the
  66 ASIC, the cocotb simulations may be used to verify that the GDS-II
  67 layout has not been "damaged" by the PnR tools.
  68
  69 Peripherals functionality tests must also be part of the simulations,
  70 particularly using cocotb, to ensure that they remain functional after PnR.
  71 Supercomputer access for compilation of verilator and/or cxxrtl is available
  72 through [[fed4fire]]
  73