dcache_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 library work;
   5 use work.common.all;
   6 use work.wishbone_types.all;
   7
   8 entity dcache_tb is
   9 end dcache_tb;
  10
  11 architecture behave of dcache_tb is
  12     signal clk          : std_ulogic;
  13     signal rst          : std_ulogic;
  14
  15     signal d_in         : Loadstore1ToDcacheType;
  16     signal d_out        : DcacheToLoadstore1Type;
  17
  18     signal m_in         : MmuToDcacheType;
  19     signal m_out        : DcacheToMmuType;
  20
  21     signal wb_bram_in   : wishbone_master_out;
  22     signal wb_bram_out  : wishbone_slave_out;
  23
  24     constant clk_period : time := 10 ns;
  25
  26     signal stall : std_ulogic;
  27 begin
  28     dcache0: entity work.dcache
  29         generic map(
  30             LINE_SIZE => 64,
  31             NUM_LINES => 4
  32             )
  33         port map(
  34             clk => clk,
  35             rst => rst,
  36             d_in => d_in,
  37             d_out => d_out,
  38             stall_out => stall,
  39             m_in => m_in,
  40             m_out => m_out,
  41             wishbone_out => wb_bram_in,
  42             wishbone_in => wb_bram_out
  43             );
  44
  45     -- BRAM Memory slave
  46     bram0: entity work.wishbone_bram_wrapper
  47         generic map(
  48             MEMORY_SIZE   => 1024,
  49             RAM_INIT_FILE => "icache_test.bin"
  50             )
  51         port map(
  52             clk => clk,
  53             rst => rst,
  54             wishbone_in => wb_bram_in,
  55             wishbone_out => wb_bram_out
  56             );
  57
  58     clk_process: process
  59     begin
  60         clk <= '0';
  61         wait for clk_period/2;
  62         clk <= '1';
  63         wait for clk_period/2;
  64     end process;
  65
  66     rst_process: process
  67     begin
  68         rst <= '1';
  69         wait for 2*clk_period;
  70         rst <= '0';
  71         wait;
  72     end process;
  73
  74     stim: process
  75     begin
  76         -- Clear stuff
  77         d_in.valid <= '0';
  78         d_in.load <= '0';
  79         d_in.nc <= '0';
  80         d_in.hold <= '0';
  81         d_in.dcbz <= '0';
  82         d_in.reserve <= '0';
  83         d_in.virt_mode <= '0';
  84         d_in.priv_mode <= '1';
  85         d_in.addr <= (others => '0');
  86         d_in.data <= (others => '0');
  87         d_in.byte_sel <= (others => '1');
  88         m_in.valid <= '0';
  89         m_in.addr <= (others => '0');
  90         m_in.pte <= (others => '0');
  91         m_in.tlbie <= '0';
  92         m_in.doall <= '0';
  93         m_in.tlbld <= '0';
  94
  95         wait for 4*clk_period;
  96         wait until rising_edge(clk);
  97
  98         -- Cacheable read of address 4
  99         report "cache read address 4...";
 100         d_in.load <= '1';
 101         d_in.nc <= '0';
 102         d_in.addr <= x"0000000000000004";
 103         d_in.valid <= '1';
 104         wait until rising_edge(clk) and stall = '0';
 105         d_in.valid <= '0';
 106
 107         wait until rising_edge(clk) and d_out.valid = '1';
 108         assert d_out.data = x"0000000100000000"
 109             report "data @" & to_hstring(d_in.addr) &
 110             "=" & to_hstring(d_out.data) &
 111             " expected 0000000100000000"
 112             severity failure;
 113
 114         -- Cacheable read of address 30 (hit after hit forward from reload)
 115         report "cache read address 30...";
 116         d_in.load <= '1';
 117         d_in.nc <= '0';
 118         d_in.addr <= x"0000000000000030";
 119         d_in.valid <= '1';
 120         wait until rising_edge(clk) and stall = '0';
 121         d_in.valid <= '0';
 122
 123         wait until rising_edge(clk) and d_out.valid = '1';
 124         assert d_out.data = x"0000000D0000000C"
 125             report "data @" & to_hstring(d_in.addr) &
 126             "=" & to_hstring(d_out.data) &
 127             " expected 0000000D0000000C"
 128             severity failure;
 129
 130         -- Ensure reload completes
 131         wait for 100*clk_period;
 132         wait until rising_edge(clk);
 133
 134         -- Cacheable read of address 38 (hit on idle cache)
 135         report "cache read address 38...";
 136         d_in.load <= '1';
 137         d_in.nc <= '0';
 138         d_in.addr <= x"0000000000000038";
 139         d_in.valid <= '1';
 140         wait until rising_edge(clk) and stall = '0';
 141         d_in.valid <= '0';
 142
 143         wait until rising_edge(clk) and d_out.valid = '1';
 144         assert d_out.data = x"0000000F0000000E"
 145             report "data @" & to_hstring(d_in.addr) &
 146             "=" & to_hstring(d_out.data) &
 147             " expected 0000000F0000000E"
 148             severity failure;
 149
 150         -- Cacheable read of address 130 (miss after hit, same index)
 151         -- This will use way 2
 152         report "cache read address 130...";
 153         d_in.load <= '1';
 154         d_in.nc <= '0';
 155         d_in.addr <= x"0000000000000130";
 156         d_in.valid <= '1';
 157         wait until rising_edge(clk) and stall = '0';
 158         d_in.valid <= '0';
 159
 160         wait until rising_edge(clk) and d_out.valid = '1';
 161         assert d_out.data = x"0000004d0000004c"
 162             report "data @" & to_hstring(d_in.addr) &
 163             "=" & to_hstring(d_out.data) &
 164             " expected 0000004d0000004c"
 165             severity failure;
 166
 167         -- Ensure reload completes
 168         wait for 100*clk_period;
 169         wait until rising_edge(clk);
 170
 171         -- Cacheable read again of address 130 (hit in idle cache)
 172         -- This should feed from way 2
 173         report "cache read address 130...";
 174         d_in.load <= '1';
 175         d_in.nc <= '0';
 176         d_in.addr <= x"0000000000000130";
 177         d_in.valid <= '1';
 178         wait until rising_edge(clk) and stall = '0';
 179         d_in.valid <= '0';
 180
 181         wait until rising_edge(clk) and d_out.valid = '1';
 182         assert d_out.data = x"0000004d0000004c"
 183             report "data @" & to_hstring(d_in.addr) &
 184             "=" & to_hstring(d_out.data) &
 185             " expected 0000004d0000004c"
 186             severity failure;
 187
 188         -- Cacheable read of address 40
 189         report "cache read address 40...";
 190         d_in.load <= '1';
 191         d_in.nc <= '0';
 192         d_in.addr <= x"0000000000000040";
 193         d_in.valid <= '1';
 194         wait until rising_edge(clk);
 195         d_in.valid <= '0';
 196
 197         wait until rising_edge(clk) and d_out.valid = '1';
 198         assert d_out.data = x"0000001100000010"
 199             report "data @" & to_hstring(d_in.addr) &
 200             "=" & to_hstring(d_out.data) &
 201             " expected 0000001100000010"
 202             severity failure;
 203
 204         -- Cacheable read of address 140 (miss after miss, same index)
 205         -- This should use way 2
 206         report "cache read address 140...";
 207         d_in.load <= '1';
 208         d_in.nc <= '0';
 209         d_in.addr <= x"0000000000000140";
 210         d_in.valid <= '1';
 211         wait until rising_edge(clk) and stall = '0';
 212         d_in.valid <= '0';
 213
 214         wait until rising_edge(clk) and d_out.valid = '1';
 215         assert d_out.data = x"0000005100000050"
 216             report "data @" & to_hstring(d_in.addr) &
 217             "=" & to_hstring(d_out.data) &
 218             " expected 0000005100000050"
 219             severity failure;
 220
 221         -- Non-cacheable read of address 200
 222         report "non-cache read address 200...";
 223         d_in.load <= '1';
 224         d_in.nc <= '1';
 225         d_in.addr <= x"0000000000000200";
 226         d_in.valid <= '1';
 227         wait until rising_edge(clk) and stall = '0';
 228         d_in.valid <= '0';
 229         wait until rising_edge(clk) and d_out.valid = '1';
 230         assert d_out.data = x"0000008100000080"
 231             report "data @" & to_hstring(d_in.addr) &
 232             "=" & to_hstring(d_out.data) &
 233             " expected 0000008100000080"
 234             severity failure;
 235
 236         wait until rising_edge(clk);
 237         wait until rising_edge(clk);
 238         wait until rising_edge(clk);
 239         wait until rising_edge(clk);
 240
 241         std.env.finish;
 242     end process;
 243 end;