debian/control

   1 Source:        tasyag
   2 Section:       Science/Electronics
   3 Priority:      optional
   4 Maintainer:    Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
   5 Build-Depends: debhelper (>= 7),
   6                quilt,
   7                tcsh,
   8                texlive-full,
   9                swig,
  10                libedit-dev,
  11                tcl8.5-dev,
  12                libmotif-dev,
  13                libxp-dev,
  14                libxt-dev,
  15                libxpm-dev,
  16                openjdk-6-jre,
  17                libsaxon-java (>= 9),
  18                libsaxonb-java,
  19                libservlet2.4-java,
  20                fop (>= 0.95)
  21 Homepage:      https://soc-extras.lip6.fr/en/tasyag-abstract-en/
  22 Standards-Version: 3.8.4
  23
  24 Package:      tasyag
  25 Architecture: any
  26 Depends:      ${misc:Depends},
  27               ${shlibs:Depends},
  28               tcl8.5
  29 Description: Tas/Yagle - Static Timing Analyser
  30  The  advent   of  semiconductor  fabrication technologies   now   allows   high
  31  performance in complex integrated circuits.
  32    With the increasing complexity of  these  circuits,  static  timing  analysis
  33  (STA)  has  revealed  itself  as  the  only feasible   method   ensuring   that
  34  expected performances are actually obtained.
  35    In addition, signal integrity (SI) issues due to  crosstalk  play  a  crucial
  36  role in performance and reliability of these systems, and must  be  taken  into
  37  account during the timing analysis.
  38    However, performance  achievement not  only lies in fabrication technologies,
  39  but also  in the way circuits  are designed.  Very high performance designs are
  40  obtained with semi or full-custom designs techniques.
  41    The HITAS platform provides advanced  STA  and  SI  solutions  at  transistor
  42  level. It has been  built-up in order to allow  engineers  to  ensure  complete
  43  timing and SI coverage on their digital custom designs,  as  well  as  IP-reuse
  44  through timing abstraction.
  45    Furthermore,  hierarchy  handling  through  transparent  timing  views allows
  46  full-chip verification, with virtually no limit of capacity in design size.