13 from testlib
import assertEqual
, assertNotEqual
, assertIn
, assertNotIn
14 from testlib
import assertGreater
, assertRegexpMatches
, assertLess
15 from testlib
import GdbTest
, GdbSingleHartTest
, TestFailed
, assertTrue
17 MSTATUS_UIE
= 0x00000001
18 MSTATUS_SIE
= 0x00000002
19 MSTATUS_HIE
= 0x00000004
20 MSTATUS_MIE
= 0x00000008
21 MSTATUS_UPIE
= 0x00000010
22 MSTATUS_SPIE
= 0x00000020
23 MSTATUS_HPIE
= 0x00000040
24 MSTATUS_MPIE
= 0x00000080
25 MSTATUS_SPP
= 0x00000100
26 MSTATUS_HPP
= 0x00000600
27 MSTATUS_MPP
= 0x00001800
28 MSTATUS_FS
= 0x00006000
29 MSTATUS_XS
= 0x00018000
30 MSTATUS_MPRV
= 0x00020000
31 MSTATUS_PUM
= 0x00040000
32 MSTATUS_MXR
= 0x00080000
33 MSTATUS_VM
= 0x1F000000
34 MSTATUS32_SD
= 0x80000000
35 MSTATUS64_SD
= 0x8000000000000000
37 # pylint: disable=abstract-method
39 def ihex_line(address
, record_type
, data
):
40 assert len(data
) < 128
41 line
= ":%02X%04X%02X" % (len(data
), address
, record_type
)
43 check
+= address
% 256
49 line
+= "%02X" % value
50 line
+= "%02X\n" % ((256-check
)%256)
54 assert line
.startswith(":")
56 data_len
= int(line
[:2], 16)
57 address
= int(line
[2:6], 16)
58 record_type
= int(line
[6:8], 16)
60 for i
in range(data_len
):
61 data
+= "%c" % int(line
[8+2*i
:10+2*i
], 16)
62 return record_type
, address
, data
64 def readable_binary_string(s
):
65 return "".join("%02x" % ord(c
) for c
in s
)
67 class SimpleRegisterTest(GdbTest
):
68 def check_reg(self
, name
, alias
):
69 a
= random
.randrange(1<<self
.hart
.xlen
)
70 b
= random
.randrange(1<<self
.hart
.xlen
)
71 self
.gdb
.p("$%s=0x%x" % (name
, a
))
72 assertEqual(self
.gdb
.p("$%s" % alias
), a
)
74 assertEqual(self
.gdb
.p("$%s" % name
), a
)
75 assertEqual(self
.gdb
.p("$%s" % alias
), a
)
76 self
.gdb
.p("$%s=0x%x" % (alias
, b
))
77 assertEqual(self
.gdb
.p("$%s" % name
), b
)
79 assertEqual(self
.gdb
.p("$%s" % name
), b
)
80 assertEqual(self
.gdb
.p("$%s" % alias
), b
)
84 self
.gdb
.command("p *((int*) 0x%x)=0x13" % self
.hart
.ram
)
85 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 4))
86 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 8))
87 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 12))
88 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 16))
89 self
.gdb
.p("$pc=0x%x" % self
.hart
.ram
)
91 class SimpleS0Test(SimpleRegisterTest
):
93 self
.check_reg("s0", "x8")
95 class SimpleS1Test(SimpleRegisterTest
):
97 self
.check_reg("s1", "x9")
99 class SimpleT0Test(SimpleRegisterTest
):
101 self
.check_reg("t0", "x5")
103 class SimpleT1Test(SimpleRegisterTest
):
105 self
.check_reg("t1", "x6")
107 class SimpleF18Test(SimpleRegisterTest
):
108 def check_reg(self
, name
, alias
):
109 if self
.hart
.extensionSupported('F'):
110 self
.gdb
.p_raw("$mstatus=$mstatus | 0x00006000")
114 self
.gdb
.p_raw("$%s=%f" % (name
, a
))
115 assertLess(abs(float(self
.gdb
.p_raw("$%s" % alias
)) - a
), .001)
117 assertLess(abs(float(self
.gdb
.p_raw("$%s" % name
)) - a
), .001)
118 assertLess(abs(float(self
.gdb
.p_raw("$%s" % alias
)) - a
), .001)
119 self
.gdb
.p_raw("$%s=%f" % (alias
, b
))
120 assertLess(abs(float(self
.gdb
.p_raw("$%s" % name
)) - b
), .001)
122 assertLess(abs(float(self
.gdb
.p_raw("$%s" % name
)) - b
), .001)
123 assertLess(abs(float(self
.gdb
.p_raw("$%s" % alias
)) - b
), .001)
125 size
= self
.gdb
.p("sizeof($%s)" % name
)
126 if self
.hart
.extensionSupported('D'):
131 output
= self
.gdb
.p_raw("$" + name
)
132 assertEqual(output
, "void")
133 output
= self
.gdb
.p_raw("$" + alias
)
134 assertEqual(output
, "void")
137 self
.check_reg("f18", "fs2")
139 class SimpleMemoryTest(GdbTest
):
140 def access_test(self
, size
, data_type
):
141 assertEqual(self
.gdb
.p("sizeof(%s)" % data_type
), size
)
142 a
= 0x86753095555aaaa & ((1<<(size
*8))-1)
143 b
= 0xdeadbeef12345678 & ((1<<(size
*8))-1)
144 addrA
= self
.hart
.ram
145 addrB
= self
.hart
.ram
+ self
.hart
.ram_size
- size
146 self
.gdb
.p("*((%s*)0x%x) = 0x%x" % (data_type
, addrA
, a
))
147 self
.gdb
.p("*((%s*)0x%x) = 0x%x" % (data_type
, addrB
, b
))
148 assertEqual(self
.gdb
.p("*((%s*)0x%x)" % (data_type
, addrA
)), a
)
149 assertEqual(self
.gdb
.p("*((%s*)0x%x)" % (data_type
, addrB
)), b
)
151 class MemTest8(SimpleMemoryTest
):
153 self
.access_test(1, 'char')
155 class MemTest16(SimpleMemoryTest
):
157 self
.access_test(2, 'short')
159 class MemTest32(SimpleMemoryTest
):
161 self
.access_test(4, 'int')
163 class MemTest64(SimpleMemoryTest
):
165 self
.access_test(8, 'long long')
167 # FIXME: I'm not passing back invalid addresses correctly in read/write memory.
168 #class MemTestReadInvalid(SimpleMemoryTest):
170 # # This test relies on 'gdb_report_data_abort enable' being executed in
171 # # the openocd.cfg file.
173 # self.gdb.p("*((int*)0xdeadbeef)")
174 # assert False, "Read should have failed."
175 # except testlib.CannotAccess as e:
176 # assertEqual(e.address, 0xdeadbeef)
177 # self.gdb.p("*((int*)0x%x)" % self.hart.ram)
179 #class MemTestWriteInvalid(SimpleMemoryTest):
181 # # This test relies on 'gdb_report_data_abort enable' being executed in
182 # # the openocd.cfg file.
184 # self.gdb.p("*((int*)0xdeadbeef)=8675309")
185 # assert False, "Write should have failed."
186 # except testlib.CannotAccess as e:
187 # assertEqual(e.address, 0xdeadbeef)
188 # self.gdb.p("*((int*)0x%x)=6874742" % self.hart.ram)
190 class MemTestBlock(GdbTest
):
195 a
= tempfile
.NamedTemporaryFile(suffix
=".ihex")
197 for i
in range(self
.length
/ self
.line_length
):
198 line_data
= "".join(["%c" % random
.randrange(256)
199 for _
in range(self
.line_length
)])
201 a
.write(ihex_line(i
* self
.line_length
, 0, line_data
))
204 self
.gdb
.command("shell cat %s" % a
.name
)
205 self
.gdb
.command("restore %s 0x%x" % (a
.name
, self
.hart
.ram
))
207 for offset
in range(0, self
.length
, increment
) + [self
.length
-4]:
208 value
= self
.gdb
.p("*((int*)0x%x)" % (self
.hart
.ram
+ offset
))
209 written
= ord(data
[offset
]) | \
210 (ord(data
[offset
+1]) << 8) | \
211 (ord(data
[offset
+2]) << 16) | \
212 (ord(data
[offset
+3]) << 24)
213 assertEqual(value
, written
)
215 b
= tempfile
.NamedTemporaryFile(suffix
=".ihex")
216 self
.gdb
.command("dump ihex memory %s 0x%x 0x%x" % (b
.name
,
217 self
.hart
.ram
, self
.hart
.ram
+ self
.length
))
218 self
.gdb
.command("shell cat %s" % b
.name
)
219 for line
in b
.xreadlines():
220 record_type
, address
, line_data
= ihex_parse(line
)
222 written_data
= data
[address
:address
+len(line_data
)]
223 if line_data
!= written_data
:
225 "Data mismatch at 0x%x; wrote %s but read %s" % (
226 address
, readable_binary_string(written_data
),
227 readable_binary_string(line_data
)))
229 class InstantHaltTest(GdbTest
):
231 """Assert that reset is really resetting what it should."""
232 self
.gdb
.command("monitor reset halt")
233 self
.gdb
.command("flushregs")
234 threads
= self
.gdb
.threads()
238 pcs
.append(self
.gdb
.p("$pc"))
240 assertIn(pc
, self
.hart
.reset_vectors
)
241 # mcycle and minstret have no defined reset value.
242 mstatus
= self
.gdb
.p("$mstatus")
243 assertEqual(mstatus
& (MSTATUS_MIE | MSTATUS_MPRV |
246 class InstantChangePc(GdbTest
):
248 """Change the PC right as we come out of reset."""
250 self
.gdb
.command("monitor reset halt")
251 self
.gdb
.command("flushregs")
252 self
.gdb
.command("p *((int*) 0x%x)=0x13" % self
.hart
.ram
)
253 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 4))
254 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 8))
255 self
.gdb
.p("$pc=0x%x" % self
.hart
.ram
)
257 assertEqual((self
.hart
.ram
+ 4), self
.gdb
.p("$pc"))
259 assertEqual((self
.hart
.ram
+ 8), self
.gdb
.p("$pc"))
261 class DebugTest(GdbSingleHartTest
):
262 # Include malloc so that gdb can make function calls. I suspect this malloc
263 # will silently blow through the memory set aside for it, so be careful.
264 compile_args
= ("programs/debug.c", "programs/checksum.c",
265 "programs/tiny-malloc.c", "-DDEFINE_MALLOC", "-DDEFINE_FREE")
271 def exit(self
, expected_result
=0xc86455d4):
272 output
= self
.gdb
.c()
273 assertIn("Breakpoint", output
)
274 assertIn("_exit", output
)
275 assertEqual(self
.gdb
.p("status"), expected_result
)
277 class DebugCompareSections(DebugTest
):
279 output
= self
.gdb
.command("compare-sections")
281 for line
in output
.splitlines():
282 if line
.startswith("Section"):
283 assert line
.endswith("matched.")
285 assertGreater(matched
, 1)
287 class DebugFunctionCall(DebugTest
):
289 self
.gdb
.b("main:start")
291 assertEqual(self
.gdb
.p('fib(6)'), 8)
292 assertEqual(self
.gdb
.p('fib(7)'), 13)
295 class DebugChangeString(DebugTest
):
297 text
= "This little piggy went to the market."
298 self
.gdb
.b("main:start")
300 self
.gdb
.p('fox = "%s"' % text
)
301 self
.exit(0x43b497b8)
303 class DebugTurbostep(DebugTest
):
305 """Single step a bunch of times."""
306 self
.gdb
.b("main:start")
308 self
.gdb
.command("p i=0")
314 pc
= self
.gdb
.p("$pc")
315 assertNotEqual(last_pc
, pc
)
316 if last_pc
and pc
> last_pc
and pc
- last_pc
<= 4:
321 # Some basic sanity that we're not running between breakpoints or
323 assertGreater(jumps
, 1)
324 assertGreater(advances
, 5)
326 class DebugExit(DebugTest
):
330 class DebugSymbols(DebugTest
):
334 output
= self
.gdb
.c()
335 assertIn(", main ", output
)
336 output
= self
.gdb
.c()
337 assertIn(", rot13 ", output
)
339 class DebugBreakpoint(DebugTest
):
342 # The breakpoint should be hit exactly 2 times.
344 output
= self
.gdb
.c()
346 assertIn("Breakpoint ", output
)
347 assertIn("rot13 ", output
)
350 class Hwbp1(DebugTest
):
352 if self
.hart
.instruction_hardware_breakpoint_count
< 1:
353 return 'not_applicable'
355 if not self
.hart
.honors_tdata1_hmode
:
356 # Run to main before setting the breakpoint, because startup code
357 # will otherwise clear the trigger that we set.
361 self
.gdb
.hbreak("rot13")
362 # The breakpoint should be hit exactly 2 times.
364 output
= self
.gdb
.c()
366 assertRegexpMatches(output
, r
"[bB]reakpoint")
367 assertIn("rot13 ", output
)
370 class Hwbp2(DebugTest
):
372 if self
.hart
.instruction_hardware_breakpoint_count
< 2:
373 return 'not_applicable'
375 self
.gdb
.hbreak("main")
376 self
.gdb
.hbreak("rot13")
377 # We should hit 3 breakpoints.
378 for expected
in ("main", "rot13", "rot13"):
379 output
= self
.gdb
.c()
381 assertRegexpMatches(output
, r
"[bB]reakpoint")
382 assertIn("%s " % expected
, output
)
385 class TooManyHwbp(DebugTest
):
388 self
.gdb
.hbreak("*rot13 + %d" % (i
* 4))
390 output
= self
.gdb
.c()
391 assertIn("Cannot insert hardware breakpoint", output
)
392 # Clean up, otherwise the hardware breakpoints stay set and future
394 self
.gdb
.command("D")
396 class Registers(DebugTest
):
398 # Get to a point in the code where some registers have actually been
403 # Try both forms to test gdb.
404 for cmd
in ("info all-registers", "info registers all"):
405 output
= self
.gdb
.command(cmd
)
406 for reg
in ('zero', 'ra', 'sp', 'gp', 'tp'):
407 assertIn(reg
, output
)
408 for line
in output
.splitlines():
409 assertRegexpMatches(line
, r
"^\S")
412 # mcpuid is one of the few registers that should have the high bit set
414 # Leave this commented out until gdb and spike agree on the encoding of
415 # mcpuid (which is going to be renamed to misa in any case).
416 #assertRegexpMatches(output, ".*mcpuid *0x80")
419 # The instret register should always be changing.
422 # instret = self.gdb.p("$instret")
423 # assertNotEqual(instret, last_instret)
424 # last_instret = instret
429 class UserInterrupt(DebugTest
):
431 """Sending gdb ^C while the program is running should cause it to
433 self
.gdb
.b("main:start")
436 self
.gdb
.c(wait
=False)
438 output
= self
.gdb
.interrupt()
439 assert "main" in output
440 assertGreater(self
.gdb
.p("j"), 10)
444 class InterruptTest(GdbSingleHartTest
):
445 compile_args
= ("programs/interrupt.c",)
447 def early_applicable(self
):
448 return self
.target
.supports_clint_mtime
455 output
= self
.gdb
.c()
456 assertIn(" main ", output
)
457 self
.gdb
.b("trap_entry")
458 output
= self
.gdb
.c()
459 assertIn(" trap_entry ", output
)
460 assertEqual(self
.gdb
.p("$mip") & 0x80, 0x80)
461 assertEqual(self
.gdb
.p("interrupt_count"), 0)
462 # You'd expect local to still be 0, but it looks like spike doesn't
463 # jump to the interrupt handler immediately after the write to
465 assertLess(self
.gdb
.p("local"), 1000)
466 self
.gdb
.command("delete breakpoints")
468 self
.gdb
.c(wait
=False)
471 interrupt_count
= self
.gdb
.p("interrupt_count")
472 local
= self
.gdb
.p("local")
473 if interrupt_count
> 1000 and \
477 assertGreater(interrupt_count
, 1000)
478 assertGreater(local
, 1000)
480 def postMortem(self
):
481 GdbSingleHartTest
.postMortem(self
)
482 self
.gdb
.p("*((long long*) 0x200bff8)")
483 self
.gdb
.p("*((long long*) 0x2004000)")
484 self
.gdb
.p("interrupt_count")
487 class MulticoreRegTest(GdbTest
):
488 compile_args
= ("programs/infinite_loop.S", "-DMULTICORE")
490 def early_applicable(self
):
491 return len(self
.target
.harts
) > 1
495 for hart
in self
.target
.harts
:
496 self
.gdb
.select_hart(hart
)
497 self
.gdb
.p("$pc=_start")
501 for hart
in self
.target
.harts
:
502 self
.gdb
.select_hart(hart
)
505 assertIn("main", self
.gdb
.where())
506 self
.gdb
.command("delete breakpoints")
508 # Run through the entire loop.
509 for hart
in self
.target
.harts
:
510 self
.gdb
.select_hart(hart
)
511 self
.gdb
.b("main_end")
513 assertIn("main_end", self
.gdb
.where())
516 for hart
in self
.target
.harts
:
517 self
.gdb
.select_hart(hart
)
518 # Check register values.
519 hart_id
= self
.gdb
.p("$x1")
520 assertNotIn(hart_id
, hart_ids
)
521 hart_ids
.append(hart_id
)
522 for n
in range(2, 32):
523 value
= self
.gdb
.p("$x%d" % n
)
524 assertEqual(value
, hart_ids
[-1] + n
- 1)
526 # Confirmed that we read different register values for different harts.
527 # Write a new value to x1, and run through the add sequence again.
529 for hart
in self
.target
.harts
:
530 self
.gdb
.select_hart(hart
)
531 self
.gdb
.p("$x1=0x%x" % (hart
.index
* 0x800))
532 self
.gdb
.p("$pc=main_post_csrr")
534 for hart
in self
.target
.harts
:
535 self
.gdb
.select_hart(hart
)
536 assertIn("main", self
.gdb
.where())
537 # Check register values.
538 for n
in range(1, 32):
539 value
= self
.gdb
.p("$x%d" % n
)
540 assertEqual(value
, hart
.index
* 0x800 + n
- 1)
542 class MulticoreRunHaltStepiTest(GdbTest
):
543 compile_args
= ("programs/multicore.c", "-DMULTICORE")
545 def early_applicable(self
):
546 return len(self
.target
.harts
) > 1
550 for hart
in self
.target
.harts
:
551 self
.gdb
.select_hart(hart
)
552 self
.gdb
.p("$pc=_start")
555 previous_hart_count
= [0 for h
in self
.target
.harts
]
556 previous_interrupt_count
= [0 for h
in self
.target
.harts
]
558 self
.gdb
.c(wait
=False)
563 self
.gdb
.p("$mstatus")
565 self
.gdb
.p("buf", fmt
="")
566 hart_count
= self
.gdb
.p("hart_count")
567 interrupt_count
= self
.gdb
.p("interrupt_count")
568 for i
, h
in enumerate(self
.target
.harts
):
569 assertGreater(hart_count
[i
], previous_hart_count
[i
])
570 assertGreater(interrupt_count
[i
], previous_interrupt_count
[i
])
571 self
.gdb
.select_hart(h
)
572 pc
= self
.gdb
.p("$pc")
574 stepped_pc
= self
.gdb
.p("$pc")
575 assertNotEqual(pc
, stepped_pc
)
577 class MulticoreRunAllHaltOne(GdbTest
):
578 compile_args
= ("programs/multicore.c", "-DMULTICORE")
580 def early_applicable(self
):
581 return len(self
.target
.harts
) > 1
584 self
.gdb
.select_hart(self
.target
.harts
[0])
586 for hart
in self
.target
.harts
:
587 self
.gdb
.select_hart(hart
)
588 self
.gdb
.p("$pc=_start")
591 if not self
.gdb
.one_hart_per_gdb():
592 return 'not_applicable'
594 # Run harts in reverse order
595 for h
in reversed(self
.target
.harts
):
596 self
.gdb
.select_hart(h
)
597 self
.gdb
.c(wait
=False)
600 # Give OpenOCD time to call poll() on both harts, which is what causes
603 self
.gdb
.p("buf", fmt
="")
605 class StepTest(GdbTest
):
606 compile_args
= ("programs/step.S", )
614 main_address
= self
.gdb
.p("$pc")
615 if self
.hart
.extensionSupported("c"):
616 sequence
= (4, 8, 0xc, 0xe, 0x14, 0x18, 0x22, 0x1c, 0x24, 0x24)
618 sequence
= (4, 8, 0xc, 0x10, 0x18, 0x1c, 0x28, 0x20, 0x2c, 0x2c)
619 for expected
in sequence
:
621 pc
= self
.gdb
.p("$pc")
622 assertEqual("%x" % (pc
- main_address
), "%x" % expected
)
624 class TriggerTest(GdbTest
):
625 compile_args
= ("programs/trigger.S", )
633 output
= self
.gdb
.c()
634 assertIn("Breakpoint", output
)
635 assertIn("_exit", output
)
637 class TriggerExecuteInstant(TriggerTest
):
638 """Test an execute breakpoint on the first instruction executed out of
641 main_address
= self
.gdb
.p("$pc")
642 self
.gdb
.command("hbreak *0x%x" % (main_address
+ 4))
644 assertEqual(self
.gdb
.p("$pc"), main_address
+4)
646 # FIXME: Triggers aren't quite working yet
647 #class TriggerLoadAddress(TriggerTest):
649 # self.gdb.command("rwatch *((&data)+1)")
650 # output = self.gdb.c()
651 # assertIn("read_loop", output)
652 # assertEqual(self.gdb.p("$a0"),
653 # self.gdb.p("(&data)+1"))
656 class TriggerLoadAddressInstant(TriggerTest
):
657 """Test a load address breakpoint on the first instruction executed out of
660 self
.gdb
.command("b just_before_read_loop")
662 read_loop
= self
.gdb
.p("&read_loop")
663 self
.gdb
.command("rwatch data")
665 # Accept hitting the breakpoint before or after the load instruction.
666 assertIn(self
.gdb
.p("$pc"), [read_loop
, read_loop
+ 4])
667 assertEqual(self
.gdb
.p("$a0"), self
.gdb
.p("&data"))
669 # FIXME: Triggers aren't quite working yet
670 #class TriggerStoreAddress(TriggerTest):
672 # self.gdb.command("watch *((&data)+3)")
673 # output = self.gdb.c()
674 # assertIn("write_loop", output)
675 # assertEqual(self.gdb.p("$a0"),
676 # self.gdb.p("(&data)+3"))
679 class TriggerStoreAddressInstant(TriggerTest
):
681 """Test a store address breakpoint on the first instruction executed out
683 self
.gdb
.command("b just_before_write_loop")
685 write_loop
= self
.gdb
.p("&write_loop")
686 self
.gdb
.command("watch data")
688 # Accept hitting the breakpoint before or after the store instruction.
689 assertIn(self
.gdb
.p("$pc"), [write_loop
, write_loop
+ 4])
690 assertEqual(self
.gdb
.p("$a0"), self
.gdb
.p("&data"))
692 class TriggerDmode(TriggerTest
):
693 def early_applicable(self
):
694 return self
.hart
.honors_tdata1_hmode
696 def check_triggers(self
, tdata1_lsbs
, tdata2
):
697 dmode
= 1 << (self
.hart
.xlen
-5)
701 if self
.hart
.xlen
== 32:
703 elif self
.hart
.xlen
== 64:
704 xlen_type
= 'long long'
706 raise NotImplementedError
711 tdata1
= self
.gdb
.p("((%s *)&data)[%d]" % (xlen_type
, 2*i
))
714 tdata2
= self
.gdb
.p("((%s *)&data)[%d]" % (xlen_type
, 2*i
+1))
719 assertEqual(tdata1
& 0xffff, tdata1_lsbs
)
720 assertEqual(tdata2
, tdata2
)
723 assertEqual(dmode_count
, 1)
728 self
.gdb
.command("hbreak write_load_trigger")
729 self
.gdb
.b("clear_triggers")
730 self
.gdb
.p("$pc=write_store_trigger")
731 output
= self
.gdb
.c()
732 assertIn("write_load_trigger", output
)
733 self
.check_triggers((1<<6) |
(1<<1), 0xdeadbee0)
734 output
= self
.gdb
.c()
735 assertIn("clear_triggers", output
)
736 self
.check_triggers((1<<6) |
(1<<0), 0xfeedac00)
738 class RegsTest(GdbTest
):
739 compile_args
= ("programs/regs.S", )
743 self
.gdb
.b("handle_trap")
746 class WriteGprs(RegsTest
):
748 regs
= [("x%d" % n
) for n
in range(2, 32)]
750 self
.gdb
.p("$pc=write_regs")
751 for i
, r
in enumerate(regs
):
752 self
.gdb
.p("$%s=%d" % (r
, (0xdeadbeef<<i
)+17))
753 self
.gdb
.p("$x1=data")
754 self
.gdb
.command("b all_done")
755 output
= self
.gdb
.c()
756 assertIn("Breakpoint ", output
)
758 # Just to get this data in the log.
759 self
.gdb
.command("x/30gx data")
760 self
.gdb
.command("info registers")
761 for n
in range(len(regs
)):
762 assertEqual(self
.gdb
.x("data+%d" % (8*n
), 'g'),
763 ((0xdeadbeef<<n
)+17) & ((1<<self
.hart
.xlen
)-1))
765 class WriteCsrs(RegsTest
):
767 # As much a test of gdb as of the simulator.
768 self
.gdb
.p("$mscratch=0")
770 assertEqual(self
.gdb
.p("$mscratch"), 0)
771 self
.gdb
.p("$mscratch=123")
773 assertEqual(self
.gdb
.p("$mscratch"), 123)
775 self
.gdb
.p("$pc=write_regs")
776 self
.gdb
.p("$x1=data")
777 self
.gdb
.command("b all_done")
778 self
.gdb
.command("c")
780 assertEqual(123, self
.gdb
.p("$mscratch"))
781 assertEqual(123, self
.gdb
.p("$x1"))
782 assertEqual(123, self
.gdb
.p("$csr832"))
784 class DownloadTest(GdbTest
):
786 # pylint: disable=attribute-defined-outside-init
787 length
= min(2**10, self
.hart
.ram_size
- 2048)
788 self
.download_c
= tempfile
.NamedTemporaryFile(prefix
="download_",
789 suffix
=".c", delete
=False)
790 self
.download_c
.write("#include <stdint.h>\n")
791 self
.download_c
.write(
792 "unsigned int crc32a(uint8_t *message, unsigned int size);\n")
793 self
.download_c
.write("uint32_t length = %d;\n" % length
)
794 self
.download_c
.write("uint8_t d[%d] = {\n" % length
)
796 assert length
% 16 == 0
797 for i
in range(length
/ 16):
798 self
.download_c
.write(" /* 0x%04x */ " % (i
* 16))
800 value
= random
.randrange(1<<8)
801 self
.download_c
.write("0x%02x, " % value
)
802 self
.crc
= binascii
.crc32("%c" % value
, self
.crc
)
803 self
.download_c
.write("\n")
804 self
.download_c
.write("};\n")
805 self
.download_c
.write("uint8_t *data = &d[0];\n")
806 self
.download_c
.write(
807 "uint32_t main() { return crc32a(data, length); }\n")
808 self
.download_c
.flush()
813 self
.binary
= self
.target
.compile(self
.hart
, self
.download_c
.name
,
814 "programs/checksum.c")
815 self
.gdb
.command("file %s" % self
.binary
)
819 self
.gdb
.command("b _exit")
820 self
.gdb
.c(timeout
=60)
821 assertEqual(self
.gdb
.p("status"), self
.crc
)
822 os
.unlink(self
.download_c
.name
)
824 #class MprvTest(GdbTest):
825 # compile_args = ("programs/mprv.S", )
830 # """Test that the debugger can access memory when MPRV is set."""
831 # self.gdb.c(wait=False)
833 # self.gdb.interrupt()
834 # output = self.gdb.command("p/x *(int*)(((char*)&data)-0x80000000)")
835 # assertIn("0xbead", output)
837 class PrivTest(GdbTest
):
838 compile_args
= ("programs/priv.S", )
840 # pylint: disable=attribute-defined-outside-init
843 misa
= self
.hart
.misa
844 self
.supported
= set()
846 self
.supported
.add(0)
848 self
.supported
.add(1)
850 self
.supported
.add(2)
851 self
.supported
.add(3)
853 class PrivRw(PrivTest
):
855 """Test reading/writing priv."""
856 # Disable physical memory protection by allowing U mode access to all
859 self
.gdb
.p("$pmpcfg0=0xf") # TOR, R, W, X
860 self
.gdb
.p("$pmpaddr0=0x%x" %
861 ((self
.hart
.ram
+ self
.hart
.ram_size
) >> 2))
862 except testlib
.CouldNotFetch
:
863 # PMP registers are optional
866 # Leave the PC at _start, where the first 4 instructions should be
868 for privilege
in range(4):
869 self
.gdb
.p("$priv=%d" % privilege
)
871 actual
= self
.gdb
.p("$priv")
872 assertIn(actual
, self
.supported
)
873 if privilege
in self
.supported
:
874 assertEqual(actual
, privilege
)
876 class PrivChange(PrivTest
):
878 """Test that the core's privilege level actually changes."""
880 if 0 not in self
.supported
:
881 return 'not_applicable'
887 self
.gdb
.p("$priv=3")
888 main_address
= self
.gdb
.p("$pc")
890 assertEqual("%x" % self
.gdb
.p("$pc"), "%x" % (main_address
+4))
893 self
.gdb
.p("$priv=0")
895 # Should have taken an exception, so be nowhere near main.
896 pc
= self
.gdb
.p("$pc")
897 assertTrue(pc
< main_address
or pc
> main_address
+ 0x100)
901 parser
= argparse
.ArgumentParser(
902 description
="Test that gdb can talk to a RISC-V target.",
904 Example command line from the real world:
905 Run all RegsTest cases against a physical FPGA, with custom openocd command:
906 ./gdbserver.py --freedom-e300 --server_cmd "$HOME/SiFive/openocd/src/openocd -s $HOME/SiFive/openocd/tcl -d" Simple
908 targets
.add_target_options(parser
)
910 testlib
.add_test_run_options(parser
)
912 # TODO: remove global
913 global parsed
# pylint: disable=global-statement
914 parsed
= parser
.parse_args()
915 target
= targets
.target(parsed
)
916 testlib
.print_log_names
= parsed
.print_log_names
918 module
= sys
.modules
[__name__
]
920 return testlib
.run_all_tests(module
, target
, parsed
)
922 # TROUBLESHOOTING TIPS
923 # If a particular test fails, run just that one test, eg.:
924 # ./gdbserver.py MprvTest.test_mprv
925 # Then inspect gdb.log and spike.log to see what happened in more detail.
927 if __name__
== '__main__':