1 // See LICENSE.SiFive for license details.
3 #include "spike/encoding.h"
5 // These are implementation-specific addresses in the Debug Module
9 #define EXCEPTION 0x10C
11 // Region of memory where each hart has 1
21 // Entry location on ebreak, Halt, or Breakpoint
22 // It is the same for all harts. They branch when
23 // their GO or RESUME bit is set.
33 // This fence is required because the execution may have written something
34 // into the Abstract Data or Program Buffer registers.
36 csrw CSR_DSCRATCH, s0 // Save s0 to allow signaling MHARTID
38 // We continue to let the hart know that we are halted in order that
39 // a DM which was reset is still made aware that a hart is halted.
40 // We keep checking both whether there is something the debugger wants
41 // us to do, or whether we should resume.
45 lbu s0, FLAGS(s0) // 1 byte flag per hart. Only one hart advances here.
46 andi s0, s0, (1 << FLAG_GO)
49 lbu s0, FLAGS(s0) // multiple harts can resume here
50 andi s0, s0, (1 << FLAG_RESUME)
55 sw zero, EXCEPTION(zero) // Let debug module know you got an exception.
59 csrr s0, CSR_DSCRATCH // Restore s0 here
60 sw zero, GOING(zero) // When debug module sees this write, the GO flag is reset.
61 jalr zero, zero, %lo(whereto) // Rocket-Chip has a specific hack which is that jalr in
62 // Debug Mode will flush the I-Cache. We need that so that the
63 // remainder of the variable instructions will be what Debug Module
67 sw s0, RESUMING(zero) // When Debug Module sees this write, the RESUME flag is reset.
68 csrr s0, CSR_DSCRATCH // Restore s0
71 // END OF ACTUAL "ROM" CONTENTS. BELOW IS JUST FOR LINKER SCRIPT.
76 // Variable "ROM" This is : jal x0 abstract, jal x0 program_buffer,
77 // or jal x0 resume, as desired.
78 // Debug Module state machine tracks what is 'desired'.
79 // We don't need/want to use jalr here because all of the
80 // Variable ROM contents are set by
81 // Debug Module before setting the OK_GO byte.