decode2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.insn_helpers.all;
  10
  11 entity decode2 is
  12     generic (
  13         EX1_BYPASS : boolean := true;
  14         HAS_FPU : boolean := true;
  15         -- Non-zero to enable log data collection
  16         LOG_LENGTH : natural := 0
  17         );
  18     port (
  19         clk   : in std_ulogic;
  20         rst   : in std_ulogic;
  21
  22         complete_in : in instr_tag_t;
  23         busy_in   : in std_ulogic;
  24         stall_out : out std_ulogic;
  25
  26         stopped_out : out std_ulogic;
  27
  28         flush_in: in std_ulogic;
  29
  30         d_in  : in Decode1ToDecode2Type;
  31
  32         e_out : out Decode2ToExecute1Type;
  33
  34         r_in  : in RegisterFileToDecode2Type;
  35         r_out : out Decode2ToRegisterFileType;
  36
  37         c_in  : in CrFileToDecode2Type;
  38         c_out : out Decode2ToCrFileType;
  39
  40         execute_bypass   : in bypass_data_t;
  41
  42         log_out : out std_ulogic_vector(9 downto 0)
  43         );
  44 end entity decode2;
  45
  46 architecture behaviour of decode2 is
  47     type reg_type is record
  48         e : Decode2ToExecute1Type;
  49         repeat : std_ulogic;
  50     end record;
  51
  52     signal r, rin : reg_type;
  53
  54     signal deferred : std_ulogic;
  55
  56     type decode_input_reg_t is record
  57         reg_valid : std_ulogic;
  58         reg       : gspr_index_t;
  59         data      : std_ulogic_vector(63 downto 0);
  60     end record;
  61
  62     type decode_output_reg_t is record
  63         reg_valid : std_ulogic;
  64         reg       : gspr_index_t;
  65     end record;
  66
  67     function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
  68                                  reg_data : std_ulogic_vector(63 downto 0);
  69                                  ispr : gspr_index_t;
  70                                  instr_addr : std_ulogic_vector(63 downto 0))
  71         return decode_input_reg_t is
  72     begin
  73         if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
  74             return ('1', gpr_to_gspr(insn_ra(insn_in)), reg_data);
  75         elsif t = SPR then
  76             -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
  77             -- If it's all 0, we don't treat it as a dependency as slow SPRs
  78             -- operations are single issue.
  79             --
  80             assert is_fast_spr(ispr) =  '1' or ispr = "0000000"
  81                 report "Decode A says SPR but ISPR is invalid:" &
  82                 to_hstring(ispr) severity failure;
  83             return (is_fast_spr(ispr), ispr, reg_data);
  84         elsif t = CIA then
  85             return ('0', (others => '0'), instr_addr);
  86         elsif HAS_FPU and t = FRA then
  87             return ('1', fpr_to_gspr(insn_fra(insn_in)), reg_data);
  88         else
  89             return ('0', (others => '0'), (others => '0'));
  90         end if;
  91     end;
  92
  93     function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
  94                                  reg_data : std_ulogic_vector(63 downto 0);
  95                                  ispr : gspr_index_t) return decode_input_reg_t is
  96         variable ret : decode_input_reg_t;
  97     begin
  98         case t is
  99             when RB =>
 100                 ret := ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
 101             when FRB =>
 102                 if HAS_FPU then
 103                     ret := ('1', fpr_to_gspr(insn_frb(insn_in)), reg_data);
 104                 else
 105                     ret := ('0', (others => '0'), (others => '0'));
 106                 end if;
 107             when CONST_UI =>
 108                 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
 109             when CONST_SI =>
 110                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
 111             when CONST_SI_HI =>
 112                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
 113             when CONST_UI_HI =>
 114                 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
 115             when CONST_LI =>
 116                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
 117             when CONST_BD =>
 118                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
 119             when CONST_DS =>
 120                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
 121             when CONST_DQ =>
 122                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dq(insn_in)) & "0000", 64)));
 123             when CONST_DXHI4 =>
 124                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dx(insn_in)) & x"0004", 64)));
 125             when CONST_M1 =>
 126                 ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
 127             when CONST_SH =>
 128                 ret := ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
 129             when CONST_SH32 =>
 130                 ret := ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
 131             when SPR =>
 132                 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 133                 -- If it's all 0, we don't treat it as a dependency as slow SPRs
 134                 -- operations are single issue.
 135                 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
 136                     report "Decode B says SPR but ISPR is invalid:" &
 137                     to_hstring(ispr) severity failure;
 138                 ret := (is_fast_spr(ispr), ispr, reg_data);
 139             when NONE =>
 140                 ret := ('0', (others => '0'), (others => '0'));
 141         end case;
 142
 143         return ret;
 144     end;
 145
 146     function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
 147                                  reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
 148     begin
 149         case t is
 150             when RS =>
 151                 return ('1', gpr_to_gspr(insn_rs(insn_in)), reg_data);
 152             when RCR =>
 153                 return ('1', gpr_to_gspr(insn_rcreg(insn_in)), reg_data);
 154             when FRS =>
 155                 if HAS_FPU then
 156                     return ('1', fpr_to_gspr(insn_frt(insn_in)), reg_data);
 157                 else
 158                     return ('0', (others => '0'), (others => '0'));
 159                 end if;
 160             when FRC =>
 161                 if HAS_FPU then
 162                     return ('1', fpr_to_gspr(insn_frc(insn_in)), reg_data);
 163                 else
 164                     return ('0', (others => '0'), (others => '0'));
 165                 end if;
 166             when NONE =>
 167                 return ('0', (others => '0'), (others => '0'));
 168         end case;
 169     end;
 170
 171     function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
 172                                 ispr : gspr_index_t) return decode_output_reg_t is
 173     begin
 174         case t is
 175             when RT =>
 176                 return ('1', gpr_to_gspr(insn_rt(insn_in)));
 177             when RA =>
 178                 return ('1', gpr_to_gspr(insn_ra(insn_in)));
 179             when FRT =>
 180                 if HAS_FPU then
 181                     return ('1', fpr_to_gspr(insn_frt(insn_in)));
 182                 else
 183                     return ('0', "0000000");
 184                 end if;
 185             when SPR =>
 186                 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 187                 -- If it's all 0, we don't treat it as a dependency as slow SPRs
 188                 -- operations are single issue.
 189                 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
 190                     report "Decode B says SPR but ISPR is invalid:" &
 191                     to_hstring(ispr) severity failure;
 192                 return (is_fast_spr(ispr), ispr);
 193             when NONE =>
 194                 return ('0', "0000000");
 195         end case;
 196     end;
 197
 198     function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 199     begin
 200         case t is
 201             when RC =>
 202                 return insn_rc(insn_in);
 203             when ONE =>
 204                 return '1';
 205             when NONE =>
 206                 return '0';
 207         end case;
 208     end;
 209
 210     -- For now, use "rc" in the decode table to decide whether oe exists.
 211     -- This is not entirely correct architecturally: For mulhd and
 212     -- mulhdu, the OE field is reserved. It remains to be seen what an
 213     -- actual POWER9 does if we set it on those instructions, for now we
 214     -- test that further down when assigning to the multiplier oe input.
 215     --
 216     function decode_oe (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 217     begin
 218         case t is
 219             when RC =>
 220                 return insn_oe(insn_in);
 221             when OTHERS =>
 222                 return '0';
 223         end case;
 224     end;
 225
 226     -- control signals that are derived from insn_type
 227     type mux_select_array_t is array(insn_type_t) of std_ulogic_vector(2 downto 0);
 228
 229     constant result_select : mux_select_array_t := (
 230         OP_AND      => "001",           -- logical_result
 231         OP_OR       => "001",
 232         OP_XOR      => "001",
 233         OP_POPCNT   => "001",
 234         OP_PRTY     => "001",
 235         OP_CMPB     => "001",
 236         OP_EXTS     => "001",
 237         OP_BPERM    => "001",
 238         OP_BCD      => "001",
 239         OP_MTSPR    => "001",
 240         OP_RLC      => "010",           -- rotator_result
 241         OP_RLCL     => "010",
 242         OP_RLCR     => "010",
 243         OP_SHL      => "010",
 244         OP_SHR      => "010",
 245         OP_EXTSWSLI => "010",
 246         OP_MUL_L64  => "011",           -- muldiv_result
 247         OP_MUL_H64  => "011",
 248         OP_MUL_H32  => "011",
 249         OP_DIV      => "011",
 250         OP_DIVE     => "011",
 251         OP_MOD      => "011",
 252         OP_CNTZ     => "100",           -- countzero_result
 253         OP_MFSPR    => "101",           -- spr_result
 254         OP_B        => "110",           -- next_nia
 255         OP_BC       => "110",
 256         OP_BCREG    => "110",
 257         OP_ADDG6S   => "111",           -- misc_result
 258         OP_ISEL     => "111",
 259         OP_DARN     => "111",
 260         OP_MFMSR    => "111",
 261         OP_MFCR     => "111",
 262         OP_SETB     => "111",
 263         others      => "000"            -- default to adder_result
 264         );
 265
 266     constant subresult_select : mux_select_array_t := (
 267         OP_MUL_L64 => "000",            -- muldiv_result
 268         OP_MUL_H64 => "001",
 269         OP_MUL_H32 => "010",
 270         OP_DIV     => "011",
 271         OP_DIVE    => "011",
 272         OP_MOD     => "011",
 273         OP_ADDG6S  => "001",            -- misc_result
 274         OP_ISEL    => "010",
 275         OP_DARN    => "011",
 276         OP_MFMSR   => "100",
 277         OP_MFCR    => "101",
 278         OP_SETB    => "110",
 279         others     => "000"
 280         );
 281
 282     -- issue control signals
 283     signal control_valid_in : std_ulogic;
 284     signal control_valid_out : std_ulogic;
 285     signal control_stall_out : std_ulogic;
 286     signal control_sgl_pipe : std_logic;
 287
 288     signal gpr_write_valid : std_ulogic;
 289     signal gpr_write : gspr_index_t;
 290
 291     signal gpr_a_read_valid : std_ulogic;
 292     signal gpr_a_read       : gspr_index_t;
 293     signal gpr_a_bypass     : std_ulogic;
 294
 295     signal gpr_b_read_valid : std_ulogic;
 296     signal gpr_b_read       : gspr_index_t;
 297     signal gpr_b_bypass     : std_ulogic;
 298
 299     signal gpr_c_read_valid : std_ulogic;
 300     signal gpr_c_read       : gspr_index_t;
 301     signal gpr_c_bypass     : std_ulogic;
 302
 303     signal cr_write_valid  : std_ulogic;
 304     signal cr_bypass       : std_ulogic;
 305     signal cr_bypass_avail : std_ulogic;
 306
 307     signal instr_tag       : instr_tag_t;
 308
 309 begin
 310     control_0: entity work.control
 311         generic map (
 312             EX1_BYPASS => EX1_BYPASS,
 313             PIPELINE_DEPTH => 1
 314             )
 315         port map (
 316             clk         => clk,
 317             rst         => rst,
 318
 319             complete_in => complete_in,
 320             valid_in    => control_valid_in,
 321             repeated    => r.repeat,
 322             busy_in     => busy_in,
 323             deferred    => deferred,
 324             flush_in    => flush_in,
 325             sgl_pipe_in => control_sgl_pipe,
 326             stop_mark_in => d_in.stop_mark,
 327
 328             gpr_write_valid_in => gpr_write_valid,
 329             gpr_write_in       => gpr_write,
 330
 331             gpr_a_read_valid_in  => gpr_a_read_valid,
 332             gpr_a_read_in        => gpr_a_read,
 333
 334             gpr_b_read_valid_in  => gpr_b_read_valid,
 335             gpr_b_read_in        => gpr_b_read,
 336
 337             gpr_c_read_valid_in  => gpr_c_read_valid,
 338             gpr_c_read_in        => gpr_c_read,
 339
 340             execute_next_tag     => execute_bypass.tag,
 341
 342             cr_read_in           => d_in.decode.input_cr,
 343             cr_write_in          => cr_write_valid,
 344             cr_bypass            => cr_bypass,
 345             cr_bypassable        => cr_bypass_avail,
 346
 347             valid_out   => control_valid_out,
 348             stall_out   => control_stall_out,
 349             stopped_out => stopped_out,
 350
 351             gpr_bypass_a => gpr_a_bypass,
 352             gpr_bypass_b => gpr_b_bypass,
 353             gpr_bypass_c => gpr_c_bypass,
 354
 355             instr_tag_out => instr_tag
 356             );
 357
 358     deferred <= r.e.valid and busy_in;
 359
 360     decode2_0: process(clk)
 361     begin
 362         if rising_edge(clk) then
 363             if rst = '1' or flush_in = '1' or deferred = '0' then
 364                 if rin.e.valid = '1' then
 365                     report "execute " & to_hstring(rin.e.nia);
 366                 end if;
 367                 r <= rin;
 368             end if;
 369         end if;
 370     end process;
 371
 372     c_out.read <= d_in.decode.input_cr;
 373
 374     decode2_1: process(all)
 375         variable v : reg_type;
 376         variable mul_a : std_ulogic_vector(63 downto 0);
 377         variable mul_b : std_ulogic_vector(63 downto 0);
 378         variable decoded_reg_a : decode_input_reg_t;
 379         variable decoded_reg_b : decode_input_reg_t;
 380         variable decoded_reg_c : decode_input_reg_t;
 381         variable decoded_reg_o : decode_output_reg_t;
 382         variable length : std_ulogic_vector(3 downto 0);
 383         variable op : insn_type_t;
 384     begin
 385         v := r;
 386
 387         v.e := Decode2ToExecute1Init;
 388
 389         mul_a := (others => '0');
 390         mul_b := (others => '0');
 391
 392         --v.e.input_cr := d_in.decode.input_cr;
 393         v.e.output_cr := d_in.decode.output_cr;
 394
 395         decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data, d_in.ispr1,
 396                                              d_in.nia);
 397         decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data, d_in.ispr2);
 398         decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
 399         decoded_reg_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn, d_in.ispro);
 400
 401         if d_in.decode.lr = '1' then
 402             v.e.lr := insn_lk(d_in.insn);
 403             -- b and bc have even major opcodes; bcreg is considered absolute
 404             v.e.br_abs := insn_aa(d_in.insn) or d_in.insn(26);
 405         end if;
 406         op := d_in.decode.insn_type;
 407
 408         if d_in.decode.repeat /= NONE then
 409             v.e.repeat := '1';
 410             v.e.second := r.repeat;
 411             case d_in.decode.repeat is
 412                 when DRSE =>
 413                     -- do RS|1,RS for LE; RS,RS|1 for BE
 414                     if r.repeat = d_in.big_endian then
 415                         decoded_reg_c.reg(0) := '1';
 416                     end if;
 417                 when DRTE =>
 418                     -- do RT|1,RT for LE; RT,RT|1 for BE
 419                     if r.repeat = d_in.big_endian then
 420                         decoded_reg_o.reg(0) := '1';
 421                     end if;
 422                 when DUPD =>
 423                     -- update-form loads, 2nd instruction writes RA
 424                     if r.repeat = '1' then
 425                         decoded_reg_o.reg := decoded_reg_a.reg;
 426                     end if;
 427                 when others =>
 428             end case;
 429         elsif v.e.lr = '1' and decoded_reg_a.reg_valid = '1' then
 430             -- bcl/bclrl/bctarl that needs to write both CTR and LR has to be doubled
 431             v.e.repeat := '1';
 432             v.e.second := r.repeat;
 433             -- first one does CTR, second does LR
 434             decoded_reg_o.reg(0) := not r.repeat;
 435         end if;
 436
 437         r_out.read1_enable <= decoded_reg_a.reg_valid and d_in.valid;
 438         r_out.read1_reg    <= decoded_reg_a.reg;
 439         r_out.read2_enable <= decoded_reg_b.reg_valid and d_in.valid;
 440         r_out.read2_reg    <= decoded_reg_b.reg;
 441         r_out.read3_enable <= decoded_reg_c.reg_valid and d_in.valid;
 442         r_out.read3_reg    <= decoded_reg_c.reg;
 443
 444         case d_in.decode.length is
 445             when is1B =>
 446                 length := "0001";
 447             when is2B =>
 448                 length := "0010";
 449             when is4B =>
 450                 length := "0100";
 451             when is8B =>
 452                 length := "1000";
 453             when NONE =>
 454                 length := "0000";
 455         end case;
 456
 457         -- execute unit
 458         v.e.nia := d_in.nia;
 459         v.e.unit := d_in.decode.unit;
 460         v.e.fac := d_in.decode.facility;
 461         v.e.instr_tag := instr_tag;
 462         v.e.read_reg1 := decoded_reg_a.reg;
 463         v.e.read_reg2 := decoded_reg_b.reg;
 464         v.e.write_reg := decoded_reg_o.reg;
 465         v.e.write_reg_enable := decoded_reg_o.reg_valid;
 466         v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
 467         if not (d_in.decode.insn_type = OP_MUL_H32 or d_in.decode.insn_type = OP_MUL_H64) then
 468             v.e.oe := decode_oe(d_in.decode.rc, d_in.insn);
 469         end if;
 470         v.e.cr := c_in.read_cr_data;
 471         v.e.bypass_cr := cr_bypass;
 472         v.e.xerc := c_in.read_xerc_data;
 473         v.e.invert_a := d_in.decode.invert_a;
 474         v.e.addm1 := '0';
 475         v.e.insn_type := op;
 476         v.e.invert_out := d_in.decode.invert_out;
 477         v.e.input_carry := d_in.decode.input_carry;
 478         v.e.output_carry := d_in.decode.output_carry;
 479         v.e.is_32bit := d_in.decode.is_32bit;
 480         v.e.is_signed := d_in.decode.is_signed;
 481         v.e.insn := d_in.insn;
 482         v.e.data_len := length;
 483         v.e.byte_reverse := d_in.decode.byte_reverse;
 484         v.e.sign_extend := d_in.decode.sign_extend;
 485         v.e.update := d_in.decode.update;
 486         v.e.reserve := d_in.decode.reserve;
 487         v.e.br_pred := d_in.br_pred;
 488         v.e.result_sel := result_select(op);
 489         v.e.sub_select := subresult_select(op);
 490         if op = OP_BC or op = OP_BCREG then
 491             if d_in.insn(23) = '0' and r.repeat = '0' and
 492                 not (d_in.decode.insn_type = OP_BCREG and d_in.insn(10) = '0') then
 493                 -- decrement CTR if BO(2) = 0 and not bcctr
 494                 v.e.addm1 := '1';
 495                 v.e.result_sel := "000";        -- select adder output
 496             end if;
 497         end if;
 498
 499         -- See if any of the operands can get their value via the bypass path.
 500         case gpr_a_bypass is
 501             when '1' =>
 502                 v.e.read_data1 := execute_bypass.data;
 503             when others =>
 504                 v.e.read_data1 := decoded_reg_a.data;
 505         end case;
 506         case gpr_b_bypass is
 507             when '1' =>
 508                 v.e.read_data2 := execute_bypass.data;
 509             when others =>
 510                 v.e.read_data2 := decoded_reg_b.data;
 511         end case;
 512         case gpr_c_bypass is
 513             when '1' =>
 514                 v.e.read_data3 := execute_bypass.data;
 515             when others =>
 516                 v.e.read_data3 := decoded_reg_c.data;
 517         end case;
 518
 519         -- issue control
 520         control_valid_in <= d_in.valid;
 521         control_sgl_pipe <= d_in.decode.sgl_pipe;
 522
 523         gpr_write_valid <= v.e.write_reg_enable;
 524         gpr_write <= decoded_reg_o.reg;
 525
 526         gpr_a_read_valid <= decoded_reg_a.reg_valid;
 527         gpr_a_read <= decoded_reg_a.reg;
 528
 529         gpr_b_read_valid <= decoded_reg_b.reg_valid;
 530         gpr_b_read <= decoded_reg_b.reg;
 531
 532         gpr_c_read_valid <= decoded_reg_c.reg_valid;
 533         gpr_c_read <= decoded_reg_c.reg;
 534
 535         cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
 536         cr_bypass_avail <= '0';
 537         if EX1_BYPASS and d_in.decode.unit = ALU then
 538             cr_bypass_avail <= d_in.decode.output_cr;
 539         end if;
 540
 541         v.e.valid := control_valid_out;
 542         if control_valid_out = '1' then
 543             v.repeat := v.e.repeat and not r.repeat;
 544         end if;
 545
 546         stall_out <= control_stall_out or v.repeat;
 547
 548         if rst = '1' or flush_in = '1' then
 549             v.e := Decode2ToExecute1Init;
 550             v.repeat := '0';
 551         end if;
 552
 553         -- Update registers
 554         rin <= v;
 555
 556         -- Update outputs
 557         e_out <= r.e;
 558     end process;
 559
 560     d2_log: if LOG_LENGTH > 0 generate
 561         signal log_data : std_ulogic_vector(9 downto 0);
 562     begin
 563         dec2_log : process(clk)
 564         begin
 565             if rising_edge(clk) then
 566                 log_data <= r.e.nia(5 downto 2) &
 567                             r.e.valid &
 568                             stopped_out &
 569                             stall_out &
 570                             gpr_a_bypass &
 571                             gpr_b_bypass &
 572                             gpr_c_bypass;
 573             end if;
 574         end process;
 575         log_out <= log_data;
 576     end generate;
 577
 578 end architecture behaviour;