decode2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.insn_helpers.all;
  10
  11 entity decode2 is
  12     generic (
  13         EX1_BYPASS : boolean := true;
  14         HAS_FPU : boolean := true;
  15         -- Non-zero to enable log data collection
  16         LOG_LENGTH : natural := 0
  17         );
  18     port (
  19         clk   : in std_ulogic;
  20         rst   : in std_ulogic;
  21
  22         complete_in : in instr_tag_t;
  23         busy_in   : in std_ulogic;
  24         stall_out : out std_ulogic;
  25
  26         stopped_out : out std_ulogic;
  27
  28         flush_in: in std_ulogic;
  29
  30         d_in  : in Decode1ToDecode2Type;
  31
  32         e_out : out Decode2ToExecute1Type;
  33
  34         r_in  : in RegisterFileToDecode2Type;
  35         r_out : out Decode2ToRegisterFileType;
  36
  37         c_in  : in CrFileToDecode2Type;
  38         c_out : out Decode2ToCrFileType;
  39
  40         execute_bypass    : in bypass_data_t;
  41         execute_cr_bypass : in cr_bypass_data_t;
  42
  43         log_out : out std_ulogic_vector(9 downto 0)
  44         );
  45 end entity decode2;
  46
  47 architecture behaviour of decode2 is
  48     type reg_type is record
  49         e : Decode2ToExecute1Type;
  50         repeat : std_ulogic;
  51     end record;
  52
  53     signal r, rin : reg_type;
  54
  55     signal deferred : std_ulogic;
  56
  57     type decode_input_reg_t is record
  58         reg_valid : std_ulogic;
  59         reg       : gspr_index_t;
  60         data      : std_ulogic_vector(63 downto 0);
  61     end record;
  62
  63     type decode_output_reg_t is record
  64         reg_valid : std_ulogic;
  65         reg       : gspr_index_t;
  66     end record;
  67
  68     function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
  69                                  reg_data : std_ulogic_vector(63 downto 0);
  70                                  ispr : gspr_index_t;
  71                                  instr_addr : std_ulogic_vector(63 downto 0))
  72         return decode_input_reg_t is
  73     begin
  74         if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
  75             return ('1', gpr_to_gspr(insn_ra(insn_in)), reg_data);
  76         elsif t = SPR then
  77             -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
  78             -- If it's all 0, we don't treat it as a dependency as slow SPRs
  79             -- operations are single issue.
  80             --
  81             assert is_fast_spr(ispr) =  '1' or ispr = "0000000"
  82                 report "Decode A says SPR but ISPR is invalid:" &
  83                 to_hstring(ispr) severity failure;
  84             return (is_fast_spr(ispr), ispr, reg_data);
  85         elsif t = CIA then
  86             return ('0', (others => '0'), instr_addr);
  87         elsif HAS_FPU and t = FRA then
  88             return ('1', fpr_to_gspr(insn_fra(insn_in)), reg_data);
  89         else
  90             return ('0', (others => '0'), (others => '0'));
  91         end if;
  92     end;
  93
  94     function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
  95                                  reg_data : std_ulogic_vector(63 downto 0);
  96                                  ispr : gspr_index_t) return decode_input_reg_t is
  97         variable ret : decode_input_reg_t;
  98     begin
  99         case t is
 100             when RB =>
 101                 ret := ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
 102             when FRB =>
 103                 if HAS_FPU then
 104                     ret := ('1', fpr_to_gspr(insn_frb(insn_in)), reg_data);
 105                 else
 106                     ret := ('0', (others => '0'), (others => '0'));
 107                 end if;
 108             when CONST_UI =>
 109                 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
 110             when CONST_SI =>
 111                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
 112             when CONST_SI_HI =>
 113                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
 114             when CONST_UI_HI =>
 115                 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
 116             when CONST_LI =>
 117                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
 118             when CONST_BD =>
 119                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
 120             when CONST_DS =>
 121                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
 122             when CONST_DQ =>
 123                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dq(insn_in)) & "0000", 64)));
 124             when CONST_DXHI4 =>
 125                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dx(insn_in)) & x"0004", 64)));
 126             when CONST_M1 =>
 127                 ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
 128             when CONST_SH =>
 129                 ret := ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
 130             when CONST_SH32 =>
 131                 ret := ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
 132             when SPR =>
 133                 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 134                 -- If it's all 0, we don't treat it as a dependency as slow SPRs
 135                 -- operations are single issue.
 136                 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
 137                     report "Decode B says SPR but ISPR is invalid:" &
 138                     to_hstring(ispr) severity failure;
 139                 ret := (is_fast_spr(ispr), ispr, reg_data);
 140             when NONE =>
 141                 ret := ('0', (others => '0'), (others => '0'));
 142         end case;
 143
 144         return ret;
 145     end;
 146
 147     function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
 148                                  reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
 149     begin
 150         case t is
 151             when RS =>
 152                 return ('1', gpr_to_gspr(insn_rs(insn_in)), reg_data);
 153             when RCR =>
 154                 return ('1', gpr_to_gspr(insn_rcreg(insn_in)), reg_data);
 155             when FRS =>
 156                 if HAS_FPU then
 157                     return ('1', fpr_to_gspr(insn_frt(insn_in)), reg_data);
 158                 else
 159                     return ('0', (others => '0'), (others => '0'));
 160                 end if;
 161             when FRC =>
 162                 if HAS_FPU then
 163                     return ('1', fpr_to_gspr(insn_frc(insn_in)), reg_data);
 164                 else
 165                     return ('0', (others => '0'), (others => '0'));
 166                 end if;
 167             when NONE =>
 168                 return ('0', (others => '0'), (others => '0'));
 169         end case;
 170     end;
 171
 172     function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
 173                                 ispr : gspr_index_t) return decode_output_reg_t is
 174     begin
 175         case t is
 176             when RT =>
 177                 return ('1', gpr_to_gspr(insn_rt(insn_in)));
 178             when RA =>
 179                 return ('1', gpr_to_gspr(insn_ra(insn_in)));
 180             when FRT =>
 181                 if HAS_FPU then
 182                     return ('1', fpr_to_gspr(insn_frt(insn_in)));
 183                 else
 184                     return ('0', "0000000");
 185                 end if;
 186             when SPR =>
 187                 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 188                 -- If it's all 0, we don't treat it as a dependency as slow SPRs
 189                 -- operations are single issue.
 190                 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
 191                     report "Decode B says SPR but ISPR is invalid:" &
 192                     to_hstring(ispr) severity failure;
 193                 return (is_fast_spr(ispr), ispr);
 194             when NONE =>
 195                 return ('0', "0000000");
 196         end case;
 197     end;
 198
 199     function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 200     begin
 201         case t is
 202             when RC =>
 203                 return insn_rc(insn_in);
 204             when ONE =>
 205                 return '1';
 206             when NONE =>
 207                 return '0';
 208         end case;
 209     end;
 210
 211     -- control signals that are derived from insn_type
 212     type mux_select_array_t is array(insn_type_t) of std_ulogic_vector(2 downto 0);
 213
 214     constant result_select : mux_select_array_t := (
 215         OP_AND      => "001",           -- logical_result
 216         OP_OR       => "001",
 217         OP_XOR      => "001",
 218         OP_POPCNT   => "001",
 219         OP_PRTY     => "001",
 220         OP_CMPB     => "001",
 221         OP_EXTS     => "001",
 222         OP_BPERM    => "001",
 223         OP_BCD      => "001",
 224         OP_MTSPR    => "001",
 225         OP_RLC      => "010",           -- rotator_result
 226         OP_RLCL     => "010",
 227         OP_RLCR     => "010",
 228         OP_SHL      => "010",
 229         OP_SHR      => "010",
 230         OP_EXTSWSLI => "010",
 231         OP_MUL_L64  => "011",           -- muldiv_result
 232         OP_MUL_H64  => "011",
 233         OP_MUL_H32  => "011",
 234         OP_DIV      => "011",
 235         OP_DIVE     => "011",
 236         OP_MOD      => "011",
 237         OP_CNTZ     => "100",           -- countzero_result
 238         OP_MFSPR    => "101",           -- spr_result
 239         OP_B        => "110",           -- next_nia
 240         OP_BC       => "110",
 241         OP_BCREG    => "110",
 242         OP_ADDG6S   => "111",           -- misc_result
 243         OP_ISEL     => "111",
 244         OP_DARN     => "111",
 245         OP_MFMSR    => "111",
 246         OP_MFCR     => "111",
 247         OP_SETB     => "111",
 248         others      => "000"            -- default to adder_result
 249         );
 250
 251     constant subresult_select : mux_select_array_t := (
 252         OP_MUL_L64 => "000",            -- muldiv_result
 253         OP_MUL_H64 => "001",
 254         OP_MUL_H32 => "010",
 255         OP_DIV     => "011",
 256         OP_DIVE    => "011",
 257         OP_MOD     => "011",
 258         OP_ADDG6S  => "001",            -- misc_result
 259         OP_ISEL    => "010",
 260         OP_DARN    => "011",
 261         OP_MFMSR   => "100",
 262         OP_MFCR    => "101",
 263         OP_SETB    => "110",
 264         OP_CMP     => "000",            -- cr_result
 265         OP_CMPRB   => "001",
 266         OP_CMPEQB  => "010",
 267         OP_CROP    => "011",
 268         OP_MCRXRX  => "100",
 269         OP_MTCRF   => "101",
 270         others     => "000"
 271         );
 272
 273     -- issue control signals
 274     signal control_valid_in : std_ulogic;
 275     signal control_valid_out : std_ulogic;
 276     signal control_stall_out : std_ulogic;
 277     signal control_sgl_pipe : std_logic;
 278
 279     signal gpr_write_valid : std_ulogic;
 280     signal gpr_write : gspr_index_t;
 281
 282     signal gpr_a_read_valid : std_ulogic;
 283     signal gpr_a_read       : gspr_index_t;
 284     signal gpr_a_bypass     : std_ulogic;
 285
 286     signal gpr_b_read_valid : std_ulogic;
 287     signal gpr_b_read       : gspr_index_t;
 288     signal gpr_b_bypass     : std_ulogic;
 289
 290     signal gpr_c_read_valid : std_ulogic;
 291     signal gpr_c_read       : gspr_index_t;
 292     signal gpr_c_bypass     : std_ulogic;
 293
 294     signal cr_read_valid   : std_ulogic;
 295     signal cr_write_valid  : std_ulogic;
 296     signal cr_bypass       : std_ulogic;
 297
 298     signal instr_tag       : instr_tag_t;
 299
 300 begin
 301     control_0: entity work.control
 302         generic map (
 303             EX1_BYPASS => EX1_BYPASS,
 304             PIPELINE_DEPTH => 1
 305             )
 306         port map (
 307             clk         => clk,
 308             rst         => rst,
 309
 310             complete_in => complete_in,
 311             valid_in    => control_valid_in,
 312             repeated    => r.repeat,
 313             busy_in     => busy_in,
 314             deferred    => deferred,
 315             flush_in    => flush_in,
 316             sgl_pipe_in => control_sgl_pipe,
 317             stop_mark_in => d_in.stop_mark,
 318
 319             gpr_write_valid_in => gpr_write_valid,
 320             gpr_write_in       => gpr_write,
 321
 322             gpr_a_read_valid_in  => gpr_a_read_valid,
 323             gpr_a_read_in        => gpr_a_read,
 324
 325             gpr_b_read_valid_in  => gpr_b_read_valid,
 326             gpr_b_read_in        => gpr_b_read,
 327
 328             gpr_c_read_valid_in  => gpr_c_read_valid,
 329             gpr_c_read_in        => gpr_c_read,
 330
 331             execute_next_tag     => execute_bypass.tag,
 332             execute_next_cr_tag  => execute_cr_bypass.tag,
 333
 334             cr_read_in           => cr_read_valid,
 335             cr_write_in          => cr_write_valid,
 336             cr_bypass            => cr_bypass,
 337
 338             valid_out   => control_valid_out,
 339             stall_out   => control_stall_out,
 340             stopped_out => stopped_out,
 341
 342             gpr_bypass_a => gpr_a_bypass,
 343             gpr_bypass_b => gpr_b_bypass,
 344             gpr_bypass_c => gpr_c_bypass,
 345
 346             instr_tag_out => instr_tag
 347             );
 348
 349     deferred <= r.e.valid and busy_in;
 350
 351     decode2_0: process(clk)
 352     begin
 353         if rising_edge(clk) then
 354             if rst = '1' or flush_in = '1' or deferred = '0' then
 355                 if rin.e.valid = '1' then
 356                     report "execute " & to_hstring(rin.e.nia);
 357                 end if;
 358                 r <= rin;
 359             end if;
 360         end if;
 361     end process;
 362
 363     c_out.read <= d_in.decode.input_cr;
 364
 365     decode2_1: process(all)
 366         variable v : reg_type;
 367         variable mul_a : std_ulogic_vector(63 downto 0);
 368         variable mul_b : std_ulogic_vector(63 downto 0);
 369         variable decoded_reg_a : decode_input_reg_t;
 370         variable decoded_reg_b : decode_input_reg_t;
 371         variable decoded_reg_c : decode_input_reg_t;
 372         variable decoded_reg_o : decode_output_reg_t;
 373         variable length : std_ulogic_vector(3 downto 0);
 374         variable op : insn_type_t;
 375     begin
 376         v := r;
 377
 378         v.e := Decode2ToExecute1Init;
 379
 380         mul_a := (others => '0');
 381         mul_b := (others => '0');
 382
 383         --v.e.input_cr := d_in.decode.input_cr;
 384         v.e.output_cr := d_in.decode.output_cr;
 385
 386         -- Work out whether XER common bits are set
 387         v.e.output_xer := d_in.decode.output_carry;
 388         case d_in.decode.insn_type is
 389             when OP_ADD | OP_MUL_L64 | OP_DIV | OP_DIVE =>
 390                 -- OE field is valid in OP_ADD/OP_MUL_L64 with major opcode 31 only
 391                 if d_in.insn(31 downto 26) = "011111" and insn_oe(d_in.insn) = '1' then
 392                     v.e.oe := '1';
 393                     v.e.output_xer := '1';
 394                 end if;
 395             when OP_MTSPR =>
 396                 if decode_spr_num(d_in.insn) = SPR_XER then
 397                     v.e.output_xer := '1';
 398                 end if;
 399             when others =>
 400         end case;
 401
 402         decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data, d_in.ispr1,
 403                                              d_in.nia);
 404         decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data, d_in.ispr2);
 405         decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
 406         decoded_reg_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn, d_in.ispro);
 407
 408         if d_in.decode.lr = '1' then
 409             v.e.lr := insn_lk(d_in.insn);
 410             -- b and bc have even major opcodes; bcreg is considered absolute
 411             v.e.br_abs := insn_aa(d_in.insn) or d_in.insn(26);
 412         end if;
 413         op := d_in.decode.insn_type;
 414
 415         if d_in.decode.repeat /= NONE then
 416             v.e.repeat := '1';
 417             v.e.second := r.repeat;
 418             case d_in.decode.repeat is
 419                 when DRSE =>
 420                     -- do RS|1,RS for LE; RS,RS|1 for BE
 421                     if r.repeat = d_in.big_endian then
 422                         decoded_reg_c.reg(0) := '1';
 423                     end if;
 424                 when DRTE =>
 425                     -- do RT|1,RT for LE; RT,RT|1 for BE
 426                     if r.repeat = d_in.big_endian then
 427                         decoded_reg_o.reg(0) := '1';
 428                     end if;
 429                 when DUPD =>
 430                     -- update-form loads, 2nd instruction writes RA
 431                     if r.repeat = '1' then
 432                         decoded_reg_o.reg := decoded_reg_a.reg;
 433                     end if;
 434                 when others =>
 435             end case;
 436         elsif v.e.lr = '1' and decoded_reg_a.reg_valid = '1' then
 437             -- bcl/bclrl/bctarl that needs to write both CTR and LR has to be doubled
 438             v.e.repeat := '1';
 439             v.e.second := r.repeat;
 440             -- first one does CTR, second does LR
 441             decoded_reg_o.reg(0) := not r.repeat;
 442         end if;
 443
 444         r_out.read1_enable <= decoded_reg_a.reg_valid and d_in.valid;
 445         r_out.read1_reg    <= decoded_reg_a.reg;
 446         r_out.read2_enable <= decoded_reg_b.reg_valid and d_in.valid;
 447         r_out.read2_reg    <= decoded_reg_b.reg;
 448         r_out.read3_enable <= decoded_reg_c.reg_valid and d_in.valid;
 449         r_out.read3_reg    <= decoded_reg_c.reg;
 450
 451         case d_in.decode.length is
 452             when is1B =>
 453                 length := "0001";
 454             when is2B =>
 455                 length := "0010";
 456             when is4B =>
 457                 length := "0100";
 458             when is8B =>
 459                 length := "1000";
 460             when NONE =>
 461                 length := "0000";
 462         end case;
 463
 464         -- execute unit
 465         v.e.nia := d_in.nia;
 466         v.e.unit := d_in.decode.unit;
 467         v.e.fac := d_in.decode.facility;
 468         v.e.instr_tag := instr_tag;
 469         v.e.read_reg1 := decoded_reg_a.reg;
 470         v.e.read_reg2 := decoded_reg_b.reg;
 471         v.e.write_reg := decoded_reg_o.reg;
 472         v.e.write_reg_enable := decoded_reg_o.reg_valid;
 473         v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
 474         v.e.xerc := c_in.read_xerc_data;
 475         v.e.invert_a := d_in.decode.invert_a;
 476         v.e.addm1 := '0';
 477         v.e.insn_type := op;
 478         v.e.invert_out := d_in.decode.invert_out;
 479         v.e.input_carry := d_in.decode.input_carry;
 480         v.e.output_carry := d_in.decode.output_carry;
 481         v.e.is_32bit := d_in.decode.is_32bit;
 482         v.e.is_signed := d_in.decode.is_signed;
 483         v.e.insn := d_in.insn;
 484         v.e.data_len := length;
 485         v.e.byte_reverse := d_in.decode.byte_reverse;
 486         v.e.sign_extend := d_in.decode.sign_extend;
 487         v.e.update := d_in.decode.update;
 488         v.e.reserve := d_in.decode.reserve;
 489         v.e.br_pred := d_in.br_pred;
 490         v.e.result_sel := result_select(op);
 491         v.e.sub_select := subresult_select(op);
 492         if op = OP_BC or op = OP_BCREG then
 493             if d_in.insn(23) = '0' and r.repeat = '0' and
 494                 not (d_in.decode.insn_type = OP_BCREG and d_in.insn(10) = '0') then
 495                 -- decrement CTR if BO(2) = 0 and not bcctr
 496                 v.e.addm1 := '1';
 497                 v.e.result_sel := "000";        -- select adder output
 498             end if;
 499         end if;
 500
 501         -- See if any of the operands can get their value via the bypass path.
 502         case gpr_a_bypass is
 503             when '1' =>
 504                 v.e.read_data1 := execute_bypass.data;
 505             when others =>
 506                 v.e.read_data1 := decoded_reg_a.data;
 507         end case;
 508         case gpr_b_bypass is
 509             when '1' =>
 510                 v.e.read_data2 := execute_bypass.data;
 511             when others =>
 512                 v.e.read_data2 := decoded_reg_b.data;
 513         end case;
 514         case gpr_c_bypass is
 515             when '1' =>
 516                 v.e.read_data3 := execute_bypass.data;
 517             when others =>
 518                 v.e.read_data3 := decoded_reg_c.data;
 519         end case;
 520
 521         v.e.cr := c_in.read_cr_data;
 522         if cr_bypass = '1' then
 523             v.e.cr := execute_cr_bypass.data;
 524         end if;
 525
 526         -- issue control
 527         control_valid_in <= d_in.valid;
 528         control_sgl_pipe <= d_in.decode.sgl_pipe;
 529
 530         gpr_write_valid <= v.e.write_reg_enable;
 531         gpr_write <= decoded_reg_o.reg;
 532
 533         gpr_a_read_valid <= decoded_reg_a.reg_valid;
 534         gpr_a_read <= decoded_reg_a.reg;
 535
 536         gpr_b_read_valid <= decoded_reg_b.reg_valid;
 537         gpr_b_read <= decoded_reg_b.reg;
 538
 539         gpr_c_read_valid <= decoded_reg_c.reg_valid;
 540         gpr_c_read <= decoded_reg_c.reg;
 541
 542         cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
 543         -- Since ops that write CR only write some of the fields,
 544         -- any op that writes CR effectively also reads it.
 545         cr_read_valid <= cr_write_valid or d_in.decode.input_cr;
 546
 547         v.e.valid := control_valid_out;
 548         if control_valid_out = '1' then
 549             v.repeat := v.e.repeat and not r.repeat;
 550         end if;
 551
 552         stall_out <= control_stall_out or v.repeat;
 553
 554         if rst = '1' or flush_in = '1' then
 555             v.e := Decode2ToExecute1Init;
 556             v.repeat := '0';
 557         end if;
 558
 559         -- Update registers
 560         rin <= v;
 561
 562         -- Update outputs
 563         e_out <= r.e;
 564     end process;
 565
 566     d2_log: if LOG_LENGTH > 0 generate
 567         signal log_data : std_ulogic_vector(9 downto 0);
 568     begin
 569         dec2_log : process(clk)
 570         begin
 571             if rising_edge(clk) then
 572                 log_data <= r.e.nia(5 downto 2) &
 573                             r.e.valid &
 574                             stopped_out &
 575                             stall_out &
 576                             gpr_a_bypass &
 577                             gpr_b_bypass &
 578                             gpr_c_bypass;
 579             end if;
 580         end process;
 581         log_out <= log_data;
 582     end generate;
 583
 584 end architecture behaviour;