decode2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.insn_helpers.all;
  10
  11 entity decode2 is
  12     generic (
  13         EX1_BYPASS : boolean := true;
  14         HAS_FPU : boolean := true;
  15         -- Non-zero to enable log data collection
  16         LOG_LENGTH : natural := 0
  17         );
  18     port (
  19         clk   : in std_ulogic;
  20         rst   : in std_ulogic;
  21
  22         complete_in : in std_ulogic;
  23         busy_in   : in std_ulogic;
  24         stall_out : out std_ulogic;
  25
  26         stopped_out : out std_ulogic;
  27
  28         flush_in: in std_ulogic;
  29
  30         d_in  : in Decode1ToDecode2Type;
  31
  32         e_out : out Decode2ToExecute1Type;
  33
  34         r_in  : in RegisterFileToDecode2Type;
  35         r_out : out Decode2ToRegisterFileType;
  36
  37         c_in  : in CrFileToDecode2Type;
  38         c_out : out Decode2ToCrFileType;
  39
  40         log_out : out std_ulogic_vector(9 downto 0)
  41         );
  42 end entity decode2;
  43
  44 architecture behaviour of decode2 is
  45     type reg_type is record
  46         e : Decode2ToExecute1Type;
  47         repeat : std_ulogic;
  48     end record;
  49
  50     signal r, rin : reg_type;
  51
  52     signal deferred : std_ulogic;
  53
  54     type decode_input_reg_t is record
  55         reg_valid : std_ulogic;
  56         reg       : gspr_index_t;
  57         data      : std_ulogic_vector(63 downto 0);
  58     end record;
  59
  60     type decode_output_reg_t is record
  61         reg_valid : std_ulogic;
  62         reg       : gspr_index_t;
  63     end record;
  64
  65     function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
  66                                  reg_data : std_ulogic_vector(63 downto 0);
  67                                  ispr : gspr_index_t;
  68                                  instr_addr : std_ulogic_vector(63 downto 0))
  69         return decode_input_reg_t is
  70     begin
  71         if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
  72             return ('1', gpr_to_gspr(insn_ra(insn_in)), reg_data);
  73         elsif t = SPR then
  74             -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
  75             -- If it's all 0, we don't treat it as a dependency as slow SPRs
  76             -- operations are single issue.
  77             --
  78             assert is_fast_spr(ispr) =  '1' or ispr = "0000000"
  79                 report "Decode A says SPR but ISPR is invalid:" &
  80                 to_hstring(ispr) severity failure;
  81             return (is_fast_spr(ispr), ispr, reg_data);
  82         elsif t = CIA then
  83             return ('0', (others => '0'), instr_addr);
  84         elsif HAS_FPU and t = FRA then
  85             return ('1', fpr_to_gspr(insn_fra(insn_in)), reg_data);
  86         else
  87             return ('0', (others => '0'), (others => '0'));
  88         end if;
  89     end;
  90
  91     function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
  92                                  reg_data : std_ulogic_vector(63 downto 0);
  93                                  ispr : gspr_index_t) return decode_input_reg_t is
  94         variable ret : decode_input_reg_t;
  95     begin
  96         case t is
  97             when RB =>
  98                 ret := ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
  99             when FRB =>
 100                 if HAS_FPU then
 101                     ret := ('1', fpr_to_gspr(insn_frb(insn_in)), reg_data);
 102                 else
 103                     ret := ('0', (others => '0'), (others => '0'));
 104                 end if;
 105             when CONST_UI =>
 106                 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
 107             when CONST_SI =>
 108                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
 109             when CONST_SI_HI =>
 110                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
 111             when CONST_UI_HI =>
 112                 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
 113             when CONST_LI =>
 114                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
 115             when CONST_BD =>
 116                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
 117             when CONST_DS =>
 118                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
 119             when CONST_DQ =>
 120                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dq(insn_in)) & "0000", 64)));
 121             when CONST_DXHI4 =>
 122                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dx(insn_in)) & x"0004", 64)));
 123             when CONST_M1 =>
 124                 ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
 125             when CONST_SH =>
 126                 ret := ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
 127             when CONST_SH32 =>
 128                 ret := ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
 129             when SPR =>
 130                 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 131                 -- If it's all 0, we don't treat it as a dependency as slow SPRs
 132                 -- operations are single issue.
 133                 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
 134                     report "Decode B says SPR but ISPR is invalid:" &
 135                     to_hstring(ispr) severity failure;
 136                 ret := (is_fast_spr(ispr), ispr, reg_data);
 137             when NONE =>
 138                 ret := ('0', (others => '0'), (others => '0'));
 139         end case;
 140
 141         return ret;
 142     end;
 143
 144     function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
 145                                  reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
 146     begin
 147         case t is
 148             when RS =>
 149                 return ('1', gpr_to_gspr(insn_rs(insn_in)), reg_data);
 150             when RCR =>
 151                 return ('1', gpr_to_gspr(insn_rcreg(insn_in)), reg_data);
 152             when FRS =>
 153                 if HAS_FPU then
 154                     return ('1', fpr_to_gspr(insn_frt(insn_in)), reg_data);
 155                 else
 156                     return ('0', (others => '0'), (others => '0'));
 157                 end if;
 158             when FRC =>
 159                 if HAS_FPU then
 160                     return ('1', fpr_to_gspr(insn_frc(insn_in)), reg_data);
 161                 else
 162                     return ('0', (others => '0'), (others => '0'));
 163                 end if;
 164             when NONE =>
 165                 return ('0', (others => '0'), (others => '0'));
 166         end case;
 167     end;
 168
 169     function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
 170                                 ispr : gspr_index_t) return decode_output_reg_t is
 171     begin
 172         case t is
 173             when RT =>
 174                 return ('1', gpr_to_gspr(insn_rt(insn_in)));
 175             when RA =>
 176                 return ('1', gpr_to_gspr(insn_ra(insn_in)));
 177             when FRT =>
 178                 if HAS_FPU then
 179                     return ('1', fpr_to_gspr(insn_frt(insn_in)));
 180                 else
 181                     return ('0', "0000000");
 182                 end if;
 183             when SPR =>
 184                 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 185                 -- If it's all 0, we don't treat it as a dependency as slow SPRs
 186                 -- operations are single issue.
 187                 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
 188                     report "Decode B says SPR but ISPR is invalid:" &
 189                     to_hstring(ispr) severity failure;
 190                 return (is_fast_spr(ispr), ispr);
 191             when NONE =>
 192                 return ('0', "0000000");
 193         end case;
 194     end;
 195
 196     function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 197     begin
 198         case t is
 199             when RC =>
 200                 return insn_rc(insn_in);
 201             when ONE =>
 202                 return '1';
 203             when NONE =>
 204                 return '0';
 205         end case;
 206     end;
 207
 208     -- For now, use "rc" in the decode table to decide whether oe exists.
 209     -- This is not entirely correct architecturally: For mulhd and
 210     -- mulhdu, the OE field is reserved. It remains to be seen what an
 211     -- actual POWER9 does if we set it on those instructions, for now we
 212     -- test that further down when assigning to the multiplier oe input.
 213     --
 214     function decode_oe (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 215     begin
 216         case t is
 217             when RC =>
 218                 return insn_oe(insn_in);
 219             when OTHERS =>
 220                 return '0';
 221         end case;
 222     end;
 223
 224     -- issue control signals
 225     signal control_valid_in : std_ulogic;
 226     signal control_valid_out : std_ulogic;
 227     signal control_stall_out : std_ulogic;
 228     signal control_sgl_pipe : std_logic;
 229
 230     signal gpr_write_valid : std_ulogic;
 231     signal gpr_write : gspr_index_t;
 232     signal gpr_bypassable  : std_ulogic;
 233
 234     signal update_gpr_write_valid : std_ulogic;
 235     signal update_gpr_write_reg : gspr_index_t;
 236
 237     signal gpr_a_read_valid : std_ulogic;
 238     signal gpr_a_read :gspr_index_t;
 239     signal gpr_a_bypass : std_ulogic;
 240
 241     signal gpr_b_read_valid : std_ulogic;
 242     signal gpr_b_read : gspr_index_t;
 243     signal gpr_b_bypass : std_ulogic;
 244
 245     signal gpr_c_read_valid : std_ulogic;
 246     signal gpr_c_read : gspr_index_t;
 247     signal gpr_c_bypass : std_ulogic;
 248
 249     signal cr_write_valid  : std_ulogic;
 250     signal cr_bypass       : std_ulogic;
 251     signal cr_bypass_avail : std_ulogic;
 252
 253 begin
 254     control_0: entity work.control
 255         generic map (
 256             PIPELINE_DEPTH => 1
 257             )
 258         port map (
 259             clk         => clk,
 260             rst         => rst,
 261
 262             complete_in => complete_in,
 263             valid_in    => control_valid_in,
 264             repeated    => r.repeat,
 265             busy_in     => busy_in,
 266             deferred    => deferred,
 267             flush_in    => flush_in,
 268             sgl_pipe_in => control_sgl_pipe,
 269             stop_mark_in => d_in.stop_mark,
 270
 271             gpr_write_valid_in => gpr_write_valid,
 272             gpr_write_in       => gpr_write,
 273             gpr_bypassable     => gpr_bypassable,
 274
 275             update_gpr_write_valid => update_gpr_write_valid,
 276             update_gpr_write_reg => update_gpr_write_reg,
 277
 278             gpr_a_read_valid_in  => gpr_a_read_valid,
 279             gpr_a_read_in        => gpr_a_read,
 280
 281             gpr_b_read_valid_in  => gpr_b_read_valid,
 282             gpr_b_read_in        => gpr_b_read,
 283
 284             gpr_c_read_valid_in  => gpr_c_read_valid,
 285             gpr_c_read_in        => gpr_c_read,
 286
 287             cr_read_in           => d_in.decode.input_cr,
 288             cr_write_in          => cr_write_valid,
 289             cr_bypass            => cr_bypass,
 290             cr_bypassable        => cr_bypass_avail,
 291
 292             valid_out   => control_valid_out,
 293             stall_out   => control_stall_out,
 294             stopped_out => stopped_out,
 295
 296             gpr_bypass_a => gpr_a_bypass,
 297             gpr_bypass_b => gpr_b_bypass,
 298             gpr_bypass_c => gpr_c_bypass
 299             );
 300
 301     deferred <= r.e.valid and busy_in;
 302
 303     decode2_0: process(clk)
 304     begin
 305         if rising_edge(clk) then
 306             if rst = '1' or flush_in = '1' or deferred = '0' then
 307                 if rin.e.valid = '1' then
 308                     report "execute " & to_hstring(rin.e.nia);
 309                 end if;
 310                 r <= rin;
 311             end if;
 312         end if;
 313     end process;
 314
 315     c_out.read <= d_in.decode.input_cr;
 316
 317     decode2_1: process(all)
 318         variable v : reg_type;
 319         variable mul_a : std_ulogic_vector(63 downto 0);
 320         variable mul_b : std_ulogic_vector(63 downto 0);
 321         variable decoded_reg_a : decode_input_reg_t;
 322         variable decoded_reg_b : decode_input_reg_t;
 323         variable decoded_reg_c : decode_input_reg_t;
 324         variable decoded_reg_o : decode_output_reg_t;
 325         variable length : std_ulogic_vector(3 downto 0);
 326     begin
 327         v := r;
 328
 329         v.e := Decode2ToExecute1Init;
 330
 331         mul_a := (others => '0');
 332         mul_b := (others => '0');
 333
 334         --v.e.input_cr := d_in.decode.input_cr;
 335         v.e.output_cr := d_in.decode.output_cr;
 336
 337         decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data, d_in.ispr1,
 338                                              d_in.nia);
 339         decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data, d_in.ispr2);
 340         decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
 341         decoded_reg_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn, d_in.ispr1);
 342
 343         if d_in.decode.repeat /= NONE then
 344             v.e.repeat := '1';
 345             v.e.second := r.repeat;
 346             case d_in.decode.repeat is
 347                 when DRSE =>
 348                     -- do RS|1,RS for LE; RS,RS|1 for BE
 349                     if r.repeat = d_in.big_endian then
 350                         decoded_reg_c.reg(0) := '1';
 351                     end if;
 352                 when DRTE =>
 353                     -- do RT|1,RT for LE; RT,RT|1 for BE
 354                     if r.repeat = d_in.big_endian then
 355                         decoded_reg_o.reg(0) := '1';
 356                     end if;
 357                 when others =>
 358             end case;
 359         end if;
 360
 361         r_out.read1_enable <= decoded_reg_a.reg_valid and d_in.valid;
 362         r_out.read1_reg    <= decoded_reg_a.reg;
 363         r_out.read2_enable <= decoded_reg_b.reg_valid and d_in.valid;
 364         r_out.read2_reg    <= decoded_reg_b.reg;
 365         r_out.read3_enable <= decoded_reg_c.reg_valid and d_in.valid;
 366         r_out.read3_reg    <= decoded_reg_c.reg;
 367
 368         case d_in.decode.length is
 369             when is1B =>
 370                 length := "0001";
 371             when is2B =>
 372                 length := "0010";
 373             when is4B =>
 374                 length := "0100";
 375             when is8B =>
 376                 length := "1000";
 377             when NONE =>
 378                 length := "0000";
 379         end case;
 380
 381         -- execute unit
 382         v.e.nia := d_in.nia;
 383         v.e.unit := d_in.decode.unit;
 384         v.e.fac := d_in.decode.facility;
 385         v.e.insn_type := d_in.decode.insn_type;
 386         v.e.read_reg1 := decoded_reg_a.reg;
 387         v.e.read_data1 := decoded_reg_a.data;
 388         v.e.bypass_data1 := gpr_a_bypass;
 389         v.e.read_reg2 := decoded_reg_b.reg;
 390         v.e.read_data2 := decoded_reg_b.data;
 391         v.e.bypass_data2 := gpr_b_bypass;
 392         v.e.read_data3 := decoded_reg_c.data;
 393         v.e.bypass_data3 := gpr_c_bypass;
 394         v.e.write_reg := decoded_reg_o.reg;
 395         v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
 396         if not (d_in.decode.insn_type = OP_MUL_H32 or d_in.decode.insn_type = OP_MUL_H64) then
 397             v.e.oe := decode_oe(d_in.decode.rc, d_in.insn);
 398         end if;
 399         v.e.cr := c_in.read_cr_data;
 400         v.e.bypass_cr := cr_bypass;
 401         v.e.xerc := c_in.read_xerc_data;
 402         v.e.invert_a := d_in.decode.invert_a;
 403         v.e.invert_out := d_in.decode.invert_out;
 404         v.e.input_carry := d_in.decode.input_carry;
 405         v.e.output_carry := d_in.decode.output_carry;
 406         v.e.is_32bit := d_in.decode.is_32bit;
 407         v.e.is_signed := d_in.decode.is_signed;
 408         if d_in.decode.lr = '1' then
 409             v.e.lr := insn_lk(d_in.insn);
 410         end if;
 411         v.e.insn := d_in.insn;
 412         v.e.data_len := length;
 413         v.e.byte_reverse := d_in.decode.byte_reverse;
 414         v.e.sign_extend := d_in.decode.sign_extend;
 415         v.e.update := d_in.decode.update;
 416         v.e.reserve := d_in.decode.reserve;
 417         v.e.br_pred := d_in.br_pred;
 418
 419         -- issue control
 420         control_valid_in <= d_in.valid;
 421         control_sgl_pipe <= d_in.decode.sgl_pipe;
 422
 423         gpr_write_valid <= decoded_reg_o.reg_valid;
 424         gpr_write <= decoded_reg_o.reg;
 425         gpr_bypassable <= '0';
 426         if EX1_BYPASS and d_in.decode.unit = ALU then
 427             gpr_bypassable <= '1';
 428         end if;
 429         update_gpr_write_valid <= d_in.decode.update;
 430         update_gpr_write_reg <= decoded_reg_a.reg;
 431         if v.e.lr = '1' then
 432             -- there are no instructions that have both update=1 and lr=1
 433             update_gpr_write_valid <= '1';
 434             update_gpr_write_reg <= fast_spr_num(SPR_LR);
 435         end if;
 436
 437         gpr_a_read_valid <= decoded_reg_a.reg_valid;
 438         gpr_a_read <= decoded_reg_a.reg;
 439
 440         gpr_b_read_valid <= decoded_reg_b.reg_valid;
 441         gpr_b_read <= decoded_reg_b.reg;
 442
 443         gpr_c_read_valid <= decoded_reg_c.reg_valid;
 444         gpr_c_read <= decoded_reg_c.reg;
 445
 446         cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
 447         cr_bypass_avail <= '0';
 448         if EX1_BYPASS and d_in.decode.unit = ALU then
 449             cr_bypass_avail <= d_in.decode.output_cr;
 450         end if;
 451
 452         v.e.valid := control_valid_out;
 453         if control_valid_out = '1' then
 454             v.repeat := v.e.repeat and not r.repeat;
 455         end if;
 456
 457         stall_out <= control_stall_out or v.repeat;
 458
 459         if rst = '1' or flush_in = '1' then
 460             v.e := Decode2ToExecute1Init;
 461             v.repeat := '0';
 462         end if;
 463
 464         -- Update registers
 465         rin <= v;
 466
 467         -- Update outputs
 468         e_out <= r.e;
 469     end process;
 470
 471     d2_log: if LOG_LENGTH > 0 generate
 472         signal log_data : std_ulogic_vector(9 downto 0);
 473     begin
 474         dec2_log : process(clk)
 475         begin
 476             if rising_edge(clk) then
 477                 log_data <= r.e.nia(5 downto 2) &
 478                             r.e.valid &
 479                             stopped_out &
 480                             stall_out &
 481                             r.e.bypass_data3 &
 482                             r.e.bypass_data2 &
 483                             r.e.bypass_data1;
 484             end if;
 485         end process;
 486         log_out <= log_data;
 487     end generate;
 488
 489 end architecture behaviour;