decode2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.insn_helpers.all;
  10
  11 entity decode2 is
  12     generic (
  13         EX1_BYPASS : boolean := true;
  14         HAS_FPU : boolean := true;
  15         -- Non-zero to enable log data collection
  16         LOG_LENGTH : natural := 0
  17         );
  18     port (
  19         clk   : in std_ulogic;
  20         rst   : in std_ulogic;
  21
  22         complete_in : in std_ulogic;
  23         busy_in   : in std_ulogic;
  24         stall_out : out std_ulogic;
  25
  26         stopped_out : out std_ulogic;
  27
  28         flush_in: in std_ulogic;
  29
  30         d_in  : in Decode1ToDecode2Type;
  31
  32         e_out : out Decode2ToExecute1Type;
  33
  34         r_in  : in RegisterFileToDecode2Type;
  35         r_out : out Decode2ToRegisterFileType;
  36
  37         c_in  : in CrFileToDecode2Type;
  38         c_out : out Decode2ToCrFileType;
  39
  40         log_out : out std_ulogic_vector(9 downto 0)
  41         );
  42 end entity decode2;
  43
  44 architecture behaviour of decode2 is
  45     type reg_type is record
  46         e : Decode2ToExecute1Type;
  47     end record;
  48
  49     signal r, rin : reg_type;
  50
  51     signal deferred : std_ulogic;
  52
  53     type decode_input_reg_t is record
  54         reg_valid : std_ulogic;
  55         reg       : gspr_index_t;
  56         data      : std_ulogic_vector(63 downto 0);
  57     end record;
  58
  59     type decode_output_reg_t is record
  60         reg_valid : std_ulogic;
  61         reg       : gspr_index_t;
  62     end record;
  63
  64     function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
  65                                  reg_data : std_ulogic_vector(63 downto 0);
  66                                  ispr : gspr_index_t;
  67                                  instr_addr : std_ulogic_vector(63 downto 0))
  68         return decode_input_reg_t is
  69     begin
  70         if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
  71             return ('1', gpr_to_gspr(insn_ra(insn_in)), reg_data);
  72         elsif t = SPR then
  73             -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
  74             -- If it's all 0, we don't treat it as a dependency as slow SPRs
  75             -- operations are single issue.
  76             --
  77             assert is_fast_spr(ispr) =  '1' or ispr = "0000000"
  78                 report "Decode A says SPR but ISPR is invalid:" &
  79                 to_hstring(ispr) severity failure;
  80             return (is_fast_spr(ispr), ispr, reg_data);
  81         elsif t = CIA then
  82             return ('0', (others => '0'), instr_addr);
  83         elsif HAS_FPU and t = FRA then
  84             return ('1', fpr_to_gspr(insn_fra(insn_in)), reg_data);
  85         else
  86             return ('0', (others => '0'), (others => '0'));
  87         end if;
  88     end;
  89
  90     function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
  91                                  reg_data : std_ulogic_vector(63 downto 0);
  92                                  ispr : gspr_index_t) return decode_input_reg_t is
  93         variable ret : decode_input_reg_t;
  94     begin
  95         case t is
  96             when RB =>
  97                 ret := ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
  98             when FRB =>
  99                 if HAS_FPU then
 100                     ret := ('1', fpr_to_gspr(insn_frb(insn_in)), reg_data);
 101                 else
 102                     ret := ('0', (others => '0'), (others => '0'));
 103                 end if;
 104             when CONST_UI =>
 105                 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
 106             when CONST_SI =>
 107                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
 108             when CONST_SI_HI =>
 109                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
 110             when CONST_UI_HI =>
 111                 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
 112             when CONST_LI =>
 113                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
 114             when CONST_BD =>
 115                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
 116             when CONST_DS =>
 117                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
 118             when CONST_DXHI4 =>
 119                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dx(insn_in)) & x"0004", 64)));
 120             when CONST_M1 =>
 121                 ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
 122             when CONST_SH =>
 123                 ret := ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
 124             when CONST_SH32 =>
 125                 ret := ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
 126             when SPR =>
 127                 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 128                 -- If it's all 0, we don't treat it as a dependency as slow SPRs
 129                 -- operations are single issue.
 130                 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
 131                     report "Decode B says SPR but ISPR is invalid:" &
 132                     to_hstring(ispr) severity failure;
 133                 ret := (is_fast_spr(ispr), ispr, reg_data);
 134             when NONE =>
 135                 ret := ('0', (others => '0'), (others => '0'));
 136         end case;
 137
 138         return ret;
 139     end;
 140
 141     function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
 142                                  reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
 143     begin
 144         case t is
 145             when RS =>
 146                 return ('1', gpr_to_gspr(insn_rs(insn_in)), reg_data);
 147             when RCR =>
 148                 return ('1', gpr_to_gspr(insn_rcreg(insn_in)), reg_data);
 149             when FRS =>
 150                 if HAS_FPU then
 151                     return ('1', fpr_to_gspr(insn_frt(insn_in)), reg_data);
 152                 else
 153                     return ('0', (others => '0'), (others => '0'));
 154                 end if;
 155             when FRC =>
 156                 if HAS_FPU then
 157                     return ('1', fpr_to_gspr(insn_frc(insn_in)), reg_data);
 158                 else
 159                     return ('0', (others => '0'), (others => '0'));
 160                 end if;
 161             when NONE =>
 162                 return ('0', (others => '0'), (others => '0'));
 163         end case;
 164     end;
 165
 166     function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
 167                                 ispr : gspr_index_t) return decode_output_reg_t is
 168     begin
 169         case t is
 170             when RT =>
 171                 return ('1', gpr_to_gspr(insn_rt(insn_in)));
 172             when RA =>
 173                 return ('1', gpr_to_gspr(insn_ra(insn_in)));
 174             when FRT =>
 175                 if HAS_FPU then
 176                     return ('1', fpr_to_gspr(insn_frt(insn_in)));
 177                 else
 178                     return ('0', "0000000");
 179                 end if;
 180             when SPR =>
 181                 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 182                 -- If it's all 0, we don't treat it as a dependency as slow SPRs
 183                 -- operations are single issue.
 184                 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
 185                     report "Decode B says SPR but ISPR is invalid:" &
 186                     to_hstring(ispr) severity failure;
 187                 return (is_fast_spr(ispr), ispr);
 188             when NONE =>
 189                 return ('0', "0000000");
 190         end case;
 191     end;
 192
 193     function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 194     begin
 195         case t is
 196             when RC =>
 197                 return insn_rc(insn_in);
 198             when ONE =>
 199                 return '1';
 200             when NONE =>
 201                 return '0';
 202         end case;
 203     end;
 204
 205     -- For now, use "rc" in the decode table to decide whether oe exists.
 206     -- This is not entirely correct architecturally: For mulhd and
 207     -- mulhdu, the OE field is reserved. It remains to be seen what an
 208     -- actual POWER9 does if we set it on those instructions, for now we
 209     -- test that further down when assigning to the multiplier oe input.
 210     --
 211     function decode_oe (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 212     begin
 213         case t is
 214             when RC =>
 215                 return insn_oe(insn_in);
 216             when OTHERS =>
 217                 return '0';
 218         end case;
 219     end;
 220
 221     -- issue control signals
 222     signal control_valid_in : std_ulogic;
 223     signal control_valid_out : std_ulogic;
 224     signal control_sgl_pipe : std_logic;
 225
 226     signal gpr_write_valid : std_ulogic;
 227     signal gpr_write : gspr_index_t;
 228     signal gpr_bypassable  : std_ulogic;
 229
 230     signal update_gpr_write_valid : std_ulogic;
 231     signal update_gpr_write_reg : gspr_index_t;
 232
 233     signal gpr_a_read_valid : std_ulogic;
 234     signal gpr_a_read :gspr_index_t;
 235     signal gpr_a_bypass : std_ulogic;
 236
 237     signal gpr_b_read_valid : std_ulogic;
 238     signal gpr_b_read : gspr_index_t;
 239     signal gpr_b_bypass : std_ulogic;
 240
 241     signal gpr_c_read_valid : std_ulogic;
 242     signal gpr_c_read : gspr_index_t;
 243     signal gpr_c_bypass : std_ulogic;
 244
 245     signal cr_write_valid  : std_ulogic;
 246     signal cr_bypass       : std_ulogic;
 247     signal cr_bypass_avail : std_ulogic;
 248
 249 begin
 250     control_0: entity work.control
 251         generic map (
 252             PIPELINE_DEPTH => 1
 253             )
 254         port map (
 255             clk         => clk,
 256             rst         => rst,
 257
 258             complete_in => complete_in,
 259             valid_in    => control_valid_in,
 260             busy_in     => busy_in,
 261             deferred    => deferred,
 262             flush_in    => flush_in,
 263             sgl_pipe_in => control_sgl_pipe,
 264             stop_mark_in => d_in.stop_mark,
 265
 266             gpr_write_valid_in => gpr_write_valid,
 267             gpr_write_in       => gpr_write,
 268             gpr_bypassable     => gpr_bypassable,
 269
 270             update_gpr_write_valid => update_gpr_write_valid,
 271             update_gpr_write_reg => update_gpr_write_reg,
 272
 273             gpr_a_read_valid_in  => gpr_a_read_valid,
 274             gpr_a_read_in        => gpr_a_read,
 275
 276             gpr_b_read_valid_in  => gpr_b_read_valid,
 277             gpr_b_read_in        => gpr_b_read,
 278
 279             gpr_c_read_valid_in  => gpr_c_read_valid,
 280             gpr_c_read_in        => gpr_c_read,
 281
 282             cr_read_in           => d_in.decode.input_cr,
 283             cr_write_in          => cr_write_valid,
 284             cr_bypass            => cr_bypass,
 285             cr_bypassable        => cr_bypass_avail,
 286
 287             valid_out   => control_valid_out,
 288             stall_out   => stall_out,
 289             stopped_out => stopped_out,
 290
 291             gpr_bypass_a => gpr_a_bypass,
 292             gpr_bypass_b => gpr_b_bypass,
 293             gpr_bypass_c => gpr_c_bypass
 294             );
 295
 296     deferred <= r.e.valid and busy_in;
 297
 298     decode2_0: process(clk)
 299     begin
 300         if rising_edge(clk) then
 301             if rst = '1' or flush_in = '1' or deferred = '0' then
 302                 if rin.e.valid = '1' then
 303                     report "execute " & to_hstring(rin.e.nia);
 304                 end if;
 305                 r <= rin;
 306             end if;
 307         end if;
 308     end process;
 309
 310     r_out.read1_reg <= d_in.ispr1 when d_in.decode.input_reg_a = SPR
 311                        else fpr_to_gspr(insn_fra(d_in.insn)) when d_in.decode.input_reg_a = FRA and HAS_FPU
 312                        else gpr_to_gspr(insn_ra(d_in.insn));
 313     r_out.read2_reg <= d_in.ispr2 when d_in.decode.input_reg_b = SPR
 314                        else fpr_to_gspr(insn_frb(d_in.insn)) when d_in.decode.input_reg_b = FRB and HAS_FPU
 315                        else gpr_to_gspr(insn_rb(d_in.insn));
 316     r_out.read3_reg <= gpr_to_gspr(insn_rcreg(d_in.insn)) when d_in.decode.input_reg_c = RCR
 317                        else fpr_to_gspr(insn_frc(d_in.insn)) when d_in.decode.input_reg_c = FRC and HAS_FPU
 318                        else fpr_to_gspr(insn_frt(d_in.insn)) when d_in.decode.input_reg_c = FRS and HAS_FPU
 319                        else gpr_to_gspr(insn_rs(d_in.insn));
 320
 321     c_out.read <= d_in.decode.input_cr;
 322
 323     decode2_1: process(all)
 324         variable v : reg_type;
 325         variable mul_a : std_ulogic_vector(63 downto 0);
 326         variable mul_b : std_ulogic_vector(63 downto 0);
 327         variable decoded_reg_a : decode_input_reg_t;
 328         variable decoded_reg_b : decode_input_reg_t;
 329         variable decoded_reg_c : decode_input_reg_t;
 330         variable decoded_reg_o : decode_output_reg_t;
 331         variable length : std_ulogic_vector(3 downto 0);
 332     begin
 333         v := r;
 334
 335         v.e := Decode2ToExecute1Init;
 336
 337         mul_a := (others => '0');
 338         mul_b := (others => '0');
 339
 340         --v.e.input_cr := d_in.decode.input_cr;
 341         v.e.output_cr := d_in.decode.output_cr;
 342
 343         decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data, d_in.ispr1,
 344                                              d_in.nia);
 345         decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data, d_in.ispr2);
 346         decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
 347         decoded_reg_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn, d_in.ispr1);
 348
 349         r_out.read1_enable <= decoded_reg_a.reg_valid and d_in.valid;
 350         r_out.read2_enable <= decoded_reg_b.reg_valid and d_in.valid;
 351         r_out.read3_enable <= decoded_reg_c.reg_valid and d_in.valid;
 352
 353         case d_in.decode.length is
 354             when is1B =>
 355                 length := "0001";
 356             when is2B =>
 357                 length := "0010";
 358             when is4B =>
 359                 length := "0100";
 360             when is8B =>
 361                 length := "1000";
 362             when NONE =>
 363                 length := "0000";
 364         end case;
 365
 366         -- execute unit
 367         v.e.nia := d_in.nia;
 368         v.e.unit := d_in.decode.unit;
 369         v.e.insn_type := d_in.decode.insn_type;
 370         v.e.read_reg1 := decoded_reg_a.reg;
 371         v.e.read_data1 := decoded_reg_a.data;
 372         v.e.bypass_data1 := gpr_a_bypass;
 373         v.e.read_reg2 := decoded_reg_b.reg;
 374         v.e.read_data2 := decoded_reg_b.data;
 375         v.e.bypass_data2 := gpr_b_bypass;
 376         v.e.read_data3 := decoded_reg_c.data;
 377         v.e.bypass_data3 := gpr_c_bypass;
 378         v.e.write_reg := decoded_reg_o.reg;
 379         v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
 380         if not (d_in.decode.insn_type = OP_MUL_H32 or d_in.decode.insn_type = OP_MUL_H64) then
 381             v.e.oe := decode_oe(d_in.decode.rc, d_in.insn);
 382         end if;
 383         v.e.cr := c_in.read_cr_data;
 384         v.e.bypass_cr := cr_bypass;
 385         v.e.xerc := c_in.read_xerc_data;
 386         v.e.invert_a := d_in.decode.invert_a;
 387         v.e.invert_out := d_in.decode.invert_out;
 388         v.e.input_carry := d_in.decode.input_carry;
 389         v.e.output_carry := d_in.decode.output_carry;
 390         v.e.is_32bit := d_in.decode.is_32bit;
 391         v.e.is_signed := d_in.decode.is_signed;
 392         if d_in.decode.lr = '1' then
 393             v.e.lr := insn_lk(d_in.insn);
 394         end if;
 395         v.e.insn := d_in.insn;
 396         v.e.data_len := length;
 397         v.e.byte_reverse := d_in.decode.byte_reverse;
 398         v.e.sign_extend := d_in.decode.sign_extend;
 399         v.e.update := d_in.decode.update;
 400         v.e.reserve := d_in.decode.reserve;
 401         v.e.br_pred := d_in.br_pred;
 402
 403         -- issue control
 404         control_valid_in <= d_in.valid;
 405         control_sgl_pipe <= d_in.decode.sgl_pipe;
 406
 407         gpr_write_valid <= decoded_reg_o.reg_valid;
 408         gpr_write <= decoded_reg_o.reg;
 409         gpr_bypassable <= '0';
 410         if EX1_BYPASS and d_in.decode.unit = ALU then
 411             gpr_bypassable <= '1';
 412         end if;
 413         update_gpr_write_valid <= d_in.decode.update;
 414         update_gpr_write_reg <= decoded_reg_a.reg;
 415         if v.e.lr = '1' then
 416             -- there are no instructions that have both update=1 and lr=1
 417             update_gpr_write_valid <= '1';
 418             update_gpr_write_reg <= fast_spr_num(SPR_LR);
 419         end if;
 420
 421         gpr_a_read_valid <= decoded_reg_a.reg_valid;
 422         gpr_a_read <= decoded_reg_a.reg;
 423
 424         gpr_b_read_valid <= decoded_reg_b.reg_valid;
 425         gpr_b_read <= decoded_reg_b.reg;
 426
 427         gpr_c_read_valid <= decoded_reg_c.reg_valid;
 428         gpr_c_read <= decoded_reg_c.reg;
 429
 430         cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
 431         cr_bypass_avail <= '0';
 432         if EX1_BYPASS and d_in.decode.unit = ALU then
 433             cr_bypass_avail <= d_in.decode.output_cr;
 434         end if;
 435
 436         v.e.valid := control_valid_out;
 437
 438         if rst = '1' or flush_in = '1' then
 439             v.e := Decode2ToExecute1Init;
 440         end if;
 441
 442         -- Update registers
 443         rin <= v;
 444
 445         -- Update outputs
 446         e_out <= r.e;
 447     end process;
 448
 449     d2_log: if LOG_LENGTH > 0 generate
 450         signal log_data : std_ulogic_vector(9 downto 0);
 451     begin
 452         dec2_log : process(clk)
 453         begin
 454             if rising_edge(clk) then
 455                 log_data <= r.e.nia(5 downto 2) &
 456                             r.e.valid &
 457                             stopped_out &
 458                             stall_out &
 459                             r.e.bypass_data3 &
 460                             r.e.bypass_data2 &
 461                             r.e.bypass_data1;
 462             end if;
 463         end process;
 464         log_out <= log_data;
 465     end generate;
 466
 467 end architecture behaviour;