Make wishbone_master_out and wb_io_master_out match
[microwatt.git] / decode_types.vhdl
1 library ieee;
2 use ieee.std_logic_1164.all;
3
4 package decode_types is
5 type insn_type_t is (OP_ILLEGAL, OP_NOP, OP_ADD,
6 OP_AND, OP_ATTN, OP_B, OP_BC, OP_BCREG,
7 OP_BPERM, OP_CMP, OP_CMPB, OP_CMPEQB, OP_CMPRB,
8 OP_CNTZ, OP_CROP,
9 OP_DARN, OP_DCBF, OP_DCBST, OP_DCBT, OP_DCBTST,
10 OP_DCBZ, OP_DIV, OP_DIVE, OP_EXTS, OP_EXTSWSLI,
11 OP_FPOP, OP_FPOP_I,
12 OP_ICBI, OP_ICBT, OP_ISEL, OP_ISYNC,
13 OP_LOAD, OP_STORE,
14 OP_FPLOAD, OP_FPSTORE,
15 OP_MCRXRX, OP_MFCR, OP_MFMSR, OP_MFSPR, OP_MOD,
16 OP_MTCRF, OP_MTMSRD, OP_MTSPR, OP_MUL_L64,
17 OP_MUL_H64, OP_MUL_H32, OP_OR,
18 OP_POPCNT, OP_PRTY, OP_RFID,
19 OP_RLC, OP_RLCL, OP_RLCR, OP_SC, OP_SETB,
20 OP_SHL, OP_SHR,
21 OP_SYNC, OP_TLBIE, OP_TRAP,
22 OP_XOR,
23 OP_BCD, OP_ADDG6S,
24 OP_FETCH_FAILED
25 );
26 type input_reg_a_t is (NONE, RA, RA_OR_ZERO, SPR, CIA, FRA);
27 type input_reg_b_t is (NONE, RB, CONST_UI, CONST_SI, CONST_SI_HI, CONST_UI_HI, CONST_LI, CONST_BD,
28 CONST_DXHI4, CONST_DS, CONST_M1, CONST_SH, CONST_SH32, SPR, FRB);
29 type input_reg_c_t is (NONE, RS, RCR, FRC, FRS);
30 type output_reg_a_t is (NONE, RT, RA, SPR, FRT);
31 type rc_t is (NONE, ONE, RC);
32 type carry_in_t is (ZERO, CA, OV, ONE);
33
34 constant SH_OFFSET : integer := 0;
35 constant MB_OFFSET : integer := 1;
36 constant ME_OFFSET : integer := 1;
37 constant SH32_OFFSET : integer := 0;
38 constant MB32_OFFSET : integer := 1;
39 constant ME32_OFFSET : integer := 2;
40
41 constant FXM_OFFSET : integer := 0;
42
43 constant BO_OFFSET : integer := 0;
44 constant BI_OFFSET : integer := 1;
45 constant BH_OFFSET : integer := 2;
46
47 constant BF_OFFSET : integer := 0;
48 constant L_OFFSET : integer := 1;
49
50 constant TOO_OFFSET : integer := 0;
51
52 type unit_t is (NONE, ALU, LDST, FPU);
53 type length_t is (NONE, is1B, is2B, is4B, is8B);
54
55 type decode_rom_t is record
56 unit : unit_t;
57 insn_type : insn_type_t;
58 input_reg_a : input_reg_a_t;
59 input_reg_b : input_reg_b_t;
60 input_reg_c : input_reg_c_t;
61 output_reg_a : output_reg_a_t;
62
63 input_cr : std_ulogic;
64 output_cr : std_ulogic;
65
66 invert_a : std_ulogic;
67 invert_out : std_ulogic;
68 input_carry : carry_in_t;
69 output_carry : std_ulogic;
70
71 -- load/store signals
72 length : length_t;
73 byte_reverse : std_ulogic;
74 sign_extend : std_ulogic;
75 update : std_ulogic;
76 reserve : std_ulogic;
77
78 -- multiplier and ALU signals
79 is_32bit : std_ulogic;
80 is_signed : std_ulogic;
81
82 rc : rc_t;
83 lr : std_ulogic;
84
85 sgl_pipe : std_ulogic;
86 end record;
87 constant decode_rom_init : decode_rom_t := (unit => NONE,
88 insn_type => OP_ILLEGAL, input_reg_a => NONE,
89 input_reg_b => NONE, input_reg_c => NONE,
90 output_reg_a => NONE, input_cr => '0', output_cr => '0',
91 invert_a => '0', invert_out => '0', input_carry => ZERO, output_carry => '0',
92 length => NONE, byte_reverse => '0', sign_extend => '0',
93 update => '0', reserve => '0', is_32bit => '0',
94 is_signed => '0', rc => NONE, lr => '0', sgl_pipe => '0');
95
96 end decode_types;
97
98 package body decode_types is
99 end decode_types;