distrib/docxml2/text/common/configuration/cnf_disa_output.xml

   1 <?xml version="1.0" encoding="ISO-8859-1" ?>
   2 <glossary>
   3
   4 <row type="split"><article><index>yagOutputName</index></article><def>
   5 <glossary width='small'>
   6 <row><article><f>&lt;string&gt;</f></article><def>Name given to the generated behavioral data flow description</def></row>
   7 <row><article><f>no</f></article><def>Default</def></row>
   8 </glossary>
   9 </def></row>
  10
  11 <row type="split"><article><index>yagGeniusTopName</index></article><def>
  12 <glossary width='small'>
  13 <row><article><f>&lt;string&gt;</f></article><def>Name given to the root structural figure of a hierarchical netlist
  14 generated as a result of GNS</def></row>
  15 </glossary>
  16 </def></row>
  17
  18 <row type="split"><article><index>yagGenerateBehavior</index></article><def>
  19 <glossary width='small'>
  20 <row><article><f>yes</f></article><def>Default, generates the behavioral data flow description.</def></row>
  21 </glossary>
  22 </def></row>
  23
  24 <row type="split"><article><index>yagGenerateConeFile</index></article><def>
  25 <glossary width='small'>
  26 <row><article><f>yes</f></article><def>A <f>.cns</f> file is generated, giving details of the disassembled gates</def></row>
  27 <row><article><f>no</f></article><def>Default</def></row>
  28 </glossary>
  29 </def></row>
  30
  31 <row type="split"><article><index>yagGenerateConeNetList</index></article><def>
  32 <glossary width='small'>
  33 <row><article><f>yes</f></article><def>Generates a structural description of the disassembled gates together
  34 with a behavioral model for each distinct gate type</def></row>
  35 <row><article><f>no</f></article><def>Default</def></row>
  36 </glossary>
  37 </def></row>
  38
  39 <row type="split"><article><index>yagHierarchyGroupTransistors</index></article><def>
  40 <glossary width='small'>
  41 <row><article><f>yes</f></article><def>In hierarchical abstraction mode, any transistors left in an otherwise fully modeled design hierarchy, are grouped together and abstracted as if they were in their own subckt.</def></row>
  42 <row><article><f>no</f></article><def>Default. Any transistors left over will be driven as such (in verilog) or ignored (in vhdl).</def></row>
  43 </glossary>
  44 </def></row>
  45
  46 </glossary>