distrib/docxml2/text/common/formats/file_loading.xml

   1 <section niv='2'><title>File Loading</title>
   2 <p> The purpose of this section is to show how to load files containing:</p>
   3 <list>
   4 <item>Transistor technology models</item>
   5 <item>Design netlist</item>
   6 <item>Parasitic back-annotation</item>
   7 </list>
   8 <p>File loading is done with the Tcl command <f>avt_LoadFile</f>. Depending on
   9 the file format being read, and on the netlist specificities (such as vectors,
  10 connector order,...), additional configuration is sometimes required.
  11 Additional configuration should be set with <f>avt_config</f> Tcl commands,
  12 before invoking <f>avt_LoadFile</f>.</p>
  13
  14 <section niv='3'><title>Transistor Technology Models</title>
  15 <p>Transistor technology models are necessary to compute timings. If those transistor models
  16 appear in a separate file, they should be loaded in the Tcl script with the <f>avt_LoadFile</f> function.
  17 The <f>avt_LoadFile</f> function takes as first argument the name of the file to load, and as second argument
  18 its format. A typical loading of a technology file will be such as:</p>
  19
  20 <code>avt_LoadFile ../models/bsim3.tech spice</code>
  21
  22 <p>If the technology file makes inclusions of other files then inclusion paths should be absolute.
  23 If paths are relative, further configuration will be needed to specify the location of those files:</p>
  24 <code>avt_config avtLibraryDirs .:../models</code>
  25
  26 <p>Technology file can also appear as an inclusion (<f>.INCLUDE</f> or <f>.LIB</f>) in a Spice netlist. In such a case,
  27 it will be loaded at the time the Spice netlist is loaded.</p>
  28 <p>Different industry-standard electrical simulators have different interpretations of the parameters of <f>.MODEL</f>
  29 statement, which also deviate from the Berkeley model (see Berkeley's BSIM3v3.2.4 or BSIM4.3.0 MOSFET Model User's Manual).
  30 This can lead to significant differences in the results given by different simulators.</p>
  31 <p>Besides, the LEVEL parameter which appears in the model files is not discriminant enough. Different simulators may interpret
  32 differently a same LEVEL value (as it is the case for LEVEL 49, differently interpreted by HSPICE and ELDO). Therefore, it is necessary
  33 to specify the targetted simulator of the transistor model. It should be done with the following variable:</p>
  34 <code>avt_Config simToolModel ELDO</code>
  35 <p>If the <f>simToolModel</f> variable is not specified, &tool; will interpret the transistor model as HSPICE does (default value), and check the LEVEL
  36 against the following list:</p>
  37
  38 <code>
  39 <cl>TOOL hspice </cl>
  40 <cl>BSIM3V3  param level   49 </cl>
  41 <cl>BSIM3V3  param level   53 </cl>
  42 <cl>BSIM4    param level   54 </cl>
  43 <cl>PSP      param level 1020 </cl>
  44 <cl>PSPB     param level 1021 </cl>
  45 <cl> </cl>
  46 <cl>TOOL eldo </cl>
  47 <cl>BSIM3V3  param level   49 </cl>
  48 <cl>BSIM3V3  param level   53 </cl>
  49 <cl>BSIM4    param level   60 </cl>
  50 <cl>PSP      param level 1020 </cl>
  51 <cl>PSPB     param level 1021 </cl>
  52 <cl> </cl>
  53 <cl>TOOL ngspice </cl>
  54 <cl>BSIM3V3  param level    8 </cl>
  55 <cl>BSIM4    param level   14 </cl>
  56 <cl> </cl>
  57 <cl> </cl>
  58 <cl>TOOL titan </cl>
  59 <cl>BSIM3V3  model BSM3 setdefault version 3.0 </cl>
  60 <cl>BSIM3V3  model BS32 setdefault version 3.24 </cl>
  61 <cl>BSIM4    model BS4  setdefault version 4.2 </cl>
  62 <cl>BSIM4    model BS41 setdefault version 4.1 </cl>
  63 <cl>BSIM4    model BS42 setdefault version 4.21 </cl>
  64 </code>
  65
  66 <p>If there is a conflict, for example if LEVEL=60 is given and <f>simToolModel</f> is not specified (defaulted to HSPICE), the tool will exit. User needs to
  67 properly set the <f>simToolModel</f> value.</p>
  68
  69 </section>
  70
  71
  72 <section niv='3'><title>Input Netlist</title>
  73 <p>In a way or another, one must
  74 always provide a transistor-level description of the design. If impossible to give a transistor description
  75 for some parts of the netlist, &tool; can also take <f>.lib</f> files as input, but it should be understood that &tool; is
  76 primarily designed for digital transistor-level analysis, and that providing <f>.lib</f> files should only apply
  77 to parts of the netlist where &tool; does not apply, e.g. analog parts. Integration of <f>.lib</f> files will be
  78 discussed later.</p>
  79 <p>A transistor level description can be provided within the following formats:</p>
  80 <list>
  81 <item>Flat-transistor extracted Spice netlist</item>
  82 <item>Hierarchical Spice netlist, with Spice transistor-level leaf cells</item>
  83 <item>Hierarchical Verilog netlist, with Spice transistor-level leaf cells</item>
  84 <item>Hierarchical VHDL netlist, with Spice transistor-level leaf cells</item>
  85 </list>
  86
  87 <p><b>Flat-transistor Spice netlist</b></p>
  88
  89 <p>A flat-transistor extracted Spice netlist is simply loaded with the following command:</p>
  90 <code>avt_LoadFile my_design.spi spice</code>
  91 <p>The file can contain parasitics, and preferably contains a <f>.SUBCKT</f> statement. If not, an implicit
  92 top-level is created, with all the nodes in the netlist reported on the interface. This can lead
  93 to computational explosion in further steps of the analysis.</p>
  94
  95 <p><b>Hierarchical Spice netlist</b></p>
  96
  97 <p>A hierarchical Spice netlist can be represented by several files. Those
  98 files can be loaded either through possibly recursive <f>.INCLUDE</f> statements, or through several
  99 <f>avt_LoadFile</f> commands. However, at least one <f>avt_LoadFile</f> command must appear in the Tcl script.
 100 The netlist is automatically flattened to
 101 the transistor-level, when all the dependancies have been resolved, e.g.
 102 when all instanciated sub-circuits correspond to a sub-circuit definition.</p>
 103
 104 <p>In a separate <f>avt_LoadFile</f> command, sub-circuit definition can appear after its instanciation, the order is
 105 not relevant. For example, the following file can be loaded by <f>avt_LoadFile my_design.spi spice</f>:</p>
 106
 107 <code>
 108 <cl>.SUBCKT my_design ...</cl>
 109 <cl>...</cl>
 110 <cl>.ENDS my_design</cl>
 111 <cl> </cl>
 112 <cl>.INCLUDE ../leaf_cells/n1_y.spi</cl>
 113 <cl>.INCLUDE ../leaf_cells/o3_y.spi</cl>
 114 <cl>.INCLUDE ../leaf_cells/mx2_y.spi</cl>
 115 </code>
 116
 117
 118 <p>Order is relevant if sub-circuit definitions appear in files read by separate <f>avt_LoadFile</f> commands.
 119 In that case reading the files containing sub-circuit definitions must be done before reading the
 120 files containing their instanciation, as shown in the follwing example:</p>
 121 <code>
 122 <cl>avt_LoadFile leaf_cells/n1_y.spi spice</cl>
 123 <cl>avt_LoadFile leaf_cells/o3_y.spi spice</cl>
 124 <cl>avt_LoadFile leaf_cells/mx2_y.spi spice</cl>
 125 <cl>avt_LoadFile my_design.spi spice</cl>
 126 </code>
 127
 128 <p><b>Hierarchical Verilog/VHDL netlist</b></p>
 129
 130 <p>The same example applies to a Verilog netlist and Spice transistor-level leaf-cells:</p>
 131 <code>
 132 <cl>avt_LoadFile leaf_cells/n1_y.spi spice</cl>
 133 <cl>avt_LoadFile leaf_cells/o3_y.spi spice</cl>
 134 <cl>avt_LoadFile leaf_cells/mx2_y.spi spice</cl>
 135 <cl>avt_LoadFile my_design.v verilog</cl>
 136 </code>
 137 <p>or</p>
 138 <code>
 139 <cl>avt_LoadFile my_design.vhd vhdl</cl>
 140 </code>
 141
 142 </section>
 143
 144 <section niv='3'><title>Parasitics</title>
 145 <p>&tool; treats parasitics files of two kinds:</p>
 146 <list>
 147 <item>Parasitics used as a back-annotation of schematic netlists. In such as case, the connectivity
 148 of the schematic netlist is ensured without the parasitics file, which just brings additionnal information.
 149 The formats supported for back-annotation are DSPF and SPEF.</item>
 150 <item>Parasitics used to complete the description of the netlist. In such a case, the netlist is not connected
 151 without the parasitic information. Typically, the RC networks make the connectivity. The formats supported for
 152 connectivity description are Spice and DSPF (in this case the DSPF is used as a Spice file).</item>
 153 </list>
 154
 155 <p><b>Back-annotation</b></p>
 156 <p>When a parasitic file is used to back-annotate a schematic netlist, the schematic netlist
 157 must be loaded first, through a separate <f>avt_LoadFile</f> command. Just invoking the load of the
 158 parasitic file afterwards is enough to perform the back-annotation:</p>
 159 <code>
 160 <cl>avt_loadfile my_design.spi spice</cl>
 161 <cl>avt_loadfile parasitics.spef spef</cl>
 162 </code>
 163 <p>or</p>
 164 <code>
 165 <cl>avt_loadfile my_design.spi spice</cl>
 166 <cl>avt_loadfile parasitics.spf dspf</cl>
 167 </code>
 168
 169 <p>When using back-annotation, special attention should be paid to name consistency between netlist and
 170 parasitics, especially regarding vectors (see next chapter).</p>
 171
 172 <p><b>Connectivity</b></p>
 173 <p>If the parasitics file is necessary to ensure the connectivity of the netlist, the parasitics
 174 and netlist files should be loaded through a single <f>avt_LoadFile</f> command. Parasitic files
 175 should be included at appropriate levels of hierarchy with <f>.INCLUDE</f> statements.</p>
 176
 177 </section>
 178
 179 </section>
 180
 181 <section niv='3'><title>Vectorization</title>
 182 <p>&tool; has two operating modes regarding vectors. One can choose between a mode where vectors
 183 are represented internally as they appear in the source file, and a mode where they are identified
 184 as special signals and represented internally accordingly. When a vector is identified as a special signal,
 185 the internal representation is a string containing the radical and the index separated by a space character. For
 186 example the vector <f>dummy[0]</f> is represented as <f>dummy 0</f>.</p>
 187 <p>Different delimiters can be used to represent vectors. Configuration of legal delimiters, as well as the
 188 choice to treat vectors as special, should be done with the <f>avtVectorize</f> configuration variable:</p>
 189 <code>
 190 <cl>avt_config avtVectorize "[],&lt;&gt;"</cl>
 191 </code>
 192 <p>Treating vectors as special signals is usefull when the same vectors can appear with different delimiters
 193 in different files. For example if a vector is referred to as <f>dummy[0]</f> in a Verilog file, and as
 194 <f>dummy&lt;0&gt;</f> in a SPEF file, the previous configuration is necessary to make the correspondance between
 195 the two names.</p>
 196 </section>
 197
 198 <section niv='3'><title>Ignoring Elements</title>
 199 <p>For a reason or another, some elements in the source files may be unsupported by &tool; or may not respect
 200 standard format syntax. To work around those elements, &tool; provides the means to ignore them during the
 201 parse of the source netlist. The elements that can be ignored are instances, transistors, resistances and
 202 capacitances. For further information please refer to the <f>inf_DefineIgnore</f> command documentation.</p>
 203 </section>
 204