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[tas-yagle.git] / distrib / docxml2 / text / common / formats / power_supplies.xml
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2 <section niv='3'><title>Defining Power Supplies</title>
3 <p>Special attention should be paid to the definition of power supply and ground nodes
4 (<f>avtVddName</f>, <f>avtVssName</f> and <f>simPowerSupply</f> variables).
5 Indeed, the disassembly process is heavily dependant on the naming of those nodes, as the algorithm is looking
6 for current paths towards power supply and ground. Bad specification of these nodes can lead to the construction of
7 an exponential number of wrong current paths. Power supply and ground definition is the first thing to check if the
8 disassembly process seems to loop infinitely.</p>
9 <p>&tool; also supports V cards for the definition of power supply and ground nodes. One can distinguish between two
10 cases:</p>
11 <p>The power supply and ground node appear on the interface of the <f>.SUBCKT</f>, and the subcircuit is instanciated.
12 The V cards should refer to the names used in the instanciation:</p>
13 <code>
14 <cl>Vsupply vdd gnd DC 1.2V</cl>
15 <cl>Vground gnd 0 DC 0V</cl>
16 <cl> </cl>
17 <cl>.SUBCKT my_design a b c vdd_int gnd_int</cl>
18 <cl>... </cl>
19 <cl>.ENDS my_design </cl>
20 <cl> </cl>
21 <cl>X0 a b c vdd gnd my_design</cl>
22 </code>
23
24
25 <p>The power supply and ground node does not appear on the interface of the <f>.SUBCKT</f>, or the subcircuit is not
26 instanciated. The V cards should refer to the names used within the subcircuit, or appearing on the interface of
27 the <f>.SUBCKT</f>, together with <f>.GLOBAL</f> statements:</p>
28 <code>
29 <cl>.GLOBAL vdd gnd</cl>
30 <cl> </cl>
31 <cl>Vsupply vdd gnd DC 1.2V</cl>
32 <cl>Vground gnd 0 DC 0V</cl>
33 <cl> </cl>
34 <cl>.SUBCKT my_design a b c vdd gnd</cl>
35 <cl>... </cl>
36 <cl>.ENDS my_design </cl>
37 </code>
38 </section>