projects / tas-yagle.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Initial version of donated sources by Avertec, 3.4p5.
[tas-yagle.git] / distrib / docxml2 / text / common / formats / slack_reports.xml
1 <?xml version="1.0" encoding="ISO-8859-1" ?>
2
3 <section niv='2'><title>Timing Checks</title>
4 <p>The next sections explain how timing checks are performed. They describe the more common situations one can be faced to,
5 i.e.:</p>
6 <list>
7 <item>Input to latch</item>
8 <item>Latch to latch</item>
9 <item>Latch to output</item>
10 </list>
11
12 <p>For each situation, an example of slack report is shown, and we explain the details of the timing checks calculation.</p>
13
14 <section niv='3'><title>Input to Latch</title>
15
16 <section niv='4'><title>Inputs Specifications</title>
17 <p>Regarding input specifications, the STA engine of &tool; makes the assumption that input
18 data is coming from a latch clocked on the opposite phase of the one the data arrives on.
19 In our flip-flop example, <f>dff_m</f> is opened on the high state of <f>ck</f>, so <f>di</f>
20 is supposed to come from a latch opened on the low state of <f>ck</f>.</p>
21 <imgsize namehtml="input_spec.gif" namepdf="input_spec.gif" hpdf="100pt" wpdf="220pt"/>
22 <p>As a result, <f>di</f> should be specified as coming from <f>ck</f> falling, i.e. when the
23 latch <f>src</f> opens. The corresponding SDC commands should look like:</p>
24 <code>
25 <cl>create_clock -period 1000 -waveform {500 0} ck</cl>
26 <cl>set_input_delay -clock -ck -clock_fall -min 200 di</cl>
27 <cl>set_input_delay -clock -ck -clock_fall -max 300 di</cl>
28 </code>
29
30 </section>
31
32 <section niv='4'><title>Timing Checks Description</title>
33 <p>Diagram below illustrates the way <f>set_input_delay</f> directives are propagated throughout the design, and
34 where timing checks are performed.</p>
35 <imgsize namehtml="gen_inp_slack.gif" namepdf="gen_inp_slack.gif" wpdf="400pt"/>
36 </section>
37
38 <section niv='4'><title>Setup Slack</title>
39 <p>Input to latch setup slack report is described in the <f>slack.rep</f> file </p>
40 <smallcode>
41 <cl>Path (4) : Slack of 0.762 </cl>
42 <cl> DATA VALID: </cl>
43 <cl> Delay </cl>
44 <cl> Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line </cl>
45 <cl> ____________________________________________________________________________________ </cl>
46 <cl> 0.300 0.000 0.200 R 0.034 di di </cl>
47 <cl> 0.498 0.198 0.310 F 0.028 (L) dff_m dff_m master </cl>
48 <cl> ____________________________________________________________________________________ </cl>
49 <cl> 0.498 0.198 (total) </cl>
50 <cl> </cl>
51 <cl> DATA REQUIRED: </cl>
52 <cl> Delay </cl>
53 <cl> Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line </cl>
54 <cl> __________________________________________________________________________________ </cl>
55 <cl> 0.000 0.000 0.200 F 0.016 (C) ck ck </cl>
56 <cl> 0.239 0.239 0.258 R 0.046 (CK) ckn ckn inv </cl>
57 <cl> 0.340 0.101 0.140 F 0.036 (CK) ckp ckp inv </cl>
58 <cl> 0.260 -0.081 [INTRINSIC SETUP] </cl>
59 <cl> 1.260 +1.000 [NEXT PERIOD] </cl>
60 <cl> __________________________________________________________________________________ </cl>
61 <cl> 1.260 0.260 (total) </cl>
62 <cl> </cl>
63 </smallcode>
64 <p>The value of the setup slack is given by clock_path - data_path = 1260ps - 498ps = 762ps. The intrinsic setup corresponds to an
65 additional delay which models the amount of time required for secure memorization of the data.</p>
66 </section>
67
68 <section niv='4'><title>Hold Slack</title>
69 <p>Input to latch hold slack report is described in the <f>slack.rep</f> file </p>
70 <smallcode>
71 <cl>Path (2) : Slack of 0.005 </cl>
72 <cl> DATA VALID: </cl>
73 <cl> Delay </cl>
74 <cl> Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line </cl>
75 <cl> ____________________________________________________________________________________ </cl>
76 <cl> 0.200 0.000 0.200 F 0.034 di di </cl>
77 <cl> 0.542 0.342 0.508 R 0.028 (L) dff_m dff_m master </cl>
78 <cl> ____________________________________________________________________________________ </cl>
79 <cl> 0.542 0.342 (total) </cl>
80 <cl> </cl>
81 <cl> DATA REQUIRED: </cl>
82 <cl> Delay </cl>
83 <cl> Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line </cl>
84 <cl> __________________________________________________________________________________ </cl>
85 <cl> 0.000 0.000 0.200 F 0.016 (C) ck ck </cl>
86 <cl> 0.239 0.239 0.258 R 0.046 (CK) ckn ckn inv </cl>
87 <cl> 0.537 +0.298 [INTRINSIC HOLD] </cl>
88 <cl> __________________________________________________________________________________ </cl>
89 <cl> 0.537 0.537 (total) </cl>
90 <cl> </cl>
91 </smallcode>
92
93 <p>The value of the hold slack is given by data_path - clock_path = 542ps - 537ps = 5ps. The intrinsic hold corresponds to an
94 additional delay which models the amount of time required for ensuring that the next cycle's data is not memorized in the current cycle.</p>
95 </section>
96
97
98 </section>
99
100 <section niv='3'><title>Latch to Latch</title>
101 <section niv='4'><title>Timing Checks Description</title>
102 <p>Latch to latch timing checks require no additional configuration, as they are based upon
103 the signals already propagated from inputs, and upon the clock specification. The
104 propagation of the s.w., and corresponding timing checks are described in the following
105 timing diagram:</p>
106 <imgsize namehtml="gen_ms_slck.gif" namepdf="gen_ms_slck.gif" hpdf="280pt" wpdf="370pt"/>
107 </section>
108 <section niv='4'><title>Setup Slack</title>
109 <p>Latch to latch setup slack report is described in the <f>slack.rep</f> file </p>
110 <smallcode>
111 <cl>Path (3) : Slack of 0.284 </cl>
112 <cl> DATA VALID: </cl>
113 <cl> Delay </cl>
114 <cl> Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line </cl>
115 <cl> _____________________________________________________________________________________ </cl>
116 <cl> -0.500 0.000 0.200 R 0.016 (C) ck ck </cl>
117 <cl> -0.399 0.101 0.128 F 0.046 (CK) ckn ckn inv </cl>
118 <cl> -0.236 0.164 0.169 R 0.036 (CK) ckp ckp inv </cl>
119 <cl> -0.152 0.083 0.139 F 0.028 (L) dff_m dff_m master </cl>
120 <cl> 0.090 0.242 0.189 R 0.040 n11 n11 inv </cl>
121 <cl> 0.321 0.231 0.305 F 0.089 (L) dff_s dff_s slave </cl>
122 <cl> _____________________________________________________________________________________ </cl>
123 <cl> 0.321 0.821 (total) </cl>
124 <cl> </cl>
125 <cl> DATA REQUIRED: </cl>
126 <cl> Delay </cl>
127 <cl> Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line </cl>
128 <cl> ___________________________________________________________________________________ </cl>
129 <cl> 0.500 0.000 0.200 R 0.016 (C) ck ck </cl>
130 <cl> 0.601 0.101 0.128 F 0.046 (CK) ckn ckn inv </cl>
131 <cl> 0.605 +0.005 [INTRINSIC SETUP] </cl>
132 <cl> ___________________________________________________________________________________ </cl>
133 <cl> 0.605 0.105 (total) </cl>
134 </smallcode>
135 </section>
136
137 <section niv='4'><title>Hold Slack</title>
138 <p>Latch to latch hold slack report is described in the <f>slack.rep</f> file </p>
139 <smallcode>
140 <cl>Path (3) : Slack of 0.146 </cl>
141 <cl> DATA VALID: </cl>
142 <cl> Delay </cl>
143 <cl> Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line </cl>
144 <cl> ____________________________________________________________________________________ </cl>
145 <cl> -0.500 0.000 0.200 R 0.016 (C) ck ck </cl>
146 <cl> -0.399 0.101 0.128 F 0.046 (CK) ckn ckn inv </cl>
147 <cl> -0.281 0.119 0.177 R 0.028 (L) dff_m dff_m master </cl>
148 <cl> -0.223 0.057 0.088 F 0.040 n11 n11 inv </cl>
149 <cl> 0.106 0.329 0.447 R 0.089 (L) dff_s dff_s slave </cl>
150 <cl> ____________________________________________________________________________________ </cl>
151 <cl> 0.106 0.606 (total) </cl>
152 <cl> </cl>
153 <cl> DATA REQUIRED: </cl>
154 <cl> Delay </cl>
155 <cl> Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line </cl>
156 <cl> __________________________________________________________________________________ </cl>
157 <cl> 0.500 0.000 0.200 R 0.016 (C) ck ck </cl>
158 <cl> 0.601 0.101 0.128 F 0.046 (CK) ckn ckn inv </cl>
159 <cl> 0.764 0.164 0.169 R 0.036 (CK) ckp ckp inv </cl>
160 <cl> 0.960 +0.196 [INTRINSIC HOLD] </cl>
161 <cl> -0.040 -1.000 [PREVIOUS PERIOD] </cl>
162 <cl> __________________________________________________________________________________ </cl>
163 <cl> -0.040 0.460 (total) </cl>
164 </smallcode>
165
166 </section>
167
168 </section>
169
170 <section niv='3'><title>Latch to Output</title>
171
172 <section niv='4'><title>Output Constraints</title>
173 <p>Still based on the flip-flop design described above, the timing propagation on output <f>t</f> is done as follow:</p>
174
175 <imgsize namehtml="ms_output.gif" namepdf="ms_output.gif" wpdf="400pt"/>
176 <p>In order to get setup and hold slacks on the output, one must define timing
177 constraints on <f>t</f>. These timing constraints are defined with the
178 <f>set_output_delay</f> SDC function. The <f>set_output_delay</f> specifies propagation
179 delays from output connector to the next memory element latching the data. As a result,
180 min and max delays are defined as shown in the diagram below.</p>
181
182 <imgsize namehtml="output_spec.gif" namepdf="output_spec.gif" hpdf="100pt" wpdf="220pt"/>
183
184 <p>One must also define the edge the data will be latched by. Here, <f>dff_s</f> is closed
185 on the high state of <f>ck</f>. The data launched by <f>t</f> is supposed to be latched by
186 a memory element clocked on the opposite phase, i.e. closed on low state of <f>ck</f>. Therefore,
187 constraints on <f>t</f> should be specified relative to falling edge of <f>ck</f> (when <f>dst</f>
188 latch closes). The <f>set_output_delay</f> functions should be used as follow:</p>
189 <code>
190 <cl>set_output_delay -clock ck -clock_fall -min 200 t</cl>
191 <cl>set_output_delay -clock ck -clock_fall -max 400 t</cl>
192 </code>
193
194 </section>
195
196 <section niv='4'><title>Setup Slack</title>
197 <p>Latch to output setup slack report is described in the <f>slack.rep</f> file </p>
198 <smallcode>
199 <cl>Path (1) : Slack of 0.030 </cl>
200 <cl> DATA VALID: </cl>
201 <cl> Delay </cl>
202 <cl> Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line </cl>
203 <cl> ______________________________________________________________________________ </cl>
204 <cl> 0.000 0.000 0.200 F 0.016 (C) ck ck </cl>
205 <cl> 0.239 0.239 0.258 R 0.046 (CK) ckn ckn inv </cl>
206 <cl> 0.340 0.101 0.140 F 0.036 (CK) ckp ckp inv </cl>
207 <cl> 0.568 0.227 0.327 R 0.089 (L) dff_s dff_s slave </cl>
208 <cl> 0.570 0.003 0.118 F 0.011 (S) t t inv </cl>
209 <cl> ______________________________________________________________________________ </cl>
210 <cl> 0.570 0.570 (total) </cl>
211 <cl> </cl>
212 <cl> -> Specification: Must be stable after 0.600 </cl>
213 <cl> </cl>
214 </smallcode>
215 <p>The setup time is calculated with the maximum set_output_delay value - maximum data path - which is 400ps. As the period is 1000ps,
216 data must arrive before time 1000 - 400 = 600ps. The setup slack is given by 600 - 570 = 30ps.</p>
217 </section>
218
219 <section niv='4'><title>Hold Slack</title>
220 <p>Latch to output hold slack report is described in the <f>slack.rep</f> file </p>
221 <smallcode>
222 <cl>Path (5) : Slack of 0.635 </cl>
223 <cl> DATA VALID: </cl>
224 <cl> Delay </cl>
225 <cl> Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line </cl>
226 <cl> _____________________________________________________________________________ </cl>
227 <cl> 0.000 0.000 0.200 F 0.016 (C) ck ck </cl>
228 <cl> 0.239 0.239 0.258 R 0.046 (CK) ckn ckn inv </cl>
229 <cl> 0.385 0.146 0.235 F 0.089 (L) dff_s dff_s slave </cl>
230 <cl> 0.435 0.050 0.082 R 0.011 (S) t t inv </cl>
231 <cl> _____________________________________________________________________________ </cl>
232 <cl> 0.435 0.435 (total) </cl>
233 <cl> </cl>
234 <cl> -> Specification: Must be stable before -0.200 </cl>
235 <cl> </cl>
236 </smallcode>
237
238 <p>The hold time is calculated with the minimum set_output_delay value - minimum data path - which is 200ps. The hold slack
239 is given by data path - clock path = 435 + 200 - 0 (the clock is ideal in the set_output_delay definition) = 635ps.</p>
240
241 </section>
242 </section>
243 </section>