distrib/docxml2/text/doc/gns_tutorial/genRAM.xml

   1 <?xml version="1.0" encoding="ISO-8859-1" ?>
   2 <chapter>
   3 <section niv='1'><title>The generated RAMs</title>
   4 <section niv='2'><title>Description</title>
   5
   6
   7 <p>A generated Random Acess Memory
   8 is always made of two banks, constituted of an arbitrary number of bit lines, between which is placed a decoder cell. The
   9 interfaces of the RAM are given below (there are two versions of the interface because
  10 input and output data can be bidirectional or separated):</p>
  11
  12 <p>bidirectional <f>data</f> bus:</p>
  13
  14 <code>
  15 <cl>ENTITY rage IS</cl>
  16 <cl>  PORT (adr: IN BIT_VECTOR (0 TO n);</cl>
  17 <cl>        data: INOUT BIT_VECTOR (0 TO w);</cl>
  18 <cl>        ck: IN BIT;</cl>
  19 <cl>        write: IN BIT;</cl>
  20 <cl>        en: IN BIT;</cl>
  21 <cl>        vdd: IN BIT;</cl>
  22 <cl>        vss: IN BIT);</cl>
  23 <cl>END rage;</cl>
  24 </code>
  25 <p>separate <f>din</f> and <f>dout</f> busses:</p>
  26 <code>
  27 <cl>ENTITY rage IS</cl>
  28 <cl>  PORT (adr: IN BIT_VECTOR (0 TO n);</cl>
  29 <cl>        din: IN BIT_VECTOR (0 TO w);</cl>
  30 <cl>        dout: OUT BIT_VECTOR (0 TO w);</cl>
  31 <cl>        ck: IN BIT;</cl>
  32 <cl>        write: IN BIT;</cl>
  33 <cl>        en: IN BIT;</cl>
  34 <cl>        vdd: IN BIT;</cl>
  35 <cl>        vss: IN BIT);</cl>
  36 <cl>END rage;</cl>
  37 </code>
  38
  39 <p>The signals <f> write </f> and <f> en </f>
  40 are both active high. The RAM is in precharge mode if <f> ck </f>
  41 is high for -ckup option RAMs (conversly if <f> ck </f> is low for -ckdown option RAMs),
  42 otherwise it is in evaluation mode (read or write). The <f> en </f>
  43 signal suspends the normal operation
  44 of the RAM by disabling it when its value is '0'. In this case the RAM remains in precharge mode.
  45 The <f> en </f> signal must change only during the precharge phase.</p>
  46
  47 </section>
  48 <section niv='2'><title>Parameters</title>
  49
  50
  51 <p>The number of bits per word is scalable from 2 to 128, and this number must be even. The number of
  52 words is also scalable, possible values are 128, 256, 512, 1024, 2048 and 4096. In this tutorial, we
  53 use RAMs with bidirectionnal <f>data</f> bus, one of 128 words of 4 bits, another one of 256 words of 8 bits,
  54 and a bigger one of 1096 words of 4 bits.</p>
  55
  56
  57 </section>
  58 <section niv='2'><title>Timing diagrams</title>
  59
  60 <p>The timing diagrams for a ck-high RAM are given below. The following diagram presents the read and
  61 write configurations for a RAM with a bidirectional bus <f>data</f>:</p>
  62 <imgsize namehtml="waveform_bidir.gif" namepdf="waveform_bidir.gif" hpdf="98pt" wpdf="368pt" />
  63 <p>The following diagram presents the read and write conditions for a RAM with separate <f>din</f> and <f>dout</f> busses:</p>
  64 <imgsize namehtml="waveform_unidir.gif" namepdf="waveform_unidir.gif" hpdf="124pt" wpdf="368pt" />
  65
  66 </section>
  67
  68 </section></chapter>