distrib/docxml2/text/doc/gns_tutorial/overview.xml

   1 <?xml version="1.0" encoding="ISO-8859-1" ?>
   2 <chapter>
   3 <section niv='1'><title>Overview</title>
   4 <section niv='2'><title>The verification flow</title>
   5
   6 <p>The Random Access Memory generator generates the layout of RAMs of different sizes, ranging
   7 from 256 bits to 512 kbits. The principle of the validation flow we present here is as follow:</p>
   8 <imgsize namehtml="verif_flow.gif" namepdf="verif_flow.gif" hpdf="235pt" wpdf="160pt" />
   9 <list>
  10 <item>The transistor netlist is extracted from the generated layout of the RAM.</item>
  11 <item>&tool; applies on this transistor netlist structural rules, which are the
  12 recognition of VHDL structural descriptions.</item>
  13 <item>When all the rules are satisfied, &tool; generates the behavioral VHDL of the RAM,
  14 from the behavioral descriptions associated with the structural descriptions.</item>
  15 <item>The VHDL is analyzed by simulation.</item>
  16 </list>
  17 <p>This tutorial presents the generation with YAGLE-GNS of the VHDL of several examples of generated RAMs.</p>
  18
  19 </section>
  20 <section niv='2'><title>The tutorial organization</title>
  21
  22 <p>This tutorial presents a step-by-step organization guiding the reader through all the steps of
  23 setting up the validation flow. Following this tutorial, you will be able to:</p>
  24 <list>
  25 <item>Understand the architecture of the generated RAMs. A presentation of this architecture
  26 is made through sections 2.1 to 2.3.</item>
  27 <item>Understand &tool; operating modes. Chapter 3 explains the validation concepts of
  28 &tool; and how to apply them on the generated RAMs.</item>
  29 <item>Write &tool; rules for structural validation. The writing of the structural rules
  30 is thoroughly explained in chapter 4. Following the steps described in this chapter, you will
  31 progressively integrate all the rules until complete validation.</item>
  32 <item>Write generic actions, generating a simulatable VHDL for a RAM of any size.</item>
  33 </list>
  34
  35 </section>
  36 <section niv='2'><title>Files</title>
  37 <section niv='3'><title>Installation location</title>
  38
  39 <p>All the pathes mentioned below are given relatively to your installation directory, which
  40 will be refered as <f>AVT_TOOLS_DIR</f>. The variable <f>AVT_OS</f> specifies the type of
  41 architecture you are working on (Linux or Solaris_2.5 to Solaris_2.8).</p>
  42
  43 </section>
  44 <section niv='3'><title>YAGLE-GNS</title>
  45
  46
  47 <p>The executable of &tool; is:</p>
  48
  49 <p><f>$AVT_TOOLS_DIR/tools/$AVT_OS/bin/yagle</f></p>
  50
  51 <p>&tool; uses the configuration file <f>avttools.conf</f>, and the directory <f>cells/</f> containing the rules for
  52 both structural and functional validation.</p>
  53
  54 <p>The <f>avttools.conf</f> and the directory <f>cells/</f> are located in the working directory (see below).</p>
  55
  56
  57 </section>
  58
  59 <section niv='3'><title>Working directories</title>
  60
  61 <p>The root working directory is:</p>
  62
  63 <p><f>$AVT_TOOLS_DIR/tutorial/&MIN;</f></p>
  64
  65 <p>It contains four directories: the three directories, <f>ram4x128/</f>, <f>ram8x256/</f> and <f>ram4x4096/</f>,
  66 referring to the three RAM examples, and the directory <f>cells/</f>, containing the recognition rules.
  67 Each of the three directories <f>ram4x128/</f>, <f>ram8x256/</f> and <f>ram4x4096/</f>, contains four files.</p>
  68
  69 <p>The file <f>avttools.conf</f> is the configuration file for &tool;.</p>
  70
  71 <p>The files <f>ram4x128.spi</f>, <f>ram8x256.spi</f> or <f>ram4x4096.spi</f> are the extracted netlists (with
  72 resistances and capacitances) of the three different RAMs in SPICE format.</p>
  73
  74 <p>The files <f>tb_ram4x128.vhd</f>, <f>tb_ram8x256.vhd</f> or <f>tb_ram4x4096.vhd</f> are the test benches for the
  75 simulation.</p>
  76
  77 <p>The files <f>ram4x128.pat</f>, <f>ram8x256.pat</f> or <f>ram4x4096.pat</f> are the corresponding pattern files.</p>
  78
  79
  80 </section>
  81 </section>
  82
  83 </section></chapter>