distrib/docxml2/text/doc/gns_tutorial/structval.xml

   1 <?xml version="1.0" encoding="ISO-8859-1" ?>
   2 <chapter>
   3 <section niv='1'><title>Structural validation</title>
   4 <section niv='2'><title>Writing the &tool; recognition rules</title>
   5
   6 <p>We describe here the set of rules which must be applied on the RAM to recognize the matrix, i.e. the block
   7 constituted of two banks
   8 together with the command buffers. Each bank is formed by a row of bit-lines.</p>
   9
  10 <p>The hierarchical recognition starts from the lower levels, therefore the rules must be written
  11 in the following order: firstly for a bit-line, then for a bank, and finally for the matrix.</p>
  12
  13 <p>All these rules are already written, and each rule is described in a separate file with a <f>.vhd</f>
  14 extension. All the rule files are located in the <f>cells/</f> directory.
  15 The special file <f>cells/LIBRARY</f>
  16 indicates to &tool; which of those rules are to be applied, and in which order.</p>
  17
  18 <p>In the following sections, we will progressively integrate the rules in the <f>LIBRARY</f> file,
  19 and apply them to the netlist <f>ram4x128.spi</f>, until the complete
  20 recognition of the two-ram-cell block. The rules are made generic so they can as well be applied to the two other RAMs.
  21 We will see how.</p>
  22 </section>
  23 <last></last>
  24 <section niv='2'><title>Recognition rules for a bit-line</title>
  25 <section niv='3'><title>Transistor level leaves</title>
  26 <p>A bit-line has the following structure:</p>
  27 <imgsize namehtml="bitline_leaves.gif" namepdf="bitline_leaves.gif" hpdf="345pt" wpdf="368pt" />
  28 <p>The first step of recognition consists in describing the transistor-level leaves (grayscale parts of the figure).
  29 The recognition rules for those leaves are described in the next sections, and refer to the files <f>mem_cell.vhd</f>,
  30 <f>sense_amp.vhd</f>, <f>precharge.vhd</f> and <f>write_enable.vhd</f>.</p>
  31 <pagebreak/>
  32 <section niv='4'><title>Memory cell</title>
  33
  34 <code>
  35 <cl>ENTITY mem_cell IS </cl>
  36 <cl>  PORT (q, nq: INOUT BIT;</cl>
  37 <cl>        com: IN BIT;</cl>
  38 <cl>        vdd, vss: IN BIT</cl>
  39 <cl>  );</cl>
  40 <cl>  -- pragma symmetric q nq</cl>
  41 <cl>  -- pragma symmetric com</cl>
  42 <cl>END;</cl>
  43 <cl> </cl>
  44 <cl>ARCHITECTURE archi OF mem_cell IS
  45 </cl>
  46 <cl>  COMPONENT tn </cl>
  47 <cl>    PORT (grid: IN BIT; source, drain: INOUT BIT); </cl>
  48 <cl>  END COMPONENT;</cl>
  49 <cl>  COMPONENT tp </cl>
  50 <cl>    PORT (grid: IN BIT; source, drain: INOUT BIT); </cl>
  51 <cl>  END COMPONENT;</cl>
  52 <cl> </cl>
  53 <cl>  SIGNAL s_q, s_nq: BIT;
  54 </cl>
  55 <cl> </cl>
  56 <cl>BEGIN</cl>
  57 <cl>  t0: tn PORT MAP (com,  s_q,  q);</cl>
  58 <cl>  t1: tn PORT MAP (com,  s_nq, nq);</cl>
  59 <cl>  t2: tn PORT MAP (s_q,  vss,  s_nq);</cl>
  60 <cl>  t3: tp PORT MAP (s_q,  vdd,  s_nq);</cl>
  61 <cl>  t4: tn PORT MAP (s_nq, vss,  s_q);</cl>
  62 <cl>  t5: tp PORT MAP (s_nq, vdd,  s_q);</cl>
  63 <cl>END;</cl>
  64 </code>
  65 <p>The directive <f>-- pragma symmetric q nq</f> is essential for the further steps
  66 of the recognition. As a memory cell is intrinsicly symmetric,
  67 the <f>q</f> (<f>nq</f>) port of the rule may match either the <f>q</f> or <f>nq</f>
  68 signal in the transistor netlist. This directive allows the program to consider <f>q</f>
  69 and <f>nq</f> as identical.</p>
  70
  71 </section>
  72 <section niv='4'><title>Sense amplifier</title>
  73
  74
  75 <p>The generated RAMs use different architectures of sense amplifiers, depending
  76 on the size of the generated RAM. The 4 x 128 and 8 x 256 RAMs use the first architecture, as
  77 the 4 x 4096 RAM uses the second one.</p>
  78 <p>In order to use the same rule for the three different RAMs, we have introduced in the
  79 'sense_amp' rule those two possible architectures. In the recognition process,
  80 &tool; will try to identify each one of the architectures.</p>
  81 <last> </last>
  82 <code>
  83 <cl>ENTITY sense_amp IS</cl>
  84 <cl>    PORT (</cl>
  85 <cl>        data, ndata : IN BIT;</cl>
  86 <cl>        cke, ckp : IN BIT;</cl>
  87 <cl>        x : OUT BIT;</cl>
  88 <cl>        vdd, vss : IN BIT</cl>
  89 <cl>    );</cl>
  90 <cl>    -- pragma symmetric data ndata</cl>
  91 <cl>END;</cl>
  92 <cl> </cl>
  93 <cl>ARCHITECTURE sa OF sense_amp is</cl>
  94 <cl>    </cl>
  95 <cl>  COMPONENT tp </cl>
  96 <cl>    PORT (grid: IN BIT; </cl>
  97 <cl>          source, draIN: INOUT BIT); </cl>
  98 <cl>    END COMPONENT;</cl>
  99 <cl>  COMPONENT tn </cl>
 100 <cl>    PORT (grid: IN BIT; </cl>
 101 <cl>          source, draIN : INOUT BIT); </cl>
 102 <cl>  END COMPONENT;</cl>
 103 <cl>    </cl>
 104 <cl>  SIGNAL sig, nsig, dout : BIT;</cl>
 105 <cl>  SIGNAL c1, c2, c3 : BIT;</cl>
 106 <cl>  SIGNAL s1, s2, s3 : BIT;</cl>
 107 <cl>    </cl>
 108 <cl>BEGIN</cl>
 109 <cl>  sa0_0 : tp PORT MAP (c1,    c1,   vdd);</cl>
 110 <cl>  sa0_1 : tp PORT MAP (c1,    sig,  vdd);</cl>
 111 <cl>  sa0_2 : tn PORT MAP (data,  c1,   s1);</cl>
 112 <cl>  sa0_3 : tn PORT MAP (ndata, sig,  s1);</cl>
 113 <cl>  sa0_4 : tn PORT MAP (cke,   s1,   vss);</cl>
 114 <cl>  sa1_0 : tp PORT MAP (c2,    c2,   vdd);</cl>
 115 <cl>  sa1_1 : tp PORT MAP (c2,    nsig, vdd);</cl>
 116 <cl>  sa1_2 : tn PORT MAP (ndata, c2,   s2);</cl>
 117 <cl>  sa1_3 : tn PORT MAP (data,  nsig, s2);</cl>
 118 <cl>  sa1_4 : tn PORT MAP (cke,   s2,   vss);</cl>
 119 <cl>  sa2_0 : tp PORT MAP (c3,    c3,   vdd);</cl>
 120 <cl>  sa2_1 : tp PORT MAP (c3,    x,    vdd);</cl>
 121 <cl>  sa2_2 : tn PORT MAP (sig,   c3,   s3);</cl>
 122 <cl>  sa2_3 : tn PORT MAP (nsig,  x,    s3);</cl>
 123 <cl>  sa2_4 : tn PORT MAP (cke,   s3,   vss);</cl>
 124 <cl>  link  : tn PORT MAP (ckp,   sig,  nsig);</cl>
 125 <cl>END;     </cl>
 126 <cl> </cl>
 127 <cl>ARCHITECTURE sa2 OF sense_amp is</cl>
 128 <cl> </cl>
 129 <cl>  COMPONENT tp </cl>
 130 <cl>    PORT (grid: IN BIT; </cl>
 131 <cl>          source, draIN: INOUT BIT); </cl>
 132 <cl>    END COMPONENT;</cl>
 133 <cl>  COMPONENT tn </cl>
 134 <cl>    PORT (grid: IN BIT; </cl>
 135 <cl>          source, draIN: INOUT BIT); </cl>
 136 <cl>  END COMPONENT;</cl>
 137 <cl>    </cl>
 138 <cl>  SIGNAL sig, nsig: BIT;</cl>
 139 <cl>  SIGNAL s1, s2, s3: BIT;</cl>
 140 <cl>  SIGNAL c1, c2, c3: BIT;</cl>
 141 <cl> </cl>
 142 <cl>BEGIN</cl>
 143 <cl>  sa2_0  : tp PORT MAP (c1,    c1,   vdd);</cl>
 144 <cl>  sa2_1  : tn PORT MAP (ndata, s1,   c1);</cl>
 145 <cl>  sa2_2  : tp PORT MAP (c2,    c2,   vdd);</cl>
 146 <cl>  sa2_3  : tn PORT MAP (data,  c2,   s1);</cl>
 147 <cl>  sa2_4  : tn PORT MAP (cke,   s1,   vss);</cl>
 148 <cl>  sa2_5  : tp PORT MAP (c1,    nsig, vdd);</cl>
 149 <cl>  sa2_6  : tn PORT MAP (data,  nsig, s2);</cl>
 150 <cl>  sa2_7  : tn PORT MAP (cke,   s2,   vss);</cl>
 151 <cl>  sa2_8  : tp PORT MAP (c2,    sig,  vdd);</cl>
 152 <cl>  sa2_9  : tn PORT MAP (ndata, sig,  s2);</cl>
 153 <cl>  sa2_10 : tn PORT MAP (ckp,   sig,  nsig);</cl>
 154 <cl>  sa_0   : tp PORT MAP (c3,    c3,   vdd);</cl>
 155 <cl>  sa_1   : tp PORT MAP (c3,    x,    vdd);</cl>
 156 <cl>  sa_2   : tn PORT MAP (sig,   c3,   s3);</cl>
 157 <cl>  sa_3   : tn PORT MAP (nsig,  x,    s3);</cl>
 158 <cl>  sa_4   : tn PORT MAP (cke,   s3,   vss);</cl>
 159 <cl>END;</cl>
 160 </code>
 161
 162 </section>
 163 <section niv='4'><title>Precharge</title>
 164
 165 <code>
 166 <cl>ENTITY precharge IS</cl>
 167 <cl>  PORT (q, nq: INOUT BIT;</cl>
 168 <cl>        ck: IN BIT;</cl>
 169 <cl>        vdd: IN BIT);</cl>
 170 <cl>  -- pragma symmetric q nq</cl>
 171 <cl>END; </cl>
 172 <cl> </cl>
 173 <cl>ARCHITECTURE nq_q OF precharge IS </cl>
 174 <cl> </cl>
 175 <cl>  COMPONENT tn</cl>
 176 <cl>    PORT (grid: IN BIT; source, drain: INOUT BIT); </cl>
 177 <cl>  END COMPONENT; </cl>
 178 <cl> </cl>
 179 <cl>BEGIN</cl>
 180 <cl>  t0: tn PORT MAP (ck, q,  vdd);</cl>
 181 <cl>  t1: tn PORT MAP (ck, nq, vdd);</cl>
 182 <cl>  t2: tn PORT MAP (ck, q,  nq);</cl>
 183 <cl>END;</cl>
 184 </code>
 185
 186 </section>
 187
 188
 189 <pagebreak/>
 190 <section niv='4'><title>Write enable</title>
 191
 192 <code>
 193 <cl>ENTITY write_enable IS</cl>
 194 <cl>  PORT (din, wen: IN BIT;</cl>
 195 <cl>        q, nq: INOUT BIT;</cl>
 196 <cl>        vss, vdd: IN BIT);</cl>
 197 <cl>  -- pragma symmetric q nq</cl>
 198 <cl>END; </cl>
 199 <cl> </cl>
 200 <cl>ARCHITECTURE write_enable OF write_enable IS </cl>
 201 <cl> </cl>
 202 <cl>  COMPONENT tp </cl>
 203 <cl>    PORT (grid: IN BIT; source, drain: INOUT BIT); </cl>
 204 <cl>  END COMPONENT;</cl>
 205 <cl>  COMPONENT tn </cl>
 206 <cl>    PORT (grid: IN BIT; source, drain: INOUT BIT); </cl>
 207 <cl>  END COMPONENT; </cl>
 208 <cl> </cl>
 209 <cl>  SIGNAL s2_q, s_nq, s_q: BIT; </cl>
 210 <cl> </cl>
 211 <cl>BEGIN</cl>
 212 <cl>  t0: tn PORT MAP (wen,  q,   s_q);</cl>
 213 <cl>  t1: tn PORT MAP (wen,  nq,  s_nq);</cl>
 214 <cl>  t2: tn PORT MAP (din,  vss, s_nq);</cl>
 215 <cl>  t3: tp PORT MAP (din,  vdd, s_nq);</cl>
 216 <cl>  t4: tn PORT MAP (s2_q, vss, s_q);</cl>
 217 <cl>  t5: tp PORT MAP (s2_q, vdd, s_q);</cl>
 218 <cl>  t6: tn PORT MAP (din,  vss, s2_q);</cl>
 219 <cl>  t7: tp PORT MAP (din,  vdd, s2_q);</cl>
 220 <cl>END;</cl>
 221 </code>
 222
 223 </section>
 224
 225 <section niv='4'><title>Performing the recognition</title>
 226
 227 <p>To perform the recognition of the transistor leaves described above, edit the <f>LIBRARY</f> file, and
 228 uncomment the following lines:</p>
 229 <code>
 230 <cl>mem_cell.vhd;</cl>
 231 <cl>write_enable.vhd;</cl>
 232 <cl>precharge.vhd;</cl>
 233 <cl>sense_amp.vhd;</cl>
 234 </code>
 235
 236 <p>Type the command line <f> yagle -xg -rp -v ram4x128</f></p>
 237
 238 <p>The <f>-xg</f> option performs the &tool; hierarchical recognition,
 239 and makes the program exit after the &tool; recognition,
 240 the <f>-rp</f> option reduces transistors extracted in parallel.</p>
 241
 242 <p>The execution lasts a few seconds. Execution trace is displayed on the standard output,
 243 and should have this appearence:</p>
 244 <code>
 245 <cl>                                     @@@@            </cl>
 246 <cl>                                       @@            </cl>
 247 <cl>                                       @@            </cl>
 248 <cl>        @@@@@ @@@   @@@@      @@@@@@   @@     @@@@@  </cl>
 249 <cl>         @@    @   @@   @    @@  @@    @@    @     @ </cl>
 250 <cl>          @@   @   @@   @@   @   @@    @@   @@     @@</cl>
 251 <cl>          @@  @      @@@@@   @   @     @@   @@@@@@@@@</cl>
 252 <cl>           @@ @    @@   @@    @@@      @@   @@       </cl>
 253 <cl>           @@@    @@    @@   @@        @@   @@      @</cl>
 254 <cl>            @@    @@   @@@   @@@@@@    @@    @@    @@</cl>
 255 <cl>        @@  @      @@@@  @@ @@   @@@ @@@@@@    @@@@  </cl>
 256 <cl>        @@  @                @     @                 </cl>
 257 <cl>         @@@                  @@@@@                  </cl>
 258 <cl>      </cl>
 259 <cl>              Yet Another Gate Level Extractor</cl>
 260 <cl>      </cl>
 261 <cl>             AVERTEC CAD System 1.00, yagle 3.50</cl>
 262 <cl>             Copyright (c) 2000-2002,    AVERTEC</cl>
 263 <cl>             E-mail support: support@avertec.com</cl>
 264 <cl>      </cl>
 265 <cl>[YAG MES] Loading the figure ram4x128 </cl>
 266 <cl>[YAG MES] Transistor netlist checking </cl>
 267 <cl>[YAG MES] Hierarchical recognition    </cl>
 268 <cl>_________________________  FCL</cl>
 269 <cl>mem_cell:  512 found</cl>
 270 <cl>write_enable:  4 found</cl>
 271 <cl>precharge:  12 found</cl>
 272 <cl>sense_amp:  4 found</cl>
 273 <cl>sense_amp (sa2):  not found</cl>
 274 <cl> </cl>
 275 <cl>_________________________ GENIUS</cl>
 276 <cl>Building final instance list and executing C actions...</cl>
 277 <cl> </cl>
 278 <cl>_________________________  END</cl>
 279 <cl> 00m04s  u:00m03.4  M:9032Kb</cl>
 280 <cl> </cl>
 281 </code>
 282
 283 <p>Additionnal information is available by setting the
 284 <f> GnsTraceLevel</f> variable in the <f> avttools.conf</f>
 285 file to a higher level (up to level 6). Information can be redirected by setting the
 286 <f> GnsTraceFile</f> variable to a file name.</p>
 287
 288 <p>The execution generates four FCL report files: <f>mem_cell.fclins</f>, <f>write_enable.fclins</f>,
 289 <f>precharge.fclins</f> and <f>sense_amp.fclins</f>. Each of those files details the
 290 relationships between the recognized component and the netlist of ram4x128.</p>
 291
 292 <p>The generation of the FCL report files can be disabled by setting the <f>FclWriteReport</f> variable
 293 in the <f>avttools.conf</f> file to <f>no</f>.</p>
 294
 295
 296 </section>
 297
 298 </section>
 299 <last></last>
 300 <section niv='3'><title>Column of memory cells</title>
 301
 302 <p>The first of the hierarchical rules groups an arbitrary number of 'mem_cell' components into a column.</p>
 303 <imgsize namehtml="bitline_column.gif" namepdf="bitline_column.gif" hpdf="345pt" wpdf="368pt" />
 304 <p>The memory cells are grouped together when their ports <f>q</f> and <f>nq</f>
 305 are connected on the same signals <f>q</f> and <f>nq</f>.
 306 The directive <f>-- pragma symmetric q nq</f>
 307 placed in the 'mem_cell' rule allows the program to group two memory cells if the
 308 <f>q</f> port of the first one is connected on the same signal as the <f>nq</f>
 309 port of the second one, as illustrated in the figure above. The rule is described below,
 310 and refers to the file <f>column.vhd</f>.</p>
 311 <last></last>
 312 <code>
 313 <cl>ENTITY column IS</cl>
 314 <cl>  GENERIC (capacity: INTEGER);</cl>
 315 <cl>  PORT (q, nq: INOUT BIT;</cl>
 316 <cl>        com: IN BIT_VECTOR (0 TO capacity - 1);</cl>
 317 <cl>        vdd, vss: IN BIT</cl>
 318 <cl>  );</cl>
 319 <cl>  -- pragma symmetric q nq</cl>
 320 <cl>  -- pragma symmetric com</cl>
 321 <cl>END; </cl>
 322 <cl> </cl>
 323 <cl>ARCHITECTURE column OF column IS
 324 </cl>
 325 <cl>  COMPONENT mem_cell </cl>
 326 <cl>    PORT (q, nq: INOUT BIT; com, vdd, vss: IN BIT);</cl>
 327 <cl>  END COMPONENT; </cl>
 328 <cl> </cl>
 329 <cl>BEGIN</cl>
 330 <cl>  loop: FOR i IN 0 TO capacity - 1 GENERATE</cl>
 331 <cl>    mem_i: mem_cell</cl>
 332 <cl>      PORT MAP (q, nq, com (i), vdd, vss);</cl>
 333 <cl>  END GENERATE;</cl>
 334 <cl>END;</cl>
 335 </code>
 336 <p>This rule is generic, so it can match columns made of any number of memory cells. When the 'column' rule
 337 has been applied, the value of the generic 'capacity' is fixed by the number of occurencies of memory cells
 338 found by the rule. This value is then available for rules of higher level of hierarchy, instantiating
 339 the 'column' rule.</p>
 340 <p>The VHDL used to describe the structural rules in &tool; differs here slightly from IEEE-1067 VHDL.
 341 Actually, in GNS-VHDL, the value of a generic is computed at the lower level it appears, by counting
 342 the number of component occurencies in the <f>GENERATE</f> statement where the generic occurs.
 343 This value is transmitted via the <f>GENERIC MAP</f> statements to higher levels of hierarchy.</p>
 344 <p>To perform the recognition of the rule described above, edit the <f>LIBRARY</f> file,
 345 and uncomment the following line:</p>
 346
 347 <p><f>column.vhd;</f></p>
 348
 349 <p>Then type the command line <f> yagle -xg -rp ram4x128</f></p>
 350
 351 </section>
 352 <last></last>
 353 <section niv='3'><title>Column of memory cells with precharge and selector</title>
 354
 355 <p>The 'column_and_sel' rule groups a 'column' component, recognized by the preceding rule, together
 356 with a 'prechage' component and two transistors.</p>
 357 <imgsize namehtml="bitline_clmn_sel.gif" namepdf="bitline_clmn_sel.gif" hpdf="345pt" wpdf="368pt" />
 358 <p>The rule is described below and refers to the file <f>column_and_sel.vhd</f>.</p>
 359 <last></last>
 360 <code>
 361 <cl>ENTITY column_and_sel IS</cl>
 362 <cl>  GENERIC (capacity: INTEGER);</cl>
 363 <cl>  PORT (q, nq: INOUT BIT;</cl>
 364 <cl>        com: IN BIT_vector (0 TO capacity - 1);</cl>
 365 <cl>        ck, sel_column, vdd, vss: in BIT</cl>
 366 <cl>  );</cl>
 367 <cl>  -- pragma symmetric q nq</cl>
 368 <cl>  -- pragma symmetric com</cl>
 369 <cl>END; </cl>
 370 <cl> </cl>
 371 <cl>ARCHITECTURE sel_precharge OF column_and_sel IS </cl>
 372 <cl> </cl>
 373 <cl>  COMPONENT column </cl>
 374 <cl>    GENERIC (capacity: INTEGER);</cl>
 375 <cl>    PORT (q, nq: INOUT BIT; </cl>
 376 <cl>          com: in BIT_VECTOR (0 TO capacity - 1); </cl>
 377 <cl>          vdd, vss: IN BIT);</cl>
 378 <cl>  END COMPONENT;      </cl>
 379 <cl>  COMPONENT precharge</cl>
 380 <cl>    PORT (q, nq: INOUT BIT; ck: IN BIT; vdd: IN BIT);</cl>
 381 <cl>  END COMPONENT;</cl>
 382 <cl>  COMPONENT tn </cl>
 383 <cl>    PORT (grid: IN BIT; source, drain: INOUT BIT); </cl>
 384 <cl>  END COMPONENT; </cl>
 385 <cl> </cl>
 386 <cl>  SIGNAL a, na: BIT; </cl>
 387 <cl> </cl>
 388 <cl>BEGIN</cl>
 389 <cl>  col: column </cl>
 390 <cl>    GENERIC MAP (capacity)</cl>
 391 <cl>    PORT MAP (a, na, com, vdd, vss);</cl>
 392 <cl>  prech: precharge PORT MAP (a, na, ck, vdd);</cl>
 393 <cl>  t1: tn PORT MAP (sel_column, a, q);</cl>
 394 <cl>  t2: tn PORT MAP (sel_column, na, nq);</cl>
 395 <cl>END;</cl>
 396 </code>
 397 <p>The <f>GENERIC MAP (capacity)</f>
 398 statement allows the program to extract the value of the generic 'capacity' computed by the preceding rule.</p>
 399 <p>To perform the recognition of the rule described above, edit the <f>LIBRARY</f> file, and
 400 uncomment the following line:</p>
 401
 402 <p><f>column_and_sel.vhd;</f></p>
 403
 404 <p>Then type the command line <f> yagle -xg -rp ram4x128</f></p>
 405
 406 </section>
 407 <last></last>
 408 <section niv='3'><title>Bit line</title>
 409
 410 <p>The 'bit_line' rule groups an undefined number of 'column_and_sel' components, recognized by
 411 the preceding rule, together with a 'sense amplifier' component, a 'write enable' component and
 412 a 'precharge' component.</p>
 413 <imgsize namehtml="bitline.gif" namepdf="bitline.gif" hpdf="345pt" wpdf="368pt" />
 414 <p>The 'bit_line' rule is described below and refers to the file <f>bit_line.vhd</f>.</p>
 415 <last></last>
 416 <code>
 417 <cl>ENTITY bit_line IS</cl>
 418 <cl>  GENERIC (capacity, nbcolumn: INTEGER);</cl>
 419 <cl>  PORT (din: IN BIT;</cl>
 420 <cl>        dout: OUT BIT;</cl>
 421 <cl>        com: in BIT_VECTOR (0 TO capacity - 1);</cl>
 422 <cl>        sel: in BIT_VECTOR (0 TO nbcolumn - 1);</cl>
 423 <cl>        wen, ck, cke, ckp, vdd, vss: IN BIT);</cl>
 424 <cl>  -- pragma symmetric com</cl>
 425 <cl>  -- pragma symmetric sel</cl>
 426 <cl>END; </cl>
 427 <cl> </cl>
 428 <cl>ARCHITECTURE bit_line OF bit_line IS </cl>
 429 <cl> </cl>
 430 <cl>  COMPONENT column_and_sel</cl>
 431 <cl>    GENERIC (capacity: INTEGER);</cl>
 432 <cl>    PORT (q, nq: INOUT BIT;</cl>
 433 <cl>          com: IN BIT_VECTOR (0 TO capacity - 1);</cl>
 434 <cl>          ck, sel_column, vdd, vss: IN BIT);</cl>
 435 <cl>  END COMPONENT;      </cl>
 436 <cl>  COMPONENT sense_amp </cl>
 437 <cl>    PORT (data, ndata: IN BIT;</cl>
 438 <cl>          cke, ckp: IN BIT;</cl>
 439 <cl>          dout: OUT BIT;</cl>
 440 <cl>          vdd, vss: IN BIT);</cl>
 441 <cl>  END COMPONENT;</cl>
 442 <cl>  COMPONENT write_enable</cl>
 443 <cl>    PORT (datain, wen: IN BIT;</cl>
 444 <cl>          q, nq: INOUT BIT;</cl>
 445 <cl>          vss, vdd: IN BIT);</cl>
 446 <cl>  END COMPONENT;</cl>
 447 <cl>  COMPONENT precharge</cl>
 448 <cl>    PORT (q, nq: INOUT BIT; ck, vdd: IN BIT);</cl>
 449 <cl>  END COMPONENT; </cl>
 450 <cl> </cl>
 451 <cl>  SIGNAL nq, q: BIT; </cl>
 452 <cl> </cl>
 453 <cl>BEGIN</cl>
 454 <cl>  loop: FOR i IN 0 TO nbcolumn - 1 GENERATE</cl>
 455 <cl>    column_sel_i: column_and_sel </cl>
 456 <cl>      GENERIC MAP (capacity)</cl>
 457 <cl>      PORT MAP (q, nq, com (0 TO capacity - 1), ck, sel (i),</cl>
 458 <cl>                vdd, vss);</cl>
 459 <cl>  END GENERATE;</cl>
 460 <cl>  sa: sense_amp PORT MAP (q, nq, cke, ckp, dout, vdd, vss);</cl>
 461 <cl>  wen: write_enable PORT MAP (din, wen, q, nq, vss, vdd);</cl>
 462 <cl>  prech: precharge PORT MAP (q, nq, ckp, vdd);</cl>
 463 <cl>END;</cl>
 464 </code>
 465 <p>The generic 'nbcolumn' is fixed by the number of occurencies of 'column_and_sel' components
 466 found by the 'bit_line' rule. The generic 'capacity' is extracted from the preceding rule by the
 467 <f> GENERIC MAP (capacity)</f> statement.
 468 To perform the recognition of the rule described above, edit the <f>LIBRARY</f> file, and
 469 uncomment the following line:</p>
 470
 471 <p><f>bit_line.vhd;</f></p>
 472
 473 <p>Type the command line <f> yagle -xg -rp ram4x128</f></p>
 474
 475 </section>
 476 </section>
 477 <pagebreak/>
 478 <section niv='2'><title>Recognition rules for a bank</title>
 479
 480 <p>A bank is made of an arbitrary number of bit-lines, as illustrated in the
 481 figure below.</p>
 482 <imgsize namehtml="half-ram.gif" namepdf="half-ram.gif" hpdf="237pt" wpdf="368pt" />
 483 <p>The rule 'bank', referring to the file <f>bank.vhd</f> introduces the
 484 generic 'size'. The value of this generic is computed by counting the number
 485 of occurencies of the component 'bit_line' matching the rule in the design.
 486 For instance, the rule says that bit-lines are grouped together if and only if
 487 the ports <f>com</f>, <f>sel</f>, <f>write</f>, <f>ck</f>, <f>cke</f> and <f>ckp</f> of
 488 each bit-line instance are respectively connected to the entity ports <f>com</f>, <f>sel</f>,
 489 <f>write</f>, <f>ck</f>, <f>cke</f> and <f>ckp</f>.</p>
 490 <p>The values of the generics 'capacity' and
 491 'nbcolumn' are obtained through the <f>GENERIC MAP</f> statement.</p>
 492 <last> </last>
 493 <code>
 494 <cl>ENTITY bank IS</cl>
 495 <cl>  GENERIC (size, capacity, nbcolumn: INTEGER);</cl>
 496 <cl>  PORT (din: IN BIT_VECTOR (size - 1 DOWNTO 0);</cl>
 497 <cl>        dout: OUT BIT_VECTOR (size - 1 DOWNTO 0);</cl>
 498 <cl>        com: IN BIT_VECTOR (0 TO capacity - 1);</cl>
 499 <cl>        sel: IN BIT_VECTOR (0 TO nbcolumn - 1);</cl>
 500 <cl>        write, ck, cke, ckp, vdd, vss: IN bit);</cl>
 501 <cl>  -- pragma symmetric com</cl>
 502 <cl>  -- pragma symmetric sel</cl>
 503 <cl>END; </cl>
 504 <cl> </cl>
 505 <cl>ARCHITECTURE bank OF bank IS </cl>
 506 <cl> </cl>
 507 <cl>  COMPONENT bit_line </cl>
 508 <cl>    GENERIC (capacity, nbcolumn: INTEGER);</cl>
 509 <cl>    PORT (data_in: IN bit;</cl>
 510 <cl>          data_out: OUT bit;</cl>
 511 <cl>          com: IN BIT_VECTOR (0 TO capacity - 1);</cl>
 512 <cl>          sel: IN BIT_VECTOR (0 TO nbcolumn - 1);</cl>
 513 <cl>          write, ck, cke, ckp, vdd, vss: IN bit);</cl>
 514 <cl>  END COMPONENT; </cl>
 515 <cl> </cl>
 516 <cl>BEGIN</cl>
 517 <cl>  loop: FOR i IN 0 TO size - 1 GENERATE</cl>
 518 <cl>    bit_line_i: bit_line </cl>
 519 <cl>      GENERIC MAP (capacity, nbcolumn)</cl>
 520 <cl>      PORT MAP (din (i), dout (i),</cl>
 521 <cl>                com (0 to capacity - 1),</cl>
 522 <cl>                sel (0 to nbcolumn - 1),</cl>
 523 <cl>                write, ck, cke, ckp,</cl>
 524 <cl>                vdd, vss);</cl>
 525 <cl>  END GENERATE;</cl>
 526 <cl>END;</cl>
 527 </code>
 528 <p>To perform the recognition of the rule described above, edit the <f>LIBRARY</f> file, and uncomment
 529 the following line:</p>
 530
 531 <p><f>bank.vhd;</f></p>
 532
 533 <p>Then type the command <f>yagle -xg -rp ram4x128</f>.</p>
 534 <p>As a RAM instantiates two banks, &tool; identifies two occurencies of of the rule 'bank',
 535 and the following message should be displayed on the standard output:</p>
 536 <last> </last>
 537 <code>
 538 <cl>                                     @@@@            </cl>
 539 <cl>                                       @@            </cl>
 540 <cl>                                       @@            </cl>
 541 <cl>        @@@@@ @@@   @@@@      @@@@@@   @@     @@@@@  </cl>
 542 <cl>         @@    @   @@   @    @@  @@    @@    @     @ </cl>
 543 <cl>          @@   @   @@   @@   @   @@    @@   @@     @@</cl>
 544 <cl>          @@  @      @@@@@   @   @     @@   @@@@@@@@@</cl>
 545 <cl>           @@ @    @@   @@    @@@      @@   @@       </cl>
 546 <cl>           @@@    @@    @@   @@        @@   @@      @</cl>
 547 <cl>            @@    @@   @@@   @@@@@@    @@    @@    @@</cl>
 548 <cl>        @@  @      @@@@  @@ @@   @@@ @@@@@@    @@@@  </cl>
 549 <cl>        @@  @                @     @                 </cl>
 550 <cl>         @@@                  @@@@@                  </cl>
 551 <cl>      </cl>
 552 <cl>              Yet Another Gate Level Extractor</cl>
 553 <cl>      </cl>
 554 <cl>             AVERTEC CAD System 1.00, yagle 3.50</cl>
 555 <cl>             Copyright (c) 2000-2002,    AVERTEC</cl>
 556 <cl>             E-mail support: support@avertec.com</cl>
 557 <cl> </cl>
 558 <cl>[YAG MES] Loading the figure ram4x128  </cl>
 559 <cl>[YAG MES] Transistor netlist checking  </cl>
 560 <cl>[YAG MES] Hierarchical recognition                </cl>
 561 <cl>_________________________  FCL   </cl>
 562 <cl>mem_cell:  512 found</cl>
 563 <cl>write_enable:  4 found</cl>
 564 <cl>inv:  163 found</cl>
 565 <cl>nand2:  43 found</cl>
 566 <cl>precharge:  12 found</cl>
 567 <cl>sense_amp:  4 found</cl>
 568 <cl>sense_amp (sa2):  not found</cl>
 569 <cl> </cl>
 570 <cl>_________________________ GENIUS </cl>
 571 <cl>tree:  2 found</cl>
 572 <cl>tree2:  2 found</cl>
 573 <cl>tree_command:  1 found</cl>
 574 <cl>column:  8 found   (capacity = 64)</cl>
 575 <cl>column_and_sel:  8 found</cl>
 576 <cl>n_column:  4 found   (nbcolumn = 2)</cl>
 577 <cl>bank:  2 found   (size = 2)</cl>
 578 <cl>Building final instance list and executing C actions...</cl>
 579 <cl> </cl>
 580 <cl>_________________________  END   </cl>
 581 <cl> 00m03s  u:00m02.2  M:9464Kb</cl>
 582 </code>
 583
 584 </section>
 585 <pagebreak/>
 586 <section niv='2'><title>Recognition rules for the matrix</title>
 587 <section niv='3'><title>Buffers</title>
 588 <p>The matrix has the following structure, where the two
 589 banks have already been recognized.</p>
 590 <imgsize namehtml="ram_buffers.gif" namepdf="ram_buffers.gif" hpdf="308pt" wpdf="368pt" />
 591 <p>The rule we must write to recognize the matrix may describe the interconnection
 592 of the two banks and of the components constituting the command buffers. As we can see
 593 from the figure above, the description at the transistor level of all the command buffers
 594 is a quite tedious task, and we feel more comfortable with describing intermediary levels
 595 of hierarchy, such as nand and inverter cells. The rules identifying these cells are described in
 596 sections 4.4.1.a and 4.4.1.b., referring to the files <f>inv.vhd</f> and <f>nand2.vhd</f>.</p>
 597
 598 <p>We will then be able to write much more easily the rules identifying the repetitive
 599 structures shown in the transparent grayscale boxes. These rules are described in the
 600 sections 4.4.1.c and 4.4.1.d, referring to the files <f>tree.vhd</f> and <f>tree2.vhd</f>.</p>
 601
 602 <pagebreak/>
 603 <section niv='4'><title>Inverter cell</title>
 604
 605 <code>
 606 <cl>ENTITY inv IS </cl>
 607 <cl>  PORT (i: IN BIT; o: OUT BIT; vdd, vss: IN BIT);</cl>
 608 <cl>END; </cl>
 609 <cl> </cl>
 610 <cl>ARCHITECTURE inverter OF inv IS </cl>
 611 <cl> </cl>
 612 <cl>  COMPONENT tp </cl>
 613 <cl>    PORT (grid: IN BIT; source, drain: INOUT BIT); </cl>
 614 <cl>  END COMPONENT; </cl>
 615 <cl>  COMPONENT tn </cl>
 616 <cl>    PORT (grid: IN BIT; source, drain: INOUT BIT); </cl>
 617 <cl>  END COMPONENT; </cl>
 618 <cl> </cl>
 619 <cl>BEGIN</cl>
 620 <cl>  n0: tn PORT MAP (i, vss, o);</cl>
 621 <cl>  p0: tp PORT MAP (i, vdd, o);</cl>
 622 <cl>END;</cl>
 623 </code>
 624
 625 </section>
 626 <section niv='4'><title>Nand cell</title>
 627
 628 <code>
 629 <cl>ENTITY nand2 IS</cl>
 630 <cl>  PORT (i1, i2: IN BIT;</cl>
 631 <cl>        o: OUT BIT;</cl>
 632 <cl>        vdd, vss: IN BIT);</cl>
 633 <cl>  -- pragma symmetric i1 i2</cl>
 634 <cl>END; </cl>
 635 <cl> </cl>
 636 <cl>ARCHITECTURE nand2 OF nand2 IS </cl>
 637 <cl> </cl>
 638 <cl>  COMPONENT tp </cl>
 639 <cl>    PORT (grid: IN BIT; source, drain: INOUT BIT); </cl>
 640 <cl>  END COMPONENT;</cl>
 641 <cl>  COMPONENT tn </cl>
 642 <cl>    PORT (grid: IN BIT; source, drain: INOUT BIT); </cl>
 643 <cl>  END COMPONENT;</cl>
 644 <cl> </cl>
 645 <cl>  SIGNAL s: BIT; </cl>
 646 <cl> </cl>
 647 <cl>begin</cl>
 648 <cl>  tp0: tp PORT MAP (i1, vdd, o);</cl>
 649 <cl>  tp1: tp PORT MAP (i2, vdd, o);</cl>
 650 <cl>  tn0: tn PORT MAP (i1, s, o);</cl>
 651 <cl>  tn1: tn PORT MAP (i2, vss, s);</cl>
 652 <cl>END;</cl>
 653 </code>
 654
 655 </section>
 656 <last></last>
 657 <section niv='4'><title>Tree</title>
 658
 659 <code>
 660 <cl>ENTITY tree IS</cl>
 661 <cl>  PORT (i1, i2: IN BIT;</cl>
 662 <cl>        o1, o2: OUT BIT; vdd, vss: IN BIT);</cl>
 663 <cl>  -- pragma symmetric i1 i2</cl>
 664 <cl>  -- pragma symmetric o1 o2</cl>
 665 <cl>END; </cl>
 666 <cl> </cl>
 667 <cl>ARCHITECTURE tree OF tree IS </cl>
 668 <cl> </cl>
 669 <cl>  COMPONENT nand2</cl>
 670 <cl>    PORT (i1, i2: IN BIT; o: OUT BIT; vdd, vss: IN BIT);</cl>
 671 <cl>  END COMPONENT;</cl>
 672 <cl>  COMPONENT inv</cl>
 673 <cl>    PORT (i: IN BIT; o: OUT BIT; vdd, vss: IN BIT);</cl>
 674 <cl>  END COMPONENT; </cl>
 675 <cl> </cl>
 676 <cl>  SIGNAL s1, s2: BIT; </cl>
 677 <cl> </cl>
 678 <cl>BEGIN</cl>
 679 <cl>  na2_1: nand2 PORT MAP (i1, i2, s1, vdd, vss);</cl>
 680 <cl>  na2_2: nand2 PORT MAP (i1, i2, s2, vdd, vss);</cl>
 681 <cl>  i2_i: inv PORT MAP (s1, o1, vdd, vss);</cl>
 682 <cl>  i3_i: inv PORT MAP (s2, o2, vdd, vss);</cl>
 683 <cl>END;</cl>
 684 </code>
 685
 686 </section>
 687
 688 <section niv='4'><title>Another tree</title>
 689
 690 <code>
 691 <cl>ENTITY tree2 IS</cl>
 692 <cl>  PORT (i1, i2: IN BIT;</cl>
 693 <cl>        o1, o2: OUT BIT; vdd, vss: IN BIT);</cl>
 694 <cl>  -- pragma symmetric i1 i2</cl>
 695 <cl>  -- pragma symmetric o1 o2</cl>
 696 <cl>END; </cl>
 697 <cl> </cl>
 698 <cl>ARCHITECTURE tree2 OF tree2 IS </cl>
 699 <cl>  COMPONENT nand2</cl>
 700 <cl>    PORT (i1, i2: IN BIT; o: OUT BIT; vdd, vss: IN BIT);</cl>
 701 <cl>  END COMPONENT;</cl>
 702 <cl>  COMPONENT inv</cl>
 703 <cl>    PORT (i: IN BIT; o: OUT BIT; vdd, vss: IN BIT);</cl>
 704 <cl>  END COMPONENT; </cl>
 705 <cl> </cl>
 706 <cl>  SIGNAL nand_o: BIT; </cl>
 707 <cl> </cl>
 708 <cl>BEGIN</cl>
 709 <cl>  na2_1: nand2 PORT MAP (i1, i2, nand_o, vdd, vss);</cl>
 710 <cl>  i3_i: inv PORT MAP (nand_o, o2, vdd, vss);</cl>
 711 <cl>  i2_i_0: inv PORT MAP (nand_o, o1, vdd, vss);</cl>
 712 <cl>END;</cl>
 713 </code>
 714
 715 </section>
 716
 717
 718 <p>To perform the recognition of the 'inv', 'nand2', 'tree' and 'tree2' rules, edit the <f>LIBRARY</f>
 719 file, and uncomment the following lines:</p>
 720
 721 <code>
 722 <cl>inv.vhd;</cl>
 723 <cl>nand2.vhd;</cl>
 724 <cl>tree.vhd;</cl>
 725 <cl>tree2.vhd;</cl>
 726 </code>
 727
 728 <p>Note the recognition priority of the inverter rule: it must be recognized after any other rule containing inverter
 729 structures (the 'mem_cell' rule or the 'write_enable' rule for example).
 730 Otherwise, as the transistors recognized by the 'inverter' rule cannot belong to any other rule, a rule containing
 731 inverter structures cannot be matched.</p>
 732
 733 <p>Here, the priority is set by the occurence order of the rules in the LIBRARY file.</p>
 734
 735 <p>To perform the recognition, type the command line <f>yagle -xg -rp ram4x128</f></p>
 736 </section>
 737
 738 <last></last>
 739 <section niv='3'><title>Commands bufferization</title>
 740
 741 <p>The following figure illustrates the rule grouping the two
 742 'tree' components and the two 'tree2' components into a single
 743 commands bufferization component.</p>
 744 <imgsize namehtml="ram_commandbuf.gif" namepdf="ram_commandbuf.gif" hpdf="308pt" wpdf="368pt" />
 745 <p>This rule is described below, and refer to the file <f>tree_command.vhd</f>.</p>
 746 <last></last>
 747 <code>
 748 <cl>ENTITY tree_command IS</cl>
 749 <cl>  PORT (ck, write, en: IN BIT;</cl>
 750 <cl>        cken: INOUT BIT;</cl>
 751 <cl>        ck_0, ck_1,</cl>
 752 <cl>        cke_0, cke_1,</cl>
 753 <cl>        ckp_0, ckp_1,</cl>
 754 <cl>        wen_0, wen_1: OUT BIT;</cl>
 755 <cl>        vdd, vss: IN BIT);</cl>
 756 <cl>  -- pragma symmetric write_0 write_1</cl>
 757 <cl>  -- pragma symmetric ck_0 ck_1 ckp_0 ckp_1</cl>
 758 <cl>  -- pragma symmetric cke_0 cke_1</cl>
 759 <cl>END; </cl>
 760 <cl> </cl>
 761 <cl>ARCHITECTURE tc OF tree_command IS </cl>
 762 <cl> </cl>
 763 <cl>  COMPONENT tree</cl>
 764 <cl>    PORT (i1, i2: IN BIT;</cl>
 765 <cl>          o1, o2: OUT BIT;</cl>
 766 <cl>          vdd, vss: IN BIT);</cl>
 767 <cl>  END COMPONENT;</cl>
 768 <cl>  COMPONENT tree2</cl>
 769 <cl>    PORT (i1, i2: IN BIT;</cl>
 770 <cl>          o1, o2: OUT BIT;</cl>
 771 <cl>          vdd, vss: IN BIT);</cl>
 772 <cl>  END COMPONENT;</cl>
 773 <cl>  COMPONENT nand2</cl>
 774 <cl>    PORT (i1, i2: IN BIT; o: OUT BIT; vdd, vss: IN BIT);</cl>
 775 <cl>  END COMPONENT;</cl>
 776 <cl>  COMPONENT inv</cl>
 777 <cl>     PORT (i: IN BIT; o: OUT BIT; vdd, vss: IN BIT);</cl>
 778 <cl>  END COMPONENT; </cl>
 779 <cl> </cl>
 780 <cl>  SIGNAL n, n_0, n_1: BIT;</cl>
 781 <cl>  SIGNAL ncke_0, ncke_1: BIT; </cl>
 782 <cl> </cl>
 783 <cl>BEGIN</cl>
 784 <cl>  na2_0: nand2 PORT MAP (en, ck, n, vdd, vss);</cl>
 785 <cl>  inv_2: inv PORT MAP (n, cken, vdd, vss);</cl>
 786 <cl>  inv_3: inv PORT MAP (cken, n_0, vdd, vss);</cl>
 787 <cl>  inv_4: inv PORT MAP (cken, n_1, vdd, vss);</cl>
 788 <cl>  ckp: tree PORT MAP (n_0, n, ckp_0, ckp_1, vdd, vss);</cl>
 789 <cl>  ck: tree PORT MAP (n_1, n, ck_0, ck_1, vdd, vss);</cl>
 790 <cl>  ck_0: tree2 PORT MAP (write, cken, wen_0, ncke_0, vdd, vss);</cl>
 791 <cl>  ck_1: tree2 PORT MAP (write, cken, wen_1, ncke_1, vdd, vss);</cl>
 792 <cl>  inv_6: inv PORT MAP (ncke_0, cke_0, vdd, vss);</cl>
 793 <cl>  inv_7: inv PORT MAP (ncke_1, cke_1, vdd, vss);</cl>
 794 <cl>END;</cl>
 795 </code>
 796 <p>To perform the recognition of the rule 'tree_command', edit the <f>LIBRARY</f> file
 797 and uncomment the following line:</p>
 798
 799 <p><f>tree_command.vhd;</f></p>
 800
 801 <p>Then type the command line <f>yagle -xg -rp ram4x128</f></p>
 802
 803 </section>
 804 <section niv='3'><title>Matrix</title>
 805
 806
 807 <p>The highest-level hierarchical rule 'matrix' groups the two banks, the
 808 commands bufferization component, together with inverters bufferizing the
 809 signal <f>ncom</f>.</p>
 810
 811 <p>As shown in the figure below, the number of inverters is equal to two times the
 812 size of the vector <f>ncom</f>, i.e. <f>2 * capacity</f>.</p>
 813
 814 <imgsize namehtml="ram.gif" namepdf="ram.gif" hpdf="308pt" wpdf="369pt" />
 815
 816 <p>The rule 'matrix' is described below, and refers to the file 'matrix.vhd'.</p>
 817
 818 <last></last>
 819
 820 <code>
 821 <cl>ENTITY matrix IS</cl>
 822 <cl>  GENERIC (size, capacity, nbcolumn: INTEGER);</cl>
 823 <cl>  PORT (din: IN BIT_VECTOR (2 * size - 1 DOWNTO 0);</cl>
 824 <cl>        dout: OUT BIT_VECTOR (2 * size - 1 DOWNTO 0);</cl>
 825 <cl>        ncom: IN BIT_VECTOR (0 TO capacity - 1);</cl>
 826 <cl>        sel: IN BIT_VECTOR (0 TO nbcolumn - 1);</cl>
 827 <cl>        write, ck, en: IN BIT; cken: INOUT BIT;</cl>
 828 <cl>        cke, wen: INOUT BIT_vector (0 to 1); </cl>
 829 <cl>        vdd, vss: IN BIT);</cl>
 830 <cl>END; </cl>
 831 <cl> </cl>
 832 <cl>ARCHITECTURE matrix OF matrix IS </cl>
 833 <cl>  COMPONENT bank </cl>
 834 <cl>    GENERIC (size, capacity, nbcolumn: INTEGER);</cl>
 835 <cl>    PORT (din: IN BIT_VECTOR (size - 1 DOWNTO 0);</cl>
 836 <cl>          dout: OUT BIT_VECTOR (size - 1 DOWNTO 0);</cl>
 837 <cl>          com: IN BIT_VECTOR (0 TO capacity - 1);</cl>
 838 <cl>          sel: IN BIT_VECTOR (0 TO nbcolumn - 1);</cl>
 839 <cl>          write, ck, cke, ckp, vdd, vss: IN BIT);</cl>
 840 <cl>  END COMPONENT;</cl>
 841 <cl>  COMPONENT tree_command</cl>
 842 <cl>    PORT (ck, write, en: IN BIT;</cl>
 843 <cl>          cken: INOUT BIT;</cl>
 844 <cl>          ck_0, ck_1, cke_0, cke_1, ckp_0, ckp_1,</cl>
 845 <cl>          write_0, write_1: OUT BIT; vdd, vss: IN BIT);</cl>
 846 <cl>  END COMPONENT;</cl>
 847 <cl>  COMPONENT inv</cl>
 848 <cl>    PORT (i: IN BIT; o: OUT BIT; vdd, vss: IN BIT);</cl>
 849 <cl>  END COMPONENT; </cl>
 850 <cl> </cl>
 851 <cl>  SIGNAL com0, com1: BIT_VECTOR (0 to capacity - 1);</cl>
 852 <cl>  SIGNAL ckb, ckp: BIT_VECTOR (0 to 1); </cl>
 853 <cl> </cl>
 854 <cl>BEGIN</cl>
 855 <cl>  bank0: bank</cl>
 856 <cl>    GENERIC MAP (size, capacity, nbcolumn)</cl>
 857 <cl>    PORT MAP (din (2 * size - 1 downto size),</cl>
 858 <cl>              dout (2 * size - 1 downto size),</cl>
 859 <cl>              com0, sel, wen (0), ckb (0),</cl>
 860 <cl>              cke (0), ckp (0), vdd, vss);</cl>
 861 <cl>  bank1: bank</cl>
 862 <cl>    GENERIC MAP (size, capacity, nbcolumn)</cl>
 863 <cl>    PORT MAP (din (size - 1 DOWNTO 0),</cl>
 864 <cl>              dout (size - 1 DOWNTO 0),</cl>
 865 <cl>              com1, sel, wen (1), ckb (1),</cl>
 866 <cl>              cke (1), ckp (1), vdd, vss);</cl>
 867 <cl>  tree_com: tree_command</cl>
 868 <cl>    PORT MAP (ck, write, en, cken,</cl>
 869 <cl>              ckb (0), ckb (1), cke (0), cke (1),</cl>
 870 <cl>              ckp (0), ckp (1), wen (0), wen (1), vdd, vss);</cl>
 871 <cl>  loop_com: FOR i IN 0 TO capacity - 1 GENERATE</cl>
 872 <cl>    inv_0: inv PORT MAP (ncom (i), com0 (i), vdd, vss);</cl>
 873 <cl>    inv_1: inv PORT MAP (ncom (i), com1 (i), vdd, vss);</cl>
 874 <cl>  END GENERATE;</cl>
 875 <cl>END;</cl>
 876 </code>
 877 <p>To perform the recognition of the rule 'matrix', edit the <f>LIBRARY</f> file
 878 and uncomment the following lines:</p>
 879
 880 <p><f>matrix.vhd;</f></p>
 881
 882 <p>Then type the command line <f>yagle -xg -rp ram4x128</f></p>
 883 <p>The trace displayed on the standard output tells you that the matrix has been recognized:</p>
 884 <code>
 885 <cl>                                      @@@@            </cl>
 886 <cl>                                        @@            </cl>
 887 <cl>                                        @@            </cl>
 888 <cl>         @@@@@ @@@   @@@@      @@@@@@   @@     @@@@@  </cl>
 889 <cl>          @@    @   @@   @    @@  @@    @@    @     @ </cl>
 890 <cl>           @@   @   @@   @@   @   @@    @@   @@     @@</cl>
 891 <cl>           @@  @      @@@@@   @   @     @@   @@@@@@@@@</cl>
 892 <cl>            @@ @    @@   @@    @@@      @@   @@       </cl>
 893 <cl>            @@@    @@    @@   @@        @@   @@      @</cl>
 894 <cl>             @@    @@   @@@   @@@@@@    @@    @@    @@</cl>
 895 <cl>         @@  @      @@@@  @@ @@   @@@ @@@@@@    @@@@  </cl>
 896 <cl>         @@  @                @     @                 </cl>
 897 <cl>          @@@                  @@@@@                  </cl>
 898 <cl>      </cl>
 899 <cl>               Yet Another Gate Level Extractor</cl>
 900 <cl>      </cl>
 901 <cl>              AVERTEC CAD System 1.00, yagle 3.50</cl>
 902 <cl>              Copyright (c) 2000-2002,    AVERTEC</cl>
 903 <cl>              E-mail support: support@avertec.com</cl>
 904 <cl>      </cl>
 905 <cl>[YAG MES] Loading the figure ram4x128  </cl>
 906 <cl>[YAG MES] Transistor netlist checking  </cl>
 907 <cl>[YAG MES] Hierarchical recognition                </cl>
 908 <cl>_________________________  FCL   </cl>
 909 <cl>mem_cell:  512 found</cl>
 910 <cl>write_enable:  4 found</cl>
 911 <cl>inv:  163 found</cl>
 912 <cl>nand2:  43 found</cl>
 913 <cl>precharge:  12 found</cl>
 914 <cl>sense_amp:  4 found</cl>
 915 <cl>sense_amp (sa2):  not found</cl>
 916 <cl> </cl>
 917 <cl>_________________________ GENIUS </cl>
 918 <cl>tree:  2 found</cl>
 919 <cl>tree2:  2 found</cl>
 920 <cl>tree_command:  1 found</cl>
 921 <cl>column:  8 found   (capacity = 64)</cl>
 922 <cl>column_and_sel:  8 found</cl>
 923 <cl>n_column:  4 found   (nbcolumn = 2)</cl>
 924 <cl>bank:  2 found   (size = 2)</cl>
 925 <cl>matrix:  1 found</cl>
 926 <cl>Building final instance list and executing C actions...</cl>
 927 <cl> </cl>
 928 <cl>_________________________  END   </cl>
 929 <cl> 00m02s  u:00m02.4  M:9520Kb</cl>
 930 <cl>------------------------------------------------------</cl>
 931 <cl>[YAG MES] Execution COMPLETED </cl>
 932 <cl>------------------------------------------------------</cl>
 933 <cl>[YAG WAR 06] 312 transistors connected as parallel pairs</cl>
 934 <cl>See file 'ram4x128.rep' for more information</cl>
 935 </code>
 936
 937 <p>To generate a hierarchical netlist containing the matrix and the unmatched transistors, edit
 938 the <f>LIBRARY</f> file, recomment the line:</p>
 939
 940 <p><f>/* matrix.vhd; */</f></p>
 941
 942 <p>and uncomment the line:</p>
 943
 944 <p><f>matrix.vhd: keep = yes;</f></p>
 945
 946 <p>The option <f>keep = yes</f> tells &tool; to cut the structure recognized by the 'matrix' rule
 947 in the 'ram4x128' netlist. Therefore &tool; will create a hierarchical structural
 948 entity, instantiating two components: the recognized structure (the matrix) and a component constituted of
 949 the remaining transistors (the ones that haven't been matched by any rule).</p>
 950
 951 <p>The name of the hierarchical structural entity is the name of the radix of the flat transistor
 952 netlist (<f>ram4x128</f>), to which is appended the suffix <f>_yagroot</f>: <f>ram4x128_yagroot</f>.
 953 The corresponding generated file, in VHDL format, is <f>ram4x128_yagroot.vhd</f>.
 954 In SPICE format, it is <f>ram4x128_yagroot.spi</f></p>
 955
 956 <p>The name of the recognized structure is the name of the highest-level recognition rule ('matrix'),
 957 followed by the computed
 958 values of the generics: <f>matrix_2_64_2</f>. The description of this component is not automatic, as it is
 959 associated with a user-defined rule (the 'matrix' rule). Actually, the description of the component must be done
 960 by the action associated with the 'matrix' rule. For we are, for the moment, only interested in structural recognition,
 961 we will use the simple action described in the files <f>matrix_vhdl.c</f> or <f>matrix_spice.c</f>.
 962 This actions generate but the interface of the component <f>matrix</f>, respectively in VHDL or SPICE format.
 963 Note that it is possible to generate almost everything with an action, for it is a C program executed
 964 by &tool;.</p>
 965
 966 <p>The name of the component containing the unmatched transistor is the name of the radix of the flat
 967 transistor netlist (<f>ram4x128</f>), to which is appended the suffix <f>_yagcore</f>: <f>ram4x128_yagcore</f>.
 968 The corresponding generated file, in VHDL format, is <f>ram4x128_yagcore.vhd</f>.
 969 In SPICE format, it is <f>ram4x128_yagcore.spi</f></p>
 970
 971 <p>Now let's generate the hierarchical netlist <f>ram4x128_yagroot</f>, the component <f>ram4x128_yagcore</f>
 972 and the component <f>matrix_2_64_2</f>. If you want to have netlists in VHDL
 973 format, set <f>avtOutputNetlistFormat</f> to <f>vhd</f> in the <f>avttools.conf</f> file,
 974 edit the <f>LIBRARY</f> file and uncomment the line:</p>
 975
 976 <p><f>matrix_vhdl.c;</f></p>
 977
 978 <p>If you want to have netlists in SPICE format, set <f>avtOutputNetlistFormat</f> to <f>vhd</f> in the
 979 <f>avttools.conf</f> file, edit the <f>LIBRARY</f> file and uncomment the line:</p>
 980
 981 <p><f>matrix_spice.c;</f></p>
 982
 983 <p>Then type the command line <f>yagle -xg -rp ram4x128</f></p>
 984
 985 <p>Note that, as VHDL can not describe transistor level netlists, it is preferable to generate the files in SPICE
 986 format.</p>
 987
 988 </section>
 989 </section>
 990 </section></chapter>