distrib/docxml2/text/doc/gns_tutorial/validation.xml

   1 <?xml version="1.0" encoding="ISO-8859-1" ?>
   2 <chapter>
   3 <section niv='1'><title>&tool; in the validation flow</title>
   4 <section niv='2'><title>Structural validation</title>
   5
   6
   7 <p>The structural validation performed by &tool; is based upon the
   8 recognition of user-defined structural rules. These rules are in fact VHDL structural
   9 descriptions of elements of the RAM. The validation is then performed by finding
  10 occurencies of these structural descriptions in the transistor netlist.</p>
  11
  12 <p>The rules may be either transistor-level rules or hierarchical rules.
  13 &tool; looks first for occurencies of transistor-level rules, then
  14 for higher-level hierarchical rules, instantiating already recognized transistor level
  15 rules, or lower-level hierarchical rules. The number of hierarchical levels is not limited.</p>
  16
  17
  18 </section>
  19 <section niv='2'><title>Functional validation</title>
  20
  21
  22 <p>The functional validation is performed by generating the behavioral VHDL of
  23 the entire Random Access Memory. This VHDL is generated by two means:</p>
  24
  25 <p>When a behavioral VHDL is associated with a structural rule, each occurence
  26 in the transistor netlist, of the pattern matching the structural rule, is replaced by the behavioral VHDL.</p>
  27
  28 <p>When all the rules have been applied, &tool; generates automatically
  29 a behavioral VHDL for the transistors which remain unmatched.</p>
  30
  31 <p>The generated VHDL may then be either flat or hierarchical. The VHDL is flat
  32 when all the transistors have been matched by a rule, and when a behavioral description
  33 has been associated with the highest-level structural rule. The VHDL is hierarchical when
  34 some transistors have not been matched. In this case, a top-level structural VHDL,
  35 instantiating the automatically generated behavioral VHDL, and the behavioral VHDLs associated with
  36 the structural rules, is created.</p>
  37
  38 </section>
  39 <section niv='2'><title>Validation strategy for the generated RAMs</title>
  40
  41
  42 <p>As stated in chapter 2, a RAM is constituted of two banks connected together with buffers,
  43 and of a decoder cell. The two banks, together with the buffers, form what we call the matrix.
  44 We propose here to perform the structural validation of the matrix,
  45 and the functional validation of the entire RAM.</p>
  46
  47 <p>In order to perform the structural validation of the matrix,
  48 we will write a set of rules describing the hierarchy of a block formed of the two banks, and of the buffers
  49 connecting them together.</p>
  50
  51 <p>In order to perform the functional validation, we will associate a behavioral description
  52 with the top-level rule of this hierarchy. The remaining transistors - the transistors
  53 of the decoder - will be automatically treated by &tool;, which will generate a behavioral VHDL.
  54 A structural hierarchical VHDL, which instantiates the matrix VHDL and the decoder VHDL, will be finally created.</p>
  55
  56 <p>The following diagram illustrates the generation of the behavioral VHDL of the entire RAM.</p>
  57
  58
  59 <imgsize namehtml="genius_flow.gif" namepdf="genius_flow.gif" hpdf="322pt" wpdf="420pt" />
  60 </section>
  61 </section></chapter>