distrib/docxml2/text/doc/hitas_reference/stoFormat.xml

   1 <?xml version="1.0" encoding="ISO-8859-1" ?>
   2
   3 <section niv='2'><title>STO - STA Output Format</title>
   4
   5 <p>The <f>.sto</f> file is an ASCII text file made up of six distinct sections. This file is generated by &tool; and is intended mainly for debugging purposes, since for most purposes, the setup and hold slacks given in the timing report are sufficient. The six sections are:</p>
   6 <list>
   7 <item>General header</item>
   8 <item>Clock Specifications</item>
   9 <item>Conditioned clock states</item>
  10 <item>Input connector switching windows </item>
  11 <item>Output connector switching windows</item>
  12 <item>Memory Signal switching windows</item>
  13 <item>Internal Signal switching windows</item>
  14 </list>
  15 <p>Apart from the general header, some of the sections may be omitted if they are of no relevance.</p>
  16
  17
  18
  19 <section niv='3'><title>Input Connector Switching Windows</title>
  20
  21 <p>This section gives the switching windows at the input connectors.</p>
  22 <p>The syntax is as follows:</p>
  23 <code>
  24 <cl>input connectors stability</cl>
  25 <cl>begin</cl>
  26 <cl>  &lt;input1&gt; [from &lt;phase&gt;]:</cl>
  27 <cl>    unstable &lt;value&gt;;</cl>
  28 <cl>    stable   &lt;value&gt;;</cl>
  29 <cl>        |    |</cl>
  30 <cl>        |    |</cl>
  31 <cl>  &lt;inputn&gt; [from &lt;phase&gt;]:</cl>
  32 <cl>    unstable &lt;value&gt;;</cl>
  33 <cl>    stable   &lt;value&gt;;</cl>
  34 <cl>end;</cl>
  35 </code>
  36
  37 </section>
  38
  39
  40 <section niv='3'><title>Memory Signals Switching Windows</title>
  41
  42 <p>This section specifies the switching windows at all memory signals.</p>
  43 <p>The syntax is as follows:</p>
  44 <code>
  45 <cl>memory nodes stability</cl>
  46 <cl>begin</cl>
  47 <cl>  &lt;node1&gt; [from &lt;phase&gt;]:</cl>
  48 <cl>    unstable &lt;value&gt;;</cl>
  49 <cl>    stable   &lt;value&gt;;</cl>
  50 <cl>        |    |</cl>
  51 <cl>        |    |</cl>
  52 <cl>  &lt;noden&gt; [from &lt;phase&gt;]:</cl>
  53 <cl>    unstable &lt;value&gt;;</cl>
  54 <cl>    stable   &lt;value&gt;;</cl>
  55 <cl>end;</cl>
  56 </code>
  57 <p>This section gives the switching windows calculated for all memory signals.</p>
  58
  59 </section>
  60
  61
  62 <section niv='3'><title>Internal Signals Switching Windows</title>
  63
  64 <p>This section specifies the switching windows at all internal signals, except memory signals.</p>
  65 <p>The syntax is as follows:</p>
  66 <code>
  67 <cl>internal nodes stability</cl>
  68 <cl>begin</cl>
  69 <cl>  &lt;node1&gt; [from &lt;phase&gt;]:</cl>
  70 <cl>    unstable &lt;value&gt;;</cl>
  71 <cl>    stable   &lt;value&gt;;</cl>
  72 <cl>        |    |</cl>
  73 <cl>        |    |</cl>
  74 <cl>  &lt;noden&gt; [from &lt;phase&gt;]:</cl>
  75 <cl>    unstable &lt;value&gt;;</cl>
  76 <cl>    stable   &lt;value&gt;;</cl>
  77 <cl>end;</cl>
  78 </code>
  79 <p>This section gives the switching windows calculated for all signals, except memory signals. If the analysis is performed on the timing path graph (the default), the section is empty. If the analysis is performed on the timing arcs graph, then the set includes all signals.</p>
  80
  81 </section>
  82
  83
  84 <section niv='3'><title>Output Connector Switching Windows</title>
  85
  86 <p>This section specifies the switching windows at the output connectors.</p>
  87 <p>The syntax is as follows:</p>
  88 <code>
  89 <cl>output connectors stability</cl>
  90 <cl>begin</cl>
  91 <cl>  &lt;output1&gt; [from &lt;phase&gt;]:</cl>
  92 <cl>    unstable &lt;value&gt;;</cl>
  93 <cl>    stable   &lt;value&gt;;</cl>
  94 <cl>        |    |</cl>
  95 <cl>        |    |</cl>
  96 <cl>  &lt;outputn&gt; [from &lt;phase&gt;]:</cl>
  97 <cl>    unstable &lt;value&gt;;</cl>
  98 <cl>    stable   &lt;value&gt;;</cl>
  99 <cl>end;</cl>
 100 </code>
 101 <p>This section gives the switching windows calculated for outputs. This is the data which is compared with the output connector constraints specified in the '.inf' file or in the Tcl script, to calculate the setup and hold slacks. Every output connector is specified explicitly.</p>
 102 <p>Note that, unlike the output specifications, it is the phase of origin which is given. The destination phase obviously cannot be deduced.</p>
 103
 104 </section>
 105 </section>
 106
 107