Initial version of donated sources by Avertec, 3.4p5.
[tas-yagle.git] / distrib / docxml2 / text / doc / hitas_tutorial / old / lab4_charac_initiation.xml
1 <?xml version="1.0" encoding="ISO-8859-1" ?>
2 <chapter>
3 <section niv='1'><title>Lab4. Characterization Initiation</title>
4 <p>This lab presents how &tool; performs characterization in LIB format upon a small combinational design and simple master-slave flip-flop (<f>msdp2_y</f>). This lab takes place in the directory <f>lab4_charac_initiation/</f></p>
5
6
7 <section niv='2'><title>Timing Abstraction upon combinational design</title>
8 <p>The timing abstraction configuration takes place in the
9 <f>comb_charac.tcl</f> script as follow:</p>
10 <glossary>
11 <row type='split'><article><f>avt_config tmaDtxInput yes</f></article>
12 <def>tells the tool to take input file in DTX format.</def></row>
13 </glossary>
14 <p>The timing abstraction is done through the command <f>tma_abstract</f>.</p>
15 <code>
16 <cl>set abs [tma_abstract $fig NULL]</cl>
17 <cl>lib_drivefile [list $abs] {} comb.lib max</cl>
18 </code>
19 </section>
20
21 <section niv='2'><title>Timing Abstraction upon flip-flop</title>
22 <p>The timing abstraction configuration takes place in the
23 <f>ms_charac.tcl</f> script as follow:</p>
24 <glossary>
25 <row type='split'><article><f>avt_config tmaDtxInput yes</f></article>
26 <def>tells the tool to take input file in DTX format.</def></row>
27 <row type='split'><article><f>inf_SetFigureName msdp2_y</f></article>
28 <def>tells the tool to apply the SDC constraints to the flip-flop design. </def></row>
29 <row type='split'><article><f>create_clock -period 1000 -waveform {500 0} ck</f></article>
30 <def>creates a clock on signal <f>ck</f></def></row>
31 </glossary>
32 <p>The timing abstraction is done through the command <f>tma_abstract</f>.</p>
33 <code>
34 <cl>set abs [tma_abstract $fig NULL]</cl>
35 <cl>lib_drivefile [list $abs] {} msdp2_y.lib max</cl>
36 </code>
37 </section>
38
39 </section>
40
41 </chapter>
42
43