1 <?xml version=
"1.0" encoding=
"ISO-8859-1" ?>
3 <section niv='
1'
><title>Lab6. Cpu2901
</title>
4 <section niv='
2'
><title>Design Description
</title>
5 <imgsize namehtml=
"amd2901.gif" namepdf=
"amd2901.gif" wpdf=
"340pt"/>
7 <section niv='
2'
><title>Database Generation
</title>
8 <section niv='
3'
><title>Global Configuration
</title>
9 <p>The complete configuration required for the database generation takes place in the
<f>script0_db.tcl
</f>. The script also launches the commands that effectively generate that database.
</p>
10 <p>Configuration variables are set in the Tcl script by the mean of the
<f>avt_config
</f> function.
</p>
12 <row type='split'
><article><f>avt_config tasGenerateDetailTimingFile yes
</f></article>
13 <def>tells the tool to dump on disk the
<f>.dtx
</f> file, which contains all the cones' timing arcs (otherwise the tool only dumps timing paths in the .ttx file).
</def></row>
14 <row type='split'
><article><f>avt_config tasExitAfterDetailTimingFile yes
</f></article>
15 <def>tells the tool to dump on disk only the
<f>.dtx
</f> file.
</def></row>
16 <row type='split'
><article><f>avt_config tasGenerateConeFile yes
</f></article>
17 <def>tells the tool to dump on disk the .cns file, which contains the partitions (the cones) created by the partitioning algorithm.
</def></row>
18 <row type='split'
><article><f>avt_config tasModelsForDelays scm_cpl
</f></article>
19 <def>tells the tool to dump on disk all the models used to compute cones' delays. Those models are dumped in the .stm file. Necessary when re-computation is needed, as in crosstalk analysis.
</def></row>
20 <row type='split'
><article><f>avt_config yagleAutomaticLatchDetection yes
</f></article>
21 <def>tells the tool to make a Boolean analysis of loops to detect memorizing elements.
</def></row>
23 <p>The temperature and supplies specifications take place in the
<f>cpu2901.spi
</f> file:
</p>
26 <cl>.GLOBAL vdd vss
</cl>
27 <cl>Vsupply vdd
0 DC
1.62</cl>
28 <cl>Vground vss
0 DC
0</cl>
30 <p>As the
<f>cpu2901.spi
</f> subcircuit is not instantiated, the
<f>vdd
</f> and
<f>vss
</f> signals appear in the
<f>.GLOBAL
</f>
34 <section niv='
3'
><title>Technology Integration
</title>
35 <p>In the present example, the avt_LoadFile command is used.
</p>
36 <code>avt_LoadFile ./bsim3_018.tech
</code>
39 <section niv='
3'
><title>Database Generation
</title>
40 <p>The generation launch is done through the command hitas:
</p>
42 <cl>avt_LoadFile cpu2901.spi
</cl>
43 <cl>set fig [hitas cpu2901]
</cl>
47 <section niv='
3'
><title>Exercises
</title>
49 <item>Ex
6.1. Check in the
<f>.rep
</f> file the supplies that have been detected
</item>
50 <item>Ex
6.2. Check in the
<f>.rep
</f> file the latches that have been detected
</item>
51 <item>Ex
6.3. Look at the latch nodes in the CNV file, identify data and commands.
</item>
52 <item>Ex
6.4. Configure the tool to mark master-slave in the
<f>.rep
</f> file
</item>
58 <section niv='
2'
><title>Database Analysis
</title>
59 <section niv='
3'
><title>Path Searching with the Tcl Interface
</title>
60 <p>The complete configuration required for the database browsing takes place in the
<f>script1_report.tcl
</f>.
</p>
62 <code>set fig [ttv_LoadSpecifiedTimingFigure cpu2901]
</code>
63 <p>reads the timing database from disk.
</p>
65 <code>set clist [ttv_GetPaths $fig * * uu
5 critic path max]
</code>
66 <p>gives the
5 most critical paths (
<f>critic
</f> and
<f>path
</f> arguments) of the design, that begin and end on a rising transition (
<f>uu
</f> argument), with no specification of signal name (
<f>* *
</f> arguments), in the database pointed out by
<f>$fig
</f>. The function returns a pointer on the newly created list.
</p>
68 <code>ttv_DisplayPathListDetail stdout $clist
</code>
69 <p>displays on the standard output the detail of all the paths of the path list given by the
<f>ttv_GetPaths
</f> function.
</p>
72 <section niv='
3'
><title>Exercises
</title>
73 <p>Ex
6.5 Find the most critical access time from connector
<f>ck
</f></p>
76 <section niv='
3'
><title>Path Searching with the GUI
</title>
77 <p>Database can also be accessed with the xtas GUI. To launch the GUI, type in command line:
</p>
79 <p>Open the database
<f>cpu2901.dtx
</f> and follow the same steps as for the adder.
</p>
84 <section niv='
2'
><title>Stability and Timing Constraints Checks
</title>
85 <p>The complete configuration required for stability analysis takes place in the
<f>script2_stb.tcl
</f>.
</p>
86 <section niv='
3'
><title>Stability with Tcl Interface
</title>
87 <section niv='
4'
><title>Timing Constraints
</title>
88 <p>Timing constraints are set in SDC format. Let's review the constraints commands applied to the cpu2901:
</p>
90 <row type='split'
><article><f>avt_config stbDetailedGraph yes
</f></article>
91 <def>Stability analysis on the detailed graph (.dtx file).
</def></row>
93 <row type='split'
><article><f>inf_SetFigureName cpu2901
</f></article>
94 <def> tells the tool to apply the SDC constraints to the design cpu2901.
</def></row>
96 <row type='split'
><article><f>create_clock -period
10000 -waveform {
5000 0} ck
</f></article>
97 <def>Creates of clock of period
10000</def></row>
99 <row type='split'
><article><f>inf_DefineConditionedCommandStates * noverif
</f></article>
100 <def>No check of the gated clocks for the moment
</def></row>
102 <row type='split'
><article><f>set_input_delay -min
2000 -clock ck -clock_fall [all_inputs]
</f></article>
104 <row type='split'
><article><f>set_input_delay -max
6500 -clock ck -clock_fall [all_inputs]
</f></article>
105 <def>Defines a switching window between times
2000 and
6500 on the input connectors
</def></row>
107 <row type='split'
><article><f>inf_Drive cpu2901
</f></article>
108 <def>Dumps on disk the timing constraints in Avertec's STB format (for GUI use)
</def></row>
113 <section niv='
4'
><title>Stability Analysis
</title>
114 <p>Launch of the stability analysis is done by invoking the following commands:
</p>
115 <p>As before, the command:
</p>
116 <code>set fig [ttv_LoadSpecifiedTimingFigure cpu2901]
</code>
117 <p>reads the timing database from disk.
</p>
119 <code>set stbfig [stb $fig]
</code>
120 <p>launches the stability analysis.
</p>
124 <section niv='
3'
><title>Exercises
</title>
126 <item>Ex
6.6. The stability analysis produces warning of the kind
"[STB WAR 101] No clock for the command ...". Try
127 to identify the cause by looking at timing paths to those commands (with the GUI).
</item>
128 <item>Ex
6.7. Generate the database with connector
<f>fonc
</f> stuck to
1 and connector
<f>test
</f> stuck to
0. Use
129 <f>inf_SetFigureName
</f> and
<f>set_case_analysis
</f>. Observe the REP file
</item>
130 <item>Ex
6.8. Perform a new stability analysis and observe the differences.
</item>
131 <item>Ex
6.9. Disable timing checks between masters and slave (
<f>set_false_path -setup / -hold
</f>).
</item>
135 <section niv='
3'
><title>Stability with the GUI
</title>
136 <section niv='
4'
><title>Timing Constraints
</title>
137 <p>In the case where the stability analysis is done from the GUI, the timing constraints must be set in a special file cpu2901.inf. This file is read at the start of the xtas GUI. Ass this file is generated with the Tcl command
<f>inf_Drive
</f>, it contains the same constraint information as in the Tcl script, in Avertec proprietary format STB.
</p>
140 <section niv='
4'
><title>GUI Launch
</title>
141 <p>To launch the GUI, type in command line:
</p>
143 <p>Open the database
<f>cpu2901.dtx
</f> from the menu:
</p>
144 <code>> File
> Open
</code>
145 <p>Load the INF file
<f>cpu2901.inf
</f> from the menu:
</p>
146 <code>> File
> Load an INF file
</code>
149 <section niv='
4'
><title>Stability Analysis
</title>
150 <p>Launch the stability analysis from the menu:
</p>
151 <code>> Tools
> Stability
</code>
152 <p>This will open the
"Stability Parameterization" window. Default configuration is sufficient to perform a first run.
</p>
153 <p>Clicking on OK in the
"Stability Parameterization" window launches the stability analysis. Once the algorithm has finished, the
"Stability Analysis Window" appears, reporting the timing violations.
</p>
154 <p>To observe the timing diagrams relative to a specific violation, select one in the list, and select the menu:
</p>
155 <code>Tools
> Debug Error
</code>
156 <p>This will open the
"Signal Selection" window, where the signal associated with the selected violation appears. Clicking on OK will make the
"Debug" window appear.
</p>
157 <p>This window displays the impact of each path of the fan-in of the violated-signal (the fan-in appears in the
"Input Signals List" list). Clicking on one the input signals will make appear the appropriate timing diagrams.
</p>
158 <p>To get details on the path associated with the timing diagram, select the menu:
</p>
159 <code>> Tools
> Get Paths
</code>
160 <p>Then select the path and select the menu:
</p>
161 <code>> Tools
> Path Details
</code>
166 <section niv='
3'
><title>Exercises
</title>
168 <item>Ex
6.10. Modify the
<f>set_input_delay
</f> to suppress violations.
</item>
174 <section niv='
2'
><title>Signal Integrity
</title>
175 <section niv='
3'
><title>Introduction
</title>
176 <p>Avertec's SI analysis computes the delta-delays and voltage peaks due to coupling capacitances, for all the signals in the design.
</p>
177 <p>SI analysis is based upon the propagation of switching windows. The tool uses switching windows intersections to detect real crosstalk aggressions situations. It then uses second-order charge transfer models to compute the impact of aggressors on delay and voltage-levels.
</p>
178 <p>The propagation engine is the same as the one used for the stability analysis and the configuration made for the stability analysis is still pertinent for the SI analysis.
</p>
179 <p>Furthermore, timing constraints are still taken into account, and the tool performs crosstalk-aware timing checks (setup/hold margins).
</p>
183 <section niv='
3'
><title>Signal Integrity with the Tcl Interface
</title>
184 <section niv='
4'
><title>SI Configuration
</title>
185 <p>The complete configuration required for SI analysis takes place in the
<f>script3_xtalk.tcl
</f>.
</p>
186 <p>The following additional variables are used to perform the crosstalk-aware stability analysis:
</p>
188 <row type='split'
><article><f>avt_config stbCrosstalkMode yes
</f></article>
189 <def>tells the tool to perform SI analysis.
</def></row>
190 <row type='split'
><article><f>avt_config stbDetailedGraph yes
</f></article>
191 <def>tells the tool to perform SI analysis on detailed graph.
</def></row>
192 <row type='split'
><article><f>avt_config stbDetailedAnalysis yes
</f></article>
193 <def>tells the tool not to merge switching windows when multiple ones appear on a single signal (unless they overlap). This configuration is more precise and less pessimistic.
</def></row>
197 <section niv='
4'
><title>SI Analysis
</title>
198 <p>Launch of the crosstalk-aware stability analysis is done by invoking the following commands:
</p>
200 <p>As before, the command:
</p>
201 <code>set fig [ttv_LoadSpecifiedTimingFigure adder]
</code>
202 <p>reads the timing database from disk.
</p>
204 <code>set stbfig [stb $fig]
</code>
205 <p>launches the stability analysis.
</p>
206 <p>When invoked in crosstalk mode, the stb function creates two additional files:
</p>
208 <item>adder.ctk reports human-readable delta-delays and voltage peaks
</item>
209 <item>adder.ctx contains the delta-delays for database use
</item>
213 <section niv='
4'
><title>Exercise
</title>
214 <p>Ex
6.11. Re-analyze timing paths with crosstalk information. Use
<f>ttv_LoadCrosstalkFile
</f> (this command reads the file
215 <f>adder.ctx
</f>, and back-annotates the database with crosstalk-induced delta-delay information.
</p>
218 <section niv='
4'
><title>Analyzing Voltage Peaks
</title>
219 <p>Not yet available in Tcl. Available in GUI.
</p>
224 <section niv='
3'
><title>Signal Integrity with the GUI
</title>
225 <section niv='
4'
><title>GUI Launch
</title>
226 <p>To launch the GUI, type in command line:
</p>
228 <p>Open the database adder.ttx from the menu:
</p>
229 <code>> File
> Open
</code>
232 <section niv='
4'
><title>SI Configuration
</title>
233 <p>To launch the SI analysis process, select in the menu:
</p>
234 <code>> Tools
> Stability Analysis
</code>
235 <p>(as said before, the SI analysis is based on the propagation of switching windows the stability analysis performs).
</p>
236 <p>This will open the
"Stability Parameterization" window. Clicking on the
"Crosstalk Analysis" checkbox will enable the advanced configuration checkboxes. Default configuration is sufficient to perform a first run.
</p>
239 <section niv='
4'
><title>SI Analysis
</title>
240 <p>Clicking on OK in the
"Stability Parameterization" window launches the analysis (iterations status is reported in the progress bar). Once iterations have converged, the
"Stability Analysis Results" window appears, reporting the timing violations.
</p>
241 <p>To observe the timing diagrams relative to a specific violation, select one in the list, and select the menu:
</p>
242 <code>> Tools
> Debug Error
</code>
243 <p>This will open the
"Signal Selection" window, where the signal associated with the selected violation appears. Clicking on OK will make the
"Debug" window appear.
</p>
244 <p>This window displays the impact of each path of the fan-in of the violated-signal (the fan-in appears in the
"Input Signals List" list). Clicking on one the input signals will make appear the appropriate timing diagrams.
</p>
247 <section niv='
4'
><title>Re-Analyzing Timing Paths
</title>
248 <p>To get details on the path associated with the timing diagram, select the menu:
</p>
249 <code>> Tools
> Get Paths
</code>
250 <p>Then select the path and select the menu:
</p>
251 <code>> Tools
> Path Details
</code>
252 <p>This time, the detail of the path is given with the contribution of the coupled signals.
</p>
255 <section niv='
4'
><title>Analyzing Voltage Peaks
</title>
256 <p>To access to voltage peaks report, from the
"<f>Stability Analysis Results</f>" window, select the menu:
</p>
257 <code>> Tools
> Noise Analysis.
</code>
258 <p>This will open the
"<f>Noise Analysis Results</f>" window.
</p>
259 <p>Voltage peaks are classified following a sum of four criteria, each criteria being attributed a score:
</p>
261 <item>Noise: ratio between the voltage peak and the minimum threshold of the fan-out gates.
</item>
262 <item>Interval: overlapping ratio between the selected signal and its aggressors
</item>
263 <item>Crosstalk: number of aggressors contributing to the voltage peak. The less aggressors there is, the higher is the score (as the voltage peak is due to a few aggressors, the situation is more likely to occur).
</item>
264 <item>Activity: estimation of the transition density of a signal. Clock signal value is
10, others signals' value is
0.
</item>
266 <p>The model box has either value
"scr" or
"cc". The value
"scr" stands for
"single constant resistor", and tells that the voltage peak is computed with drivers modeled as equivalent resistors. The value
"cc" stands for
"connector constant", and is applied when the driver is a connector. The voltage peak is computed with a default resistor value.
</p>
267 <p>To access detailed crosstalk information about a voltage peak on a signal, select the signal in the list, then select the menu:
</p>
268 <code>> View
> Crosstalk Info
</code>
269 <p>This will open the
"Crosstalk Info" window, in which appear all the aggressors of the signal, as well as their contribution to the voltage peak. The four letters B W R F specify:
</p>
270 <p>B: aggressor contributes to decrease delay
</p>
271 <p>W: aggressor contributes to increase delay
</p>
272 <p>R: aggressor contributes to voltage overshoot
</p>
273 <p>F: aggressor contributes to voltage undershoot
</p>
274 <p>All the information of the
"Noise Analysis Results" and
"Crosstalk Info" windows is also available in the CTK file.
</p>
projects / tas-yagle.git / blob