distrib/docxml2/text/doc/hitas_tutorial/old/lab8_blackbox.xml

   1 <?xml version="1.0" encoding="ISO-8859-1" ?>
   2 <chapter>
   3 <section niv='1'><title>Lab8. Sub-Circuit Blackboxing</title>
   4
   5 <section niv='2'><title>Objective</title>
   6 <p>&tool; is designed to compute propagation delays in digital designs. The advantage of this
   7 restrictive target is to enable very fast computing times. The drawback is that non-digital
   8 block characterization is not directly handled by &tool; and should be supplied to 3rd-party analog
   9 simulators. However, &tool; provides various ways to link with external characterizations.</p>
  10 <p>First, the tool provides the means to choose between integrating a pre-characterization (such as
  11 a .lib or .dtx file) and integrating an on-the-fly characterization (by piloting an analog
  12 simulator).</p>
  13 <p>The pre-characterization strategy is easier to set-up, but has the drawback to provide
  14 only one characterization for (potentially) several instances of an analog sub-circuit.
  15 The on-the-fly characterization is a little more difficult to set-up, but provides
  16 environment-dependant (PVT, input slopes, output loads) characterizations, and therefore greater
  17 accuracy.</p>
  18 <p>This lab presents an illustration of the pre-characterization strategy, i.e. the integration of
  19 a <f>.lib</f> file to replace an analog block.</p>
  20 </section> <!-- Objective -->
  21
  22 <section niv='2'><title>Pre-Characterization</title>
  23 <p>In this section, we present how to create a DTX file within a Tcl script, and how to get timing values
  24 from analog simulation results. We then present how to make a <f>.lib</f> file out of it, and how to integrate
  25 this pre-characterization in the top-level timing database construction.</p>
  26
  27 <p>Associated files:</p>
  28 <glossary>
  29 <row><article><f>rs_clock_gen.tcl</f></article><def>Timing database construction script</def></row>
  30 <row><article><f>rs_clock_gen_sim.tcl</f></article><def>Timing database construction and simulator linking script</def></row>
  31 <row><article><f>cmd_rs_clock_gen.chi</f></article><def>Simulator output file</def></row>
  32 </glossary>
  33
  34 <section niv='3'><title>Database Construction</title>
  35 <p>The API functions provided with the <f>avt_shell</f> Tcl interface enable the creation of custom timing
  36 databases (DTX files). Using of those functions is illustrated in the <f>rs_clock_gen.tcl</f> script.
  37 The script generates a timing database for a NAND-RS-based non-overlapping clocks generator
  38 (<f>rs_clock_gen</f> sub-circuit).</p>
  39
  40 <p>The <f>avt_GetNetlist</f> function is used in order to retrieve the netlist the timing figure
  41 will be based on.</p>
  42 <p>The <f>avt_FlattenNetlist</f> function flattens the netlist to the transistor level. The purpose
  43 of the flattening is to enable the database creation function (<f>ttv_CreateTimingFigure</f>) to computing
  44 capacitances for input and output connectors: the function has an easier access to the transistors
  45 participating to the global connector capacitance. Note that the transistors models are necessary
  46 for computing gate and source/drain capacitances.</p>
  47 <p>The <f>ttv_CreateTimingFigure</f> function creates the timing database itself. The function takes
  48 as argument the netlist of the <f>rs_clock_gen</f> sub-circuit, and builds the interface of the new timing
  49 database upon the interface of the
  50 netlist. If the new timing database is intended to replace an analog sub-circuit, it
  51 ensures interface consistency between the "hole" in the top-level netlist
  52 and the newly created timing database. Note that the Vdd and Vss names must be specified if they appear on the
  53 interface.</p>
  54
  55 <p>The <f>ttv_AddTiming</f> functions add timing arcs in the database.</p>
  56 <p>The <f>ttv_FinishTimingFigure</f> function updates the database.</p>
  57 <p>The <f>ttv_DriveTimingFigure</f> function prints the database on disk (DTX file).</p>
  58
  59 <p>Launching the <f>rs_clock_gen.tcl</f> script will result in the creation of the <f>rs_clock_gen.dtx</f>
  60 timing database.</p>
  61
  62 </section> <!-- Database Construction -->
  63
  64 <section niv='3'><title>Simulator Linking</title>
  65 <p>The <f>rs_clock_gen.tcl</f> script associates "hard" values to the delays and slopes given as
  66 parameters of the <f>ttv_AddTiming</f> function (timing arc creation). It
  67 is the responsibility of the user to associate pertinent values to the parameters of the
  68 <f>ttv_AddTiming</f> function, by all the ways Tcl scripting provides.</p>
  69 <p>However, the <f>avt_shell</f> Tcl interface also provides means to retrieve the values from
  70 analog simulations results. Provided functions cover:</p>
  71 <list>
  72 <item><p>Stimuli description and formatting:</p>
  73 <p><f>sim_AddInitLevel</f></p>
  74 <p><f>sim_AddInitLevel</f></p>
  75 <p><f>sim_AddWaveForm</f></p>
  76 </item>
  77 <item><p>Measure setting</p>
  78 <p><f>sim_AddSpiceMeasureDelay</f></p>
  79 <p><f>sim_AddSpiceMeasureSlope</f></p>
  80 </item>
  81 <item><p>Simulator call</p>
  82 <p><f>sim_RunSimulation</f></p>
  83 </item>
  84 <item><p>Result retrieving</p>
  85 <p><f>sim_GetSpiceMeasureDelay</f></p>
  86 <p><f>sim_GetSpiceMeasureSlope</f></p>
  87 </item>
  88 </list>
  89
  90 <p>Configuring and using the simulator linking features is illustrated in the <f>rs_clock_gen_sim.tcl</f>
  91 script.</p>
  92
  93 <p>Launching the <f>rs_clock_gen_sim.tcl</f> script will produce the following actions:</p>
  94 <list>
  95 <item>Creation of the set of sub-circuits to be simulated (<f>rs_clock_gen.spi</f>)</item>
  96 <item>Creation of <f>cmd_rs_clock_gen.spi</f>, file to be provided as input to the simulator.
  97 This file contains the formatted stimuli and measure
  98 directives, as well as an inclusion of <f>rs_clock_gen.spi</f>. The formatting of the measure directives
  99 is done through the <f>simToolModel</f> variable. This variable formats the SPICE deck accordingly to
 100 the simulator under usage.</item>
 101 <item>Launching of the simulator in a separate process according to the <f>$spice_string</f> variable.</item>
 102 <item>Waiting for the normal termination of the process (exit 1)</item>
 103 <item>Reading the results in the <f>cmd_rs_clock_gen.chi</f> simulator output file.
 104 The output file suffix is specified by the <f>simToolModel</f> variable</item>
 105 <item>Creation of the timing database, and printing on disk of the <f>rs_clock_gen.dtx</f> file.</item>
 106 <item>Creation of the <f>rs_clock_gen.lib</f> file.</item>
 107 </list>
 108
 109 </section> <!-- Simulator Linking -->
 110
 111 <section niv='3'><title>Integration in a Hierarchical Netlist (Pre-Layout)</title>
 112
 113 <glossary>
 114 <row><article><f>db.tcl</f></article><def>Timing database construction script, with integration of the pre-characterization.</def></row>
 115 </glossary>
 116
 117 <p>The first step to perform when integrating the pre-characterized <f>.lib</f> file within a hierarchical
 118 netlist is the blackboxing of the instances of the analog sub-circuits, in order to obtain
 119 "analog holes" in the netlist. This is done with the <f>avt_SetBlackBoxes</f> function, taking as
 120 argument the list of the sub-circuits to blackbox.</p>
 121
 122 <p>The default behavior of &tool; is not to try to fill the "holes". To tell the tool to fill the
 123 holes with timing characterizations, the <f>tasIgnoreBlackbox</f> variable is set to <f>yes</f> in the
 124 <f>db.tcl</f> script.</p>
 125
 126 <p>The timing arcs for the instances <f>rs_clock_gen</f> are directly integrated in the new database.
 127 The database for <f>sample</f> is flat and does not contain instances of <f>rs_clock_gen</f>.</p>
 128 </section> <!-- Hierarchical Netlist Integration (Pre-Layout) -->
 129
 130 </section> <!-- Analog Sub-circuit Characterization -->
 131 </section> <!-- Analog Sub-circuit Characterization -->
 132
 133
 134 </chapter>